Sessions Index

Bio:

Shun Mitarai received his B.E. and M.E. degrees from Tokyo Institute of Technology in 1994 and 1996, respectively.
He joined Sony Corporation in 1998, and engaged in the research and development of FeRAM, MEMS, IPD, mm-wave module, and various packaging substrate. He also has 13 years of experience in glass core substrate technology. Current his research interests include advanced packaging for image sensor and related devices.

Abstract:

The increasing size of package substrates presents various challenges, for which glass core substrates are considered a potential solution.

The conventional process (CP) for manufacturing glass core substrates, while maintaining large glass panels, is straightforward but requires significant investment for double-sided interconnect formation and extensive equipment modifications to handle the glass without breakage.
Recognizing CP as a promising method, we propose the Singulated Glass core Embedding Process (SGEP) as an alternative. SGEP addresses the challenges of CP by embedding singulated glass cores into glass-epoxy panels and processing them in this state. SGEP offers advantages such as glass edge protection and device embedding within the same process. However, it also has limitations, including lower theoretical yield and less stringent design rules compared to CP.
This study examines the advantages and disadvantages of CP and SGEP, and highlights the technical challenges and improvements of SGEP. The results indicate that SGEP could be a feasible alternative, potentially expanding the options for panel-level manufacturing methods of glass core substrates.

 

Bio:
Tobias is the business unit leader of the Advanced Electrolytic Plating department at MKS Instruments located in Berlin.

Abstract:
This paper introduces a novel electrolytic flash copper plating system specifically designed to address the unique challenges associated with copper deposition in the modified semi-additive process (mSAP) for printed circuit board (PCB) manufacturing. In the mSAP process, one of the most critical aspects is the effective and reliable plating of buried microvias (BMVs) that are often used in high-density interconnect (HDI) and advanced PCB designs. The primary challenge in electrolytic flash copper plating lies in achieving the right balance of copper deposition: sufficient coverage inside the BMVs to ensure long-term reliability, while avoiding excessive copper plating on exposed glass fibers, copper foil overhang, and uneven BMV hole walls. Additionally, the plating process must accommodate slight variations in the drilling quality of the BMV holes, which can result in uneven hole walls. Addressing these challenges while minimizing surface copper deposition is essential for maintaining the structural integrity of the PCB and maximizing layout density.

FIGURE 1: Low copper thickness on Top for good L/S capability and high copper thickness on bottom for good reliability.

The proposed plating system incorporates a range of innovative control mechanisms to precisely manage copper deposition within the BMVs, ensuring uniform copper coverage throughout the via structure. These advanced controls enable the system to plate copper selectively inside the BMVs, effectively filling and smoothing the via walls, while avoiding too much copper on the PCB surface. This ability to maintain minimal surface plating is crucial for optimizing the high-density layout of the PCB, which is a key requirement in modern electronic devices. Furthermore, the system offers enhanced flexibility in accommodating drilling defects, allowing it to mask minor irregularities in the BMV hole walls with a smooth copper deposition that ensures reliable electrical performance.

In the latest mSAP PCB flash copper plating process, the initial copper foil thickness typically ranges from 1,5-3,5 µm, with an additional 0.35-0.5 µm of electroless copper and 1-3 µm for flash copper thickness. This thin copper layer is crucial for achieving the fine lines and spaces required in high-end HDI boards. Achieving high plating uniformity with reduced copper thickness is technically challenging and requires aligning three key factors: 1) fluid delivery system, 2) electrolyte chemistry, and 3) electrical field control. To meet this goal, the anode box design was optimized for anode segmentation and spray pattern distribution. Another challenge in advanced HDI production with finer lines and spaces is particle control to minimize defects and yield loss. To address this, the entire system has been optimized for particle avoidance and filtration. Additionally, the transportability of particularly thin panels has been improved through sophisticated guiding components.

The new design also emphasizes reducing the consumption of water, chemicals, and electrical energy. Fluid delivery systems were optimized for efficiency by reducing pressure losses. Furthermore, the chamber size was reduced, and components were arranged more smartly, resulting in a reduction in material usage and overall bath volume.

The paper discusses the key design considerations and technical solutions behind the new plating equipment, including the integration of real-time monitoring and adaptive plating control. The results demonstrate improved via reliability, enhanced process control, and superior overall performance compared to traditional electrolytic flash plating methods. This innovation presents a promising solution for the next generation of high-density PCB designs, offering the potential to overcome the limitations currently faced in the electrolytic flash copper plating process.

 

Bio:
I graduated with a Bachelor's degree in Applied Chemistry from National Yang Ming Chiao Tung University. I am currently pursuing a Master's degree at the Industrial Academia Innovation School of the same university. My research focuses on the mechanical properties of electro-deposited copper foils and how microstructure characteristics influence material performance. This presentation highlights a study in which manganese was introduced into the electroplating process, alongside conventional additives, to achieve grain refinement. The goal is to enhance the mechanical strength and thermal stability of copper foils. Our findings demonstrate that this modification significantly improves the reliability and service life of the foils, making it highly relevant for the development of electro deposited copper foil.

Abstract:
Electrolytic copper foils, owing to their excellent ductility, thermal conductivity, and electrical conductivity, has been widely applied in critical fields such as lithium-ion batteries (LIBs), printed circuit boards (PCBs), and chip packaging substrates (CPSs). As LIBs evolve towards higher energy density designs and electronic components become increasingly integrated within circuits, copper foils are required to meet more stringent performance criteria. These include enhanced mechanical strength, thermal stability, and dimensional stability to ensure reliability and long-term durability under high load and miniaturized conditions. Concurrently, with various countries progressively implementing long-term net-zero carbon emission policies, the electric vehicle market is experiencing explosive growth, which in turn raises the performance demands on their core energy systems—lithium-ion batteries (LIBs). Within LIBs, copper foil is extensively used as the current collector for the anode. During prolonged charge-discharge cycles, it must withstand significant internal stresses induced by volumetric changes of the electrode materials. Insufficient mechanical strength often leads to cracking and degradation, ultimately causing battery failures. Therefore, effectively enhancing the mechanical properties of the copper foil has become a crucial research focus to improve the overall stability and reliability of batteries.
In this study, we successfully fabricated both high electrical conductivity and high strength copper foils by using Mn-containing inhibitor. The electrolyte consisted of 0.5 M copper sulfate (CuSO4·5H2O), 80 g sulfuric acid (H2SO4), 30 ppm chloride ions (Cl⁻), 0.5 M manganese sulfate (MnSO₄·H₂O), and an additive ECD108C supplied by Chemleader Corporation. The ultimate tensile strength (UTS) of the copper foil reached up to 679 MPa, representing a 52.6% increase compared to pure copper foils, with an electric conductivity of 77% IACS (International Annealed Copper Standard). After annealing at 400°C for two hours, the UTS remained as high as 302 MPa—68.7% greater than that of the pure copper foil—with IACS improving to 93.8%. Focused ion beam (FIB) analysis revealed that the microstructures under the influence of ECD108C consisted of columnar nanocrystalline twinned copper. The addition of manganese in electrolyte effectively refined the grain size, thereby achieving strengthening effects while also providing outstanding thermal stability.

 

Bio:
Gustavo Ramos is the Senior Director of Business Development & Global Sales and Service at GreenSource Engineering, specializing in wet-chemical process tools, automation, factory engineering, and zero liquid discharge (ZLD) systems for PCB and IC substrate manufacturing. A chemical engineer from the University of São Paulo, Brazil, he has over 20 years of experience in PCB fabrication and assembly. Previously, he held various roles at MKS-Atotech Headquarters in Germany, most recently as Global Product Director for Final Finishing. His expertise focuses on PCB and IC substrate manufacturing processes and equipment as well as sustainable manufacturing solutions. Gustavo has authored and co-authored several publications in the electronics industry over the past years.

Abstract:
The increasing prominence of high aspect ratio (HAR) through holes in printed circuit board (PCB) and integrated circuit (IC) substrate manufacturing is driven by the ongoing evolution of high-performance electronics, including the growing influence of artificial intelligence (AI) and machine learning. These technologies demand unprecedented levels of data throughput, signal integrity, and power efficiency. As devices shrink and component density rises, HAR through holes enable the vertical interconnection of increasingly complex circuit architectures. This is especially critical in high-density interconnect (HDI) structures, where space savings and electrical performance are key.
In AI-driven applications, from cloud data centers to edge computing devices, substrates must support high I/O counts, low-latency communication, and reliable signal transmission across multilayer interconnect stacks. HAR vias are defined by their narrow diameter and deep penetration through thick panels this help meet these requirements by minimizing signal path lengths and reducing parasitic inductance and capacitance. These performance enhancements are essential for AI processors, accelerators, and advanced memory interfaces operating at high frequencies.
In addition to electrical benefits, HAR through holes also contribute to mechanical integrity and thermal reliability. As substrates continue to become thinner and more layered, maintaining structural stability during thermal cycling, such as reflow soldering or operational heating, becomes increasingly important. HAR structures provide mechanical anchoring and consistent connectivity between layers, improving overall reliability in advanced electronic packages.
The increasing complexity of heterogeneous integration which includes the stacking or side-by-side placement of logic, memory, and AI-specific chiplets has further fueled the demand for vertical interconnect solutions. Technologies such as 2.5D and 3D IC packaging rely heavily on precise, high aspect ratio via structures for routing signals between multiple functional components within compact footprints.
To explore fabrication capabilities and process optimization for HAR through holes, this paper presents an evaluation using a novel modular vertical electroplating system developed by GreenSource Engineering (GSE). This electroplating cell is designed to merge the advantages of horizontal and vertical conveyorized plating lines while offering unmatched process flexibility and modular control. The study focuses on 16:1 aspect ratio through holes; specifically, 0.2 mm diameter vias in 3.2 mm thick PCB panels.
Three different current density settings will be applied in a controlled plating sequence to assess process uniformity, via quality, and repeatability. The objective is to determine optimal operating conditions for reliable metallization of HAR vias in a high-throughput, production-relevant environment. By leveraging this advanced vertical plating platform, the study aims to highlight scalable approaches for manufacturing next-generation substrates that meet the performance demands of AI and advanced electronics.
The plating tools uniquely designed compatibility with GSE’s patented closed loop water recycling system will also be touched upon.

 

Bio:
Tim Lin began his career at DuPont in 2022 as an R&D chemist, where he successfully led the development of the LVF-VI-M electroplating product for substrate-like PCBs (SLP) utilizing the mSAP process. In 2024, LVF-VI-M was adopted by the largest SLP mSAP fabricator, marking the introduction of the first DuPont electroplating product in the SLP mSAP field. Tim holds a Ph.D. and a B.S. in Materials Science and Engineering, both from the Georgia Institute of Technology.

Abstract:
In the rapidly evolving landscape of mobile device technology, the demand for high-performance substrates has driven innovations in printed circuit board (PCB) fabrication processes. This paper presents a comprehensive study on the advancements in substrate-like PCB (SLP) and modified Semi-Additive Process (mSAP), focusing on a novel copper electroplating solution known as Microfill™ LVF-7. Specifically designed for mobile device applications, LVF-7 stands out due to its unique structural engineering and formulation that collectively enhance trench via filling and plating uniformity.
The first aspect of Microfill™ LVF-7 is its leveler type, which employs an advanced structural engineering approach to achieve robust bottom-to-top trench filling. This feature is critical in ensuring that the copper plating effectively fills vias completely, thus enhancing the overall integrity and reliability of the PCB. Additionally, the selection of an appropriate carrier type creates a synergetic effect with the leveler, leading to improved uniformity in plating thickness across varying trench dimensions. The intrinsic formulation of LVF-7 guarantees the absence of voids, which is a common challenge in traditional plating processes that compromises the reliability of electronic connections.
Moreover, the one-bath solution designed for LVF-7 significantly reduces process complexity while maintaining excellent trench filling capabilities. This is particularly advantageous in the mSAP process, where precision in plating thickness is paramount. Through a series of rigorous tests and evaluations, the proposed copper electroplating solution has demonstrated superior performance metrics, rendering it a viable option for next-generation substrate designs.
In conclusion, the integration of Microfill™ LVF-7 into the mSAP process not only elevates the quality of substrate-like PCBs but also paves the way for further technological advancements in mobile device fabrication. This paper elucidates the potential implications of these findings on future PCB manufacturing practices and the overall performance of mobile electronic devices.

 

Bio:
Christopher Ryder Christopher has been working in electronics for over 20 years, beginning his career at AT&S Austria, a world leading PCB and IC Substrate manufacturer. Early work in Quality Management led to initial work on industry papers on subjects of process and product reliability for developing technologies (such as embedded components) as well as a role as Instructor for HDI Manufacturing at IPC APEX. As Key Account Manager for a major American Semiconductor manufacturer while at AT&S, Christopher was also part of the company’s transformation from PCB to IC substrate manufacturer and played a role developing new products and markets. Christopher joined ESI in 2013 to lead development of the Geode Via Drilling platform as Director of Product Marketing. Since the MKS acquisition of ESI, he has worked closely with the broad spectrum of resources represented by the corporation to bring the innovative Geode Drilling platform to the market for ever-increasing area of applications. More recently Christopher changed roles to Sr Director of Business Development and relocated to MKS Japan, where his primary focus is growth in the IC substrate and adjacent semiconductor markets.

Abstract:
ABSTRACT
Laser trenching, sometimes referenced as linear laser via (LLV), is an emerging market trend for both the rigid and flexible circuit board application space. Increasingly, it has become a key solution for PCB designers and manufacturers as they look to push the difficult engineering boundaries required for products in the AI server, Low Earth Orbit (LEO), and smartphone application space. Given the steady drive for miniaturization, real estate on printed circuit boards and IC substrates in these spaces are at a premium. Maintaining the end device’s functional performance and total thermal load distribution, while adhering to strict material utilization metrics, reliability-driven quality specifications, and ever-increasing productivity requirements are the core elements of the challenge.

The root of the technology involves canal-like linear pattern ablation of one or more materials through the top of the panelized circuit to the next adjacent Cu layer, or trenches. Trench dimensionality can vary in width and depth, but design characteristics are commonly limited only by manufacturing tool limitations. Trenching is advantageous to PCB designers, as it often utilizes the otherwise unused areas of dielectric between adjacent copper layers and may enable a higher functional density without significant added costs to the manufacturer’s overall process.

While these trenches may have varying functionality in the final product, the technology demands precision in execution to fulfill strict quality specifications. Akin to standard microvias, clean sidewall taper and minimal bottom copper damage are the key quality metrics to consider when developing advanced trenching applications and investing in related processing technology. Specific to LLV drilling, it is crucial to ensure geometric uniformity throughout the trench length including junction points. Given the potential for a significant increase in total laser energy required to create LLVs, an effective thermal management strategy is also required to minimize material damage and heat-affected zone (HAZ). Moreover, as typically more material is ablated versus a standard microvia, productivity is essential to avoid laser-based manufacturing bottlenecks.

In this paper, we will explore ways in which an AOD-based (Acousto-Optical Device) CO2 laser via drilling system equipped with advanced beam-steering and laser power control technology may offer some unique technological approaches to meeting existing and emerging trench geometry specifications. This method allows for unique laser energy displacement and deflection to maintain the high rate of material ablation such applications require, while simultaneously deploying hardware and software-based thermal management strategies for HAZ reduction. Furthermore, through theory-based process simulation and replicated contrast-processes (non-AOD-based), we can gain insight into the building blocks this technology may offer to current high volume manufacturing (HVM) and future product roadmap development.

 

Bio:
Since August 2021: Senior R&D Manager, Desmear and Metallisation (PTH) at MKS Atotech September 2011-July 2021: R&D Manager, Desmear and Metallisation (PTH) at MKS Atotech September 2009-August 2011: R&D Scientist, Desmear and Metallisation (PTH) at MKS Atotech Postdoctoral researcher in computational chemistry at the Humboldt University of Berlin (Germany) PhD in inorganic chemistry at the Universities of Karlsruhe and Regensburg (Germany) MChem in chemistry and polymer science at the University of Lancaster (UK)

Abstract:
Recently, we reported on a smart, nickel-free electroless copper bath specifically designed for ultra-thin (≤ 150 nm) deposits for SAP applications. Although this bath, henceforth referred to as Bath A, is not capable of achieving thicker deposits during conventional plating times as a result of its self-limiting behavior, it does offer other significant benefits such as excellent electrical reliability, throwing power, deposit purity and crystallinity as well as good deposit adhesion to smooth substrates. Furthermore, deposits from Bath A demonstrate a low specific resistance, which is close to that of bulk copper. In view of these benefits and of the fact that the industry is still challenged in efficiently handling electroless copper deposits in the sub-200 nm regime on a mass-production scale, we decided to design a bath system that allows for easy and flexible switching between desired deposit target thicknesses using one and the same fundamental bath formulation. Consequently, by adding a certain moderating component composition to Bath A, the still nickel-free Bath B is obtained, in which the self-limiting feature of Bath A is lifted, and the deposition speed is accelerated. Bath B is therefore capable of blister-free deposition on established build-up films at thicknesses of up to 250 nm using typical plating time durations. To obtain blister-free deposits with thicknesses greater than 250 nm, one can use Bath C, which is prepared by simply adding nickel to Bath B. Since all three baths are based on the same fundamental composition defined by Bath A, enhanced throwing power, deposit purity and crystallinity as well as conductivity are ensured for all three baths. We expect Bath C to meet current and near-future industry requirements regarding electroless copper deposit properties including thickness. Thinner deposits with increasingly better conductivity can be readily accomplished by just “switching off” the nickel and the moderating component composition supply in succession, which will allow the easy transition to Bath B and finally to Bath A. Baths A-C thus constitute a modular electroless copper bath system, which is suitable for immediate deployment and is also future-ready. We expect this bath system will offer the industry unparalleled flexibility, agility and adaptability as it transitions to a state in which it is able to handle thinner and thinner electroless copper deposits on a mass-production scale.

 

Bio:
Carmichael Gugliotti has 12 years of experience in the PCB industry working at MacDermid Alpha Electronic Solutions based in Waterbury, CT. Carmichael currently is a Global Product Manager for Primary Metallization, prior to this he was the Applications Manager, Applications Specialist and R&D Chemist in the Metallization division. He holds a Bachelor of Science in Chemistry from the University of Connecticut and an MBA from Quinnipiac. He has worked on new metallization technologies for both primary and secondary metallization’s such as electroless copper, direct metallization, and acid copper plating.

Abstract:
The fabrication of a functional printed circuit board (PCB) is a complex, multi-layered process that plays a critical role in the modern electronics industry, an industry valued at $2.5 billion in 2024 (Prismark data). A key step in PCB manufacturing is metallization, specifically the process of making drilled holes conductive. Traditionally, this has been achieved using electroless copper deposition. However, direct metallization technologies based on carbon or graphite have existed as niche alternatives for over two decades, often limited by concerns regarding reliability and broader market acceptance.
In recent years, advancements in colloidal chemistry and process engineering have significantly improved the stability, performance, and sustainability of carbon- and graphite-based direct metallization systems. These innovations include more consistent colloidal dispersions, enhanced wet etch techniques, and superior coating uniformity, all contributing to a substantial reduction in void formation. These improvements enable direct metallization to meet the stringent quality and environmental standards demanded by today’s high-density interconnect (HDI) and advanced packaging applications.
This paper explores the evolution of colloid science in PCB manufacturing, detailing how next-generation carbon and graphite processes offer a more reliable and environmentally friendly alternative to traditional electroless copper. The result is a more viable metallization method better suited to meet the increasing performance demands of today's and tomorrow’s electronic applications.

Key words: Direct Metallization, Carbon, Graphite, Reliability, SEM, FIB, Ion mill, Coating, Colloid.