Sessions Index

Bio:

Abstract:

Inference tasks vary widely in complexity, data size, latency requirements, and parallelism, and each workload type interacts differently with CPU capabilities. Understanding this relationship allows for more effective hardware selection and optimization strategies tailored to specific use cases.
Key Learning Areas
-AI Model Architecture
-Types of Inference Workloads
-Quantization: Balancing Accuracy and Efficiency
-Data Throughput and Bandwidth
-Benchmarking Inference Performance
-Frameworks and Libraries Impact Performance

 

Bio:

Jay Wu is a platform application engineer at Intel's Data Center Group, specializing in thermal and mechanical development for datacenter products. He holds a Master's Degree in Mechanical Engineering from National Taiwan University.

Abstract:

As memory capacity and bandwidth demands continue to rise, system designs are pushing toward higher memory density—particularly in dual-socket server platforms. This session will explore the thermal design challenges and considerations involved in supporting a 2-socket, 32-DIMM configuration on the latest Intel® Xeon® platform within a standard 19-inch rack chassis. In such configurations, DIMM pitch is constrained to 0.25"–0.27", significantly increasing the complexity of memory cooling. We will present thermal evaluation results based on Intel-developed CPU and DDR5 Thermal Test Vehicles (TTVs), which simulate real-world heat profiles and airflow interactions.

 

Bio:

Thonas Su is a Tech Lead at Intel with over 15 years of experience in customer technical support within the server industry. He specializes in signal integrity simulation, enabling customers to perform risk analysis through simulation on Intel server products. His role also includes delivering technical training and providing ongoing support to customers. Thonas holds a Master’s degree from National Yang Ming Chiao Tung University (formerly NCTU) and is currently focused on PCI Express 6.0 and the upcoming 7.0 standards.

Abstract:

The dimensions of the Intel next platform has experienced an increase compared to the preceding ones, primarily due to the augmentation in pin count to increase the signal to ｄnoise ratio in both PCI Express 6.0 and DDR5. This alteration creates difficulties in arranging two processors, each of them has a 16 DDR5 channels, on a standard 19-inch rack. In response to this issue, Intel has embarked on a strategic initiative aimed at facilitating the accommodation of this challenge, which involves a proposal to reduce the distance between DDR5 connectors (a.k.a. DIMM pitch) as well as the processor’s keep out zone. To increase the DDR routing space underneath the DIMM connector’s pin-field area after shrinking the DIMM to DIMMM pitch, VIPPO (Via in Pad Plated Over) PCB (Printed Circuit Board) technology is used. These technologies significantly enhance signal quality when embracing the next generation MCRDIMM (Multiplexer Combined Ranks DIMM).

 

Bio:

Bryant Tsai is a customer system engineer at Intel Platform Engineering Group. Bryant has been working in the industry for 17 years, he started his career in Inventect from 2008 to 2014, and HPE from 2014-2021. In the same year, Bryant joined Intel as a Power Delivery engineer and responsible for power delivery and power integrity design of customer enabling.

Abstract:

The exponential growth in AI workload deployment has led scenarios where an 8-GPU server can consume up to 10kW, and the entire rack may consume more than 100kW, emphasizing the critical importance of power efficiency. This session presents a detailed power loss analysis across key components of power distribution within AI servers and at the rack scale and proposes future optimization directions.

 

Bio:

Ryan Chang is an experienced engineer in signal integrity and hardware design. He began his career at Wistron Corporation, where he worked from 2006 to 2018, gaining extensive experience in system development and engineering. From 2018 to 2021, he continued to build his expertise at Hewlett Packard Enterprise, contributing to high-performance computing and enterprise solutions. In 2021, Ryan joined Intel Corporation as a Signal Integrity Engineer, where he currently focuses on high-speed interface design and signal integrity analysis for next-generation computing platforms.

Abstract:

In recent years, with the continuous increase in speeds for high-speed interfaces such as PCIe in data centers, cables as enablers of high-speed interconnects have played an increasingly important role in long reach transmission channels. Raw cables are a key factor in cable assemblies and are the focus of this research. This study considers numerous factors related to the electrical characterizations of raw cables, including the testing process and methodology [1], the selection and comparison of fixture de-embedding algorithms, the extraction and fitting of simulation models, and the electrical specifications for test fixtures. Based on these considerations, a raw cable database was established, and the electrical characteristic trends and impacts of raw cables were statistically analyzed under multi-sample conditions. These standardized methods, processes, insights, and corresponding simulation and measurement examples provide detailed and comprehensive research on raw cable electrical characteristics, enabling raw cables to serve as important enablers for PCIe 5.0 and beyond.