Sessions Index

PDC1 PDC1 - Co-Packaged Optics with Silicon Photonics and Glass Packaging by Dr. John Lau

Oct. 22, 2026 10:00 AM - 12:00 PM

Room: 402bc, 4F, TaiNEX1
Session chair:  

Co-Packaged Optics with Silicon Photonics and Glass Packaging
發表編號:PDC1-1時間:10:00 - 12:00

Invited Speaker

Speaker: John H. Lau, Senior Special Project Assistant, Unimicrom


Bio:

Lecturer Bio

John H Lau, with more than 45 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 are the principal inventor), and 25 textbooks. John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.



Abstract:

Co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate chiplets such as the switch, photonic ICs (PIC) such as the laser and photodiode and the electronic ICs (EIC) such as the laser driver and transimpedance amplifier. The advantages of CPO are: (a) to reduce the length of the electrical interface between the PIC/EIC and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. Glass packaging is another important technology for high-performance computing (HPC) and data centers in artificial intelligence (AI) era. In the next few years, we will see more implementations of a higher level of heterogeneous integration of switch, EIC and PIC with silicon photonics and glass packaging, whether it is for performance, form factor, bandwidth, power consumption or cost. The contents of this lecture are shown below.

 Introduction

  • Data Centers, PIC and EIC
  • OBO (on-board optics), NPO (near-board optics), CPO (co-packaged optics)
  • 3D Integration of PIC and EIC with µbump and Hybrid Bonding
  • 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
  • 3D Heterogeneous Integration of ASIC Switch, EIC and PIC with Glass Substrate/Interposer
  • CPO with Silicon/Glass Photonics
  • Process Flow of Silicon Waveguides
  • Coupler between Laser and Silicon Waveguide
  • Coupler between Laser and Single Mode Fiber
  • Glass Packaging
  • Glass Substrate vs. Glass Interposer
  • TGV and RDLs
  • Panel-Level Packaging
  • Status of Panel Size
  • Effect of Glass Substrate on PCB Solder Joint Reliability
  • Summary and Recommendations


 


PDC2 PDC2 - High Reliability Advanced Semiconductor Soldering by Dr. Ning-Cheng Lee

Oct. 22, 2026 10:00 AM - 12:00 PM

Room: 403, 4F, TaiNEX1
Session chair:  

High Reliability Advanced Semiconductor Soldering
發表編號:PDC2-1時間:10:00 - 12:00

Invited Speaker

Speaker: Ning-Cheng Lee, Founder, ShinePure Hi-Tech


Bio:

Ning-Cheng Lee is founder of ShinePure Hi-Tech. Prior to that, he has been with Indium from 1986 to 2021. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder materials for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies” by Newnes, and co-author of 5 other books. He received 1991 award from SMT Magazine and 1993 and 2001 awards for best proceedings papers of SMI or SMTA International Conferences, 2003 Lead Free Co-Operation Award from Soldertec, 2008 and 2014 awards from IPC for Honorable Mention Paper – USA Award of APEX conference, and 2010 Best Paper Award of SMTA China South Conference. He was honored as 2002 Member of Distinction from SMTA, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.



Abstract:

Course Description:
Semiconductor soldering is much more delicate and is very critical for reliability of devices. This course covers the critical parameters governing the reliability for soldering in semiconductor packaging. The reliability discussed includes parameters affecting the intermetallic compounds (IMC), voiding, electromigration, low temperature soldering, high temperature soldering, and
electrochemical migration under a variety of material combinations. The failure modes are discussed in details, with preferred choices of materials and designs recommended.

Outline:
•IMC
–Effect of Cu Pad Grain Size on IMC
–Interaction of Cu and Ni
–Effect of Base Metal Co-P on IMC
•Voiding
–Effect of Solder Form on Voiding
–Effect of Joint Height, Temperature, Electrical, Mechanical on Shear Strength, IMC, Kirkendall Voiding
–Effect of Cu Structure on Kirkendall Voids
•Electrochemical Migration (ECM)
•EM
–Effect of EM vs TC on Crack Formation
–Effect of Back Stress on EM
–Effect of Grain Orientation on EM
–Effect of RDL Design on EM
–Electromigration of Low Temperature Sn-57Bi-1Ag
–Electromigration of LTS - Alloy Effect
–Electromigration of LTS - Surface Finish Effect
•LTS
–Bi-Rich Whisker Growth
–TCT Reliability of LTS
–Collapse of LTS
–Deposition, Hot Tear, Bi Stratification of LTS
–Hot Tear of Homogeneous LTS BiSn - Effect of Profile & Surface Finish
–Drop Test of LTS
•HTS - TLPB (Transient Liquid Phase Bonding)

Who Should Attend:
Anyone who care about achieving high reliability solder joints for semiconductor packaging and like to know how to achieve it should take this course.


 


DL 【Open Seminar III 】IEEE-EPS Distinguished Lecture by Dr. John Lau

Oct. 22, 2026 13:00 PM - 14:00 PM

Room: TPCA Show Main Stage (Area L, 4F, TaiNEX1)
Session chair: C. Robert Kao, National Taiwan University

Cu-Cu Hybrid Bonding for Chiplets Heterogeneous Integration
發表編號:DL-1時間:13:00 - 14:00

Invited Speaker

Speaker: John H. Lau, Senior Special Project Assistant, Unimicrom


Bio:

Lecturer Bio

John H Lau, with more than 45 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 are the principal inventor), and 25 textbooks. John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.



Abstract:

Cu-Cu hybrid bonding is one of the flip-chip Bumpless assembly technologies. The advantages of hybrid bonding are: (a) higher density, (b) finer pad pitch, (c) lower profile, and (d) better performance. In this lecture, some fundamentals and more than 21 high-volume manufacturing (HVM) or to be in HVM products and 12 new applications using hybrid bonding will be presented. In the next few years, we will see more implementations of Cu-Cu hybrid bonding, whether it is for performance, form factor, power consumption or cost. The content of this lecture is shown below.

Introduction

  • Origin of Hybrid Bonding
  • Cu-Cu Hybrid Bonding Fundamentals
  • 21 HVM or to be in HVM Products with Hybrid Bonding
  • 12 New Applications with Hybrid Bonding
  • Summary
  • Potential R&D Topics in Hybrid Bonding


 


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Co-hosting Event - TPCA Show 2026