Sessions Index

Bio:

Dr. Sung Jin Kim is the Chief Technology Officer of Absolics, a U.S.-based semiconductor packaging company spun off from SK Group. With over 30 years of experience in the semiconductor and microelectronic packaging industry, Dr. Kim spearheads the development of advanced packaging technologies and drives strategic business innovation at Absolics.
Prior to joining Absolics, Dr. Kim held executive leadership roles across a range of prominent organizations and international locations, including SKC, the Georgia Institute of Technology, Foxconn Advanced Technology, Daeduck Electronics, UTAC, and Amkor Technology. His extensive expertise encompasses package engineering, substrate manufacturing, and embedded component packaging technologies.
Dr. Kim is the holder of more than 200 U.S. patents and earned his Ph.D. in Electrical Engineering from the Technical University of Dresden in Germany.

Abstract:

The evolution of semiconductor packaging technologies demands materials that surpass the limitations of traditional organic and silicon-based substrates. Among emerging candidates, glass has gained momentum as a transformative platform for next-generation applications in artificial intelligence (AI), high-performance computing (HPC), and radio frequency (RF) communication.
Glass substrates offer a unique combination of properties—low dielectric loss, high insulation resistance, exceptional dimensional stability, and thermal compatibility with silicon—that enable superior electrical performance and mechanical reliability. Their ultra-smooth surfaces and ability to support fine-pitch interconnects and high-aspect-ratio Through-Glass Vias (TGVs) further enhance signal integrity and miniaturization potential.
Unlike organic materials, glass provides excellent hermeticity and environmental resistance, making it ideal for advanced MEMS and optical packaging. Moreover, large-panel glass processing offers a scalable and cost-efficient path for high-volume manufacturing, extending benefits beyond performance to production economics.
However, widespread adoption faces challenges such as mechanical fragility, TGV metallization reliability, limited thermal conductivity, and the need for ecosystem readiness. Addressing these hurdles through material innovation, process optimization, and industry collaboration is critical.
As the demand for higher integration, speed, and thermal efficiency grows, glass substrates are poised to become a foundational enabler of future packaging solutions—unlocking new possibilities for AI, HPC, and beyond.

 

Bio:

Herbert Oetzlinger , graduated HTL Braunau 1987 in high power electronics/ electrotechnics, Herbert worked in the Semiconductor industry for 30+ years, focused on wet processing.
Special focus on advanced packaging in electroplating and wet etching/cleaning of wafers and substrates. For many years he was VP of Sales with Semitool Inc, where he excelled with his in-depth knowledge of process and hardware. During this time, Herbert worked with many worldwide leading companies on Fan-out, E-WLB and other new developments in wafer level advanced packaging.
In 2012, he founded Semsysco GmbH and is also heading the company as CEO. LAM - Semsysco is a world leader in high speed electrochemical deposition with a pedigree and expertise in all-around wet processing for wafer and panel level.

Abstract:

In contemporary electronic packaging, the pursuit of miniaturization, enhanced performance, and reliability remains a fundamental driving force. This abstract introduces a novel approach in advanced packaging through the utilization of Through Glass Vias (TGVs) for Glass Core Integration, as a viable alternative to Conventional Silicon (Si) Interposer technology. The presentation encapsulates the background, motivations, technical aspects, and results of our evaluation work in this innovative packaging paradigm.
The background of this research is grounded in the growing demand for smaller form factors, increased functionality, and improved thermal management in electronic devices. Traditional Si interposer technology, while effective, presents limitations in terms of scalability, thermal conductivity, and electrical performance. Thus, the exploration of alternative materials and methodologies is imperative for the next generation of packaging solutions.
Motivated by the exceptional properties of glass, including its thermal stability, electrical insulation, and compatibility with existing manufacturing processes, this study delves into the feasibility of utilizing glass as both a carrier and core material in advanced packaging. Through Glass Vias (TGVs) emerge as a key enabler, facilitating vertical interconnects within the glass substrate.
Key considerations such as through-hole requirements, aspect ratios, seed layer deposition, and adhesion to glass are meticulously addressed to ensure the integrity and reliability of the packaging structure. Innovative process technologies are developed to fabricate TGVs with precise dimensions, high aspect ratios, and robust electrical properties.
The hardware requirements for implementing TGV-based packaging are evaluated, encompassing equipment for laser drilling, seed layer deposition, plating, and planarization processes. Cost considerations are also examined to ascertain the economic viability of this approach compared to conventional methodologies.
Results from our evaluation work demonstrate promising advancements in TGV-based packaging, including enhanced electrical performance, superior thermal dissipation, and significant miniaturization potential. Through detailed analysis and experimentation, this presentation illuminates the transformative capabilities of Through Glass Vias for Glass Core Integration, heralding a new era in advanced packaging technology

 

Bio:

Steven Tam is a seasoned professional with over 25 years of experience in the PCB and IC substrate industry, with extensive expertise in specialty chemical processes including surface treatment, metallization, and electrolytic plating. He currently serves as Product Director, IC Substrate line of business at ESI, where he leads regional strategy, product commercialization, and technology transfer across advanced ICS products platforms. Steven has held various key roles in technical marketing, product and technology management, and R&D coordination throughout his career at ESI, technology institute and various specialty chemical suppliers. He has successfully launched numerous innovative solutions for PCB and IC substrate market such as direct metallization, via fill, pulse plating, etc. A graduate in Chemical Engineering from HKUST with an MBA from the University of Hull, Steven combines strong technical insight with strategic leadership to drive growth and innovation in the electronic interconnect industry.

Abstract:

The industry transition from wafer-level packaging (WLP) to fan-out panel-level packaging (PLP) presents significant opportunities in scaling integration, cost reduction, and advanced package formats. However, this shift introduces critical plating challenges for line-and-space scaling, interconnect reliability, and uniform copper deposition across increasingly larger panels. MacDermid Alpha offers advanced solutions for overcoming challenges with innovations in plating chemistries. Synergetic relationships between materials, tools, and methodologies are essential to enable high-yield, high-performance PLP solutions that will support next-generation AI and high-performance computing applications.

 

Bio:

Ryo Tanaka, In 2014, I received my Ph.D. (Doctor of Engineering) from the University of Tokushima. The same year, I joined Okuno chemical Industries Co., Ltd. I am currently researching and developing additives for acid copper plating on semiconductor package substrates and interposer boards.

Abstract:

Advances in packaging technologies, such as chiplets, are leading to larger package substrates. As a result, production efficiency is declining. To compensate for this, panel-level packaging (PLP) technology is attracting attention.
In plating technology, dual damascene technology is essential for shortening process times. Furthermore, the development of dual damascene methods requires improved dimensional stability. To achieve this, films with minimal change in warpage due to heat are required.
We reviewed the design structure of nitrogen-based organic compounds and developed an additive that minimizes stress changes due to thermal history and can be filled with a thin film.

 

Bio:

Dr. Chin-Hock Toh is an Advanced Packaging Technologist at Lam Research, where he leads customer engagements, business strategy alignment, and the translation of technology roadmaps into advanced packaging solutions. He recently joined Lam after 10 years at Apple, where he drove packaging innovations for the iPhone, Apple Watch, and AirPods. With over 22 years of experience, including leadership roles at Applied Materials, Intel, and UTAC, he has pioneered advancements in WLP, fan-out, 2.5D IC, and 3D IC. Holder of 19 US patents, Dr. Toh is a long-time organizing committee member of SEMI SEA and IEEE EPTC, and earned his Ph.D. from UNSW, Australia.

Abstract:

Artificial Intelligence is driving a paradigm shift in semiconductor design, demanding ever-higher performance, bandwidth, and energy efficiency. Advanced Substrate, Interposer and Chiplet-based architectures have emerged as key enabler for meeting these demands, offering modularity, scalability, and accelerated development cycles. However, integrating these AI chips and memory into high-performance systems, especially for AI workloads introduces significant challenges in packaging and process integration.

This presentation explores the role of heterogeneous integration in AI-centric semiconductor design and the advanced equipment technologies required to support it. We will discuss key packaging schemes such as die-to-wafer hybrid bonding and interposer, which are essential for achieving the interconnect density and thermal performance needed in AI accelerators. Special attention will be given to Lam Research’s innovative equipment solutions that enable crack free interdie gapfill, finer interconnect and scalable manufacturing, critical for realizing the next generation of AI-enabled devices. Attendees will gain insights into how equipment innovation is accelerating heterogeneous integration and unlocking new possibilities in AI hardware design.

 

Bio:

Takashi Matsumoto ined DENSO in 2017 and was in charge of the Automotive Analog ASIC division. In 2025,transferred to the Technology Planning division and was in charge of SoC chiplet technology development.

Abstract:

Chiplets are expected to see widespread adoption in future automotive applications. However, they must be able to endure the tough operating conditions inside vehicles and meet strict mechanical and electrical requirements. In this presentation, we will propose design approaches to address these challenges.

 

Bio:
Ms. Bandharla Dharani is a Process Engineer at ASE, Taiwan, specializing in the panel backside grinding process. She focuses on ensuring panel thickness and Total Thickness Variation (TTV) remain within quality limits while preventing cracks and chips during the grinding process. Her expertise includes process control, troubleshooting, and improving throughput in grinding applications.

Abstract:
The demand of AI technology and High-Performance Computing (HPC) chips gradually increasing all around the world. For high performance and high integration, the requirement of thinner panel is necessary, here where the demand of the BS grinding process increased. The BS Grinding is the process is used to grind and polish the back side of the panel to reduce its thickness and fine surface chips which helps for high performance and integration. Achieving thin panel comes with more difficulties like to maintain Total Thickness Variation (TTV), no crack and Thickness of the panel. In this process Controlling TTV play a vital role due to its importance in Die stack, high yield and heat sink. A fine and uniform surface(thickness) is essential for detailed Integrated Circuit (IC) design and Inconsistent thickness can lead to defects in the circuit layout and also effect the next process like Bask side metallization or during Die stack process. This article introduces the Panel level BS Grinding process how precise for thinning the panel in order; to improve the mechanical and computing strength by overcoming the challenges like TTV, Thickness, Crack and Fine surface. The more even flat provides this leads to higher yields and improved performance in high-performance computing (HPC) and artificial intelligence (AI) applications.

Keywords— BS Grinding panel process, TTV, Fan-out, Fine Surface

 

Bio:
Professor Sheng-Jye Hwang received the Ph.D. degree in mechanical engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 1992. He has been a Faculty Member with National Cheng Kung University, Tainan, Taiwan, since 1992, where he is currently a professor. He has more than 96 SCI journal articles published in the areas of polymer processing, electronic packaging, 3D printing and computer-aided engineering. He is actively involved in industry-academic cooperating researches and has several technology transfers to the industry.

Abstract:
With the rapid development of artificial intelligence (AI), high-performance computing (HPC), and 5G communication technologies, traditional IC packaging techniques are increasingly inadequate to meet the demands for high transmission speeds and high-density integration. To address these challenges, the semiconductor industry has been actively developing advanced packaging technologies, including Fan-Out Packaging (FOP), 2.5D/3D integration, and Heterogeneous Integration. To achieve the high-density interconnect structures required by these technologies, the Redistribution Layer (RDL) process has become a critical and essential technology. However, polyimide (PI), the dielectric material commonly used in the RDL process, undergoes volume shrinkage during high-temperature curing, which may lead to uneven topography in the RDL structure. This deformation accumulates progressively through multi-layer stacking processes, adversely affecting the alignment accuracy during chip bonding, and potentially leading to signal short circuits or delays. To address these issues, this study establishes a simulation procedure for multi-layer RDL structures to predict the PI dish depth and topography of each layer. The simulation results are compared with experimental measurements to verify the feasibility and accuracy of the proposed approach.

This study focuses on multi-layer circuit structures in the RDL process by establishing two types of multi-layer models to investigate variations in PI dish and topography after the post-curing stage. The first model explores various line/space (L/S) dimensions, including 5/5 µm, 2/2 µm, 8/8 µm, and 10/10 µm. The second model is constructed based on actual measured topography data. Due to the lack of material properties for uncured PI, a single-layer circuit model was initially developed and simulated using assumed parameters. The results showed a noticeable discrepancy between the simulated and measured topography. Consequently, the material properties were further adjusted to enhance the simulation accuracy, and the refined parameters were applied to the multi-layer circuit models.

To simulate the multi-layer models, this study employed the Output Link, Element Birth and Death, and Morphing tools in Moldex3D to predict PI dish and topography variations in multi-layer RDL structures. The simulation results for models with different L/S dimensions revealed that both the L/S size and the PI thickness above the copper lines significantly influence PI dish and topography, with these effects becoming more pronounced as the number of RDL layers increases. Specifically, for the L/S dimensions of the 5/5 µm model, the deviation between simulated and measured PI dish was approximately 20–30%. Furthermore, the model constructed from actual topography data exhibited high consistency with the measurement results.

In conclusion, the simulation approach developed in this study effectively predicts the variations in PI dish and topography within multi-layer RDL structures, demonstrating its practical applicability. Nevertheless, the accuracy of PI dish prediction still requires further optimization and improvement.

 

Bio:
Nils Anspach is Director of Product Management at LPKF Laser & Electronics, overseeing the company’s Semiconductor and SMT product portfolio. He drives product strategy and market development for innovative solutions, including LPKF’s proprietary LIDE (Laser Induced Deep Etching) technology for glass substrates. With a focus on aligning technology and market needs, he plays a key role in shaping the future of advanced electronics manufacturing.

Abstract:
The proliferation of Artificial Intelligence, from large-scale cloud data centers to power-sensitive edge devices, has created an urgent demand for packaging solutions that deliver unprecedented performance with greater energy efficiency. As chiplet-based designs and heterogeneous integration become standard, the interconnect fabric is now a critical bottleneck, challenging the performance gains of advanced silicon. Traditional organic substrates are reaching their limits in terms of interconnect density, dimensional stability, and thermal performance, which directly impacts the power consumption and signal integrity of AI accelerators.

This paper presents Laser Induced Deep Etching (LIDE) as a pivotal enabling technology for the next generation of advanced packaging. LIDE overcomes the historical challenges of glass micromachining, allowing for the cost-effective, high-volume production of glass interposers with features previously unattainable. This unique two-step process facilitates the rapid, precise, and damage-free structuring of glass, creating micro-crack-free Through-Glass Vias (TGVs) with exceptional aspect ratios (>50:1) and vertical sidewalls.

We will demonstrate how LIDE directly addresses key trends in high-performance computing packaging. Specifically, we will detail its application in creating high-density interconnects and fabricating precise, deep cavities for the seamless embedding of silicon bridges. This architecture dramatically shortens the signal path between logic and memory chiplets, significantly reducing transmission losses and parasitic effects, which is crucial for lowering the power envelope of complex AI systems.

By leveraging the superior electrical properties and thermal stability of glass, LIDE-processed interposers provide a robust platform for 2.5D and 3D integration. The resulting packages exhibit enhanced signal integrity, improved thermal management, and superior reliability. In conclusion, LIDE is not merely an innovative process but a foundational technology that empowers package designers to build the compact, high-bandwidth, and energy-efficient hardware required to power a smarter, more sustainable world—from the cloud to the edge.

 

Bio:
John Chang is an Applications Development Manager in the Lithography Group at Onto Innovation. He holds a Master’s degree in Nanoelectronics and Photonics from National Chung Hsing University and has over 20 years of experience in semiconductor advanced packaging. Throughout his career, he has authored over 20 publications and holds numerous U.S. and Taiwan patents in metrology, lithography, advanced packaging, and AICS.

Abstract:
Advanced packaging technologies, such as ultra high density fan out packaging and 2.5D/3D integration, are essential for the continued advancement of chiplet-based AI applications. Achieving the stringent manufacturing requirements for AICS: specifically larger packaging areas, reduced line and space dimensions, finer ball pitches, and increased layer counts; necessitates the implementation of sophisticated lithography processes characterized by extremely large exposure fields coupled with fine resolution capabilities.

Despite these lithographic advancements, significant challenges persist, particularly concerning overlay accuracy. Overlay errors frequently result from alignment solution inaccuracies and can severely limit the achievable overlay yield, posing substantial impediments to scaling advanced packaging technologies. Addressing alignment solution errors effectively is critical for meeting the increasingly strict overlay budgets anticipated for next generation AI driven applications.

This study rigorously investigates process-induced alignment solution errors within large-panel lithography processes. By systematically analyzing overlay measurement data from a 510mm × 515mm panel substrate, we quantify and characterize alignment solution errors and their direct impact on overlay precision. Further, we propose an innovative early zone correction technique aimed at compensating alignment inaccuracies during the lithographic exposure phase. The early zone correction approach leverages algorithmic analysis to identify correctable zone-based overlay error components, subsequently applying these corrections proactively during lithographic exposure. The efficacy of this approach was validated experimentally using substrates exhibiting known alignment errors. The experimental outcomes indicate substantial improvements in overlay precision and yield, underscoring the robustness of early zone correction in addressing alignment inaccuracies. These findings demonstrate that the combination of extremely large exposure field lithography, fine resolution capability, and early zone correction significantly mitigates the overlay challenges inherent to advanced packaging manufacturing.

 

Bio:
Ting-Chi Chen is a Master’s student at National Yang Ming Chiao Tung University, specializing in Cu-Cu bonding technology for advanced semiconductor packaging. His research focuses on microstructural analysis and interface engineering to improve bonding quality and reliability. He is actively involved in exploring low-temperature bonding processes and their applications in 3D integration.

Abstract:
Direct copper-to-copper (Cu-Cu) bonding has emerged as a promising approach for advanced electronic packaging applications. Nanocrystalline copper (NC-Cu), with grain sizes below 100 nm, has recently garnered increasing attention because its high internal energy and enhanced grain boundary diffusion facilitate significant grain growth during high-temperature processes, which can promote grain growth across the bonding interface and improve interfacial bonding quality. Therefore, the extent of grain growth plays a critical role on NC-Cu in Cu-Cu bonding as increased grain growth provides more driving force for eliminating the bonding interface thereby enhancing the bonding strength. Our study revealed that applied pressure influenced grain growth behavior in NC-Cu in the bonding process. Accordingly, we investigated the correlation between applied pressure and grain size after annealing in NC-Cu, and examined how these factors impacted the overall bonding quality. In this study, a 2.5 µm-thick copper film was deposited on a titanium (Ti) adhesion layer using direct current (DC) electroplating in a copper sulfate solution with specific additives to produce NC-Cu. Chemical mechanical polishing (CMP) was then applied to planarize the surface. The microstructural changes were compared between the samples annealed under a compressive pressure of 10, 20 and 30 MPa at 200 °C for 1 hour, and then the film bonding was done under the same thermal conditions to evaluate its bonding quality.
The plan-view electron backscattered diffraction (EBSD) analysis was used to confirm microstructure of Cu film before and after annealing. The as-deposited NC-Cu exhibited an average grain size of 113 nm. The grain size was slightly greater than 100 nm because smaller grains in the dark regions could not be resolved due to resolution restriction. After annealing at 200 °C for 1 hour under 10 MPa, the grain size increased to 2077 nm, while a smaller increase to 746 nm was observed under 30 MPa, indicating suppressed grain growth under higher pressure. Electrical conductivity of Cu film was evaluated by measuring sheet resistance using a four-point probe, with film thickness confirmed via focused ion beam (FIB) analysis to assess the effect of pressure during annealing on film electrical properties. Cross-sectional analysis of bonded samples using FIB was conducted to evaluate the influence of bonding pressure on the microstructure and bonding quality of the interface. FIB analysis indicated that the seamless interfaces with few number of voids were obtained under all bonding conditions. These indicate that although significant grain growth serves as a primary driving force for Cu-Cu bonding in NC-Cu, the extent of grain growth suppressed under higher pressure in this study is not the only critical factor to influence bonding quality.

 

Bio:
My name is Ya-Hui, Hsu. I am a PhD student in National Central University. I major in chemical and materials engineering. My adviser is Prof. Cheng-Yi Liu. The present work studied the structure of the Ni(P) layer to predict the phase of the intermetallic compound at the interfacial reaction between SnAgCu(Ni) solder and electroless nickel electroless palladium immersion gold (ENEPIG) surface finish. Hopefully, the present work can contribute to advanced packaging technologies.

Abstract:
The present work studied the structure of the Ni(P) layer to predict the phase of the intermetallic compound at the interfacial reaction between SnAgCu(Ni) solder and electroless nickel electroless palladium immersion gold (ENEPIG) surface finish. Through the TEM analysis, we observed that nano–crystalline/amorphous and polycrystalline microstructures of the Ni(P) layer dominate the Ni dissolution rate into the molten SnAgCu(Ni) solder. Interestingly, the Ni(P) layer with nano–crystalline/amorphous microstructure dissolves less into the molten SnAgCu(Ni) solder than the Ni(P) layer with a higher crystallinity.

We believe that the P content expelled from the Ni(P) layers resides on the Ni(P) layer and retards the dissolution rate of the Ni(P) layer. In the opinion, we experimented the dual Ni(P) layer with low phosphorus content, and then covered it with high phosphorus content on the top layer. Compared with the single low–phosphorus Ni(P) layer, we found that the Ni(P) layer with high–phosphorus content does restrain the formation of intermetallic compounds during the reflow process. This phenomenon means that the interface mechanical property could be enhanced by the dual Ni(P) structure.

Moreover, the phase and morphology of the interfacial compound phase are greatly affected by the Ni content in the solder. A larger Ni content in the interfacial compound converts the prismatic-like (Cu,Ni)6Sn5 compound phase to the needle-like (Ni,Cu)3Sn4. At this point, the phases and morphology of the interfacial compound not only depend on the in situ Cu and Ni content in the molten solder, but also the reflow profile. In the experiment, the consumption of Ni(P) was calculated against different reflow times at 250℃, 265℃, and 280℃. The phases corresponding to the present determined Cu, Ni, and Sn composition in the reported Cu–Sn–Ni ternary phase diagram at 250℃ do not match the interfacial (Cu,Ni)6Sn5 compound formed in the 250℃ case. At 250℃, ripening occurred on the interfacial (Cu,Ni)6Sn5 compound grains and eventually caused them to spall from the interface. For 265℃ case, the faster ripening caused earlier formation of the valley and small spacing between the (Cu,Ni)6Sn5 compound grains after 10-s reflowing. After 20-s reflowing, the needle-shaped (Ni,Cu)3Sn4 compound phase begins to form at the valley sites of the interfacial (Cu,Ni)6Sn5 compound layer, which hinders the spalling of the (Cu,Ni)6Sn5 compound grains. For 280℃ case, we believe that the ripening of the (Cu,Ni)6Sn5 compound grains has quickly occurred within seconds. Hence, the needle-shaped (Ni,Cu)3Sn4 compound largely formed between (Cu,Ni)6Sn5 compound grains in 10-second reflowing. After a prolonged 40-s reflowing, the (Cu,Ni)6Sn5 compound grains have completely spalled off from the interface, and the needle-shaped (Ni,Cu)3Sn4 compound covered and dominated the entire reaction interface.

In this case, it is well known that the reflow profile of soldering process is not the only factor to influence the formation of intermetallic compounds at the interface. We found that the design structure of the Ni(P) layer can also control the interfacial reaction. With the ideal, we expect to develop a predictable model in SnAgCu(Ni) solder/Ni(P) layer system to enhance the interfacial mechanical property.

 

Bio:
Tan Wei Jern has been part of the semiconductor industry since 2012, working in both the Client and Server product segments. His focus has primarily been as Signal Integrity engineer in both platform design and customer product engineering. He has authored 8 papers and one patent.

Abstract:
This paper presents an electrical study on the sensitivity of channel design components in a DDR5 memory interface. The paper seeks to tackle issues caused by complex design elements in combination with ever-increasing memory signal speeds. The optimization and correct implementation of the proposed methods yield improved channel performance in terms of Eye Height/Vref(mV) and Eye Width/Delay(UI) margins. Of note, they maintain design flexibility, while enabling improved eye margins especially at higher memory data rates. The methods focus on channel design on existing signaling by identifying and mitigating harmful signal degradation caused primarily by signal reflection and signal-to-signal coupling, through correct optimization of signal layer assignment and via length, via-in pad implementation and device connector grounding. A poorly designed system might incur additional costs despite not having to. The ability of a highly correlated simulation methodology to predict a feasible routing solution through pre-silicon simulation on platform topologies with high confidence is therefore critical. It helps design engineers push the boundary on the hardware design solution and make necessary trade-offs in the design solution on PCB material. This enables server hardware design to adapt to scalable and fast design times for cost-effective solutions while keeping system electrical healthiness throughout product development by performing reliable SI trade-off analyses and avoiding potential additional costs of a poorly designed system

 

Bio:
Cheng-Yu Tsai received the M.S. degree in Electrical Engineering from National Kaohsiung First University of Science and Technology (NKFUST), Kaohsiung, Taiwan, in 2010. He joined ASE Kaohsiung in the same year and is currently a senior engineer in the Electrical Laboratory. His research interests include signal integrity (SI) and power integrity (PI) in substrate design.

Abstract:
The rapid development of artificial intelligence (AI) and high-performance computing (HPC) has driven the growing demand for bandwidth and data throughput, making chiplet architectures and advanced packaging technologies rapidly become mainstream in the semiconductor industry. As these demands grow, advanced package designs are required to integrate more RDL layers to accommodate increasingly complex signal and power distribution networks, which will inevitably lead to longer simulation times and increased challenges in design verification. To accelerate early-stage design evaluation, this work utilizes optiSLang to integrate the design and analysis workflow. By applying big data analysis and building predictive electrical models, the proposed method enables fast and accurate signal integrity (SI) checks for Die-to-Die interconnections. This helps layout engineers define design guidelines more efficiently in the early phase, thereby improving design accuracy and reducing iterative loops between simulation and design.

In this work, the Die-to-Die interconnect structure between the ASIC and HBM3 in a multi-layer RDL FOCoS package is used as an example. A parametric model is first constructed by defining input parameters such as line width, line spacing, dielectric thickness, and copper thickness. The eye width is defined as the output response. Next, an automated simulation workflow is implemented using optiSLang to perform a large number of design of experiments (DoEs) simulations. Finally, the collected data is used to train and validate a predictive model for signal integrity evaluation.

The signal integrity predictive model developed in this work has been successfully applied to FOCoS packaging and validated against actual design results, demonstrating an eye width prediction deviation of less than 10%. This predictive model not only provides practical design guidelines but also enables fast and accurate evaluation of Die-to-Die signal integrity in the early design phase, facilitating more reliable high-speed package designs.

 

Bio:
Heng Chuan Shu Product Development Engineer focuses on Power Design

Abstract:
Power Integrity (PI), & Power Delivery (PD), are two major power related electrical designs on printed circuit board (PCB), and package, for integrated circuit (IC). Both are inter-related yet each serves different spectrum of the design. Conventionally, PI and PD are designed separately as the design tools and area of focus are distinctive. PI focuses on PCB and package parasitic, ballmap and real estate planning, cap placement, and generally on higher frequency in megahertz ranges. On the other hand, PD focuses on voltage regulator (VR) design, stability, and efficiency on sub megahertz ranges. However, the actual operation mode is the full path loop which consists of both PI and PD domain.

The full path of PIPD design, consists of three major segments – VR, PCB, and IC. In order to validate the VR and PCB design, a tool to represent the IC component is needed. StarDust Load Emulator (SDLE) is an AMD’s proprietary tool that is used to validate VR and PCB design that are dedicated for AMD’s CPU. It has various controllable load patterns to mimic the behavior of CPU at board level thus it is a very useful tool to evaluate the power design of VR and PCB before the silicon arrives.

While the SDLE tool is valuable for power design validation in lab, a full path PIPD co-simulation (cosim) methodology is essential for design verification before the PCB is gerbered out. This helps to reduce the design cycle and cost by determining design flaws before they are found during the lab test. While a SDLE full circuit level model will provide the most accurate simulation output, it has two major problems. First, the circuit level model is not readily available in VR or PCB design environment. Second, the time required to run the full circuit level simulation is very long. As such, a behavioral model is proposed.

Behavioral SDLE model, PCB model, and VR model will then be converted into a common simulation environment, which is a popular commercial tool to run VR simulation – SIMPLIS. The results are then validated with actual lab measurement. The simulation and lab measurement data are highly correlated with less than 1% discrepancy.

 

Bio:
Tina Yang is currently a Platform Application Engineer in Data Center Group at Intel, responsible for high-speed interfaces design for server and workstation products. She received the M.S. in National Taiwan University of Science and Technology in 2012. She worked for Jabil from 2017 to 2019 and for Himax from 2019 to 2021. And she joined Intel Corporation as a signal integrity engineer for SI customer enablement and support and technology development from 2021.

Abstract:
As high-speed input/output (I/O) interfaces continue to evolve, The printed-circuit board (PCB) design has become increasingly challenging and complex—particularly in server and AI system applications. Designers must now address the issues for signal integrity of complex board design, to ensure reliable high-speed performance. From the currently prevalent PCIe 5.0 standard operating at 32 GT/s, to the forthcoming PCIe 6.0 and the future PCIe 7.0—targeting data rates of 64 GT/s and 128 GT/s respectively—each generation presents significant advancements in bandwidth and corresponding challenges in high-speed PCB design. From the perspective of PCB designers, performing accurate signal integrity (SI) simulations is essential at early stage for anticipating real-world behavior and mitigating potential risks prior to product fabrication.
A complete system design demands that designers perform thorough evaluations across multiple stages of development to ensure signal integrity and overall performance. In the early design phase, pre-layout simulations are conducted to assess the system architecture based on anticipated signal transmission quality. These simulations provide critical insights that guide the initial design direction. As the design progresses into the second phase, the results from early evaluations inform decisions regarding PCB topology and signal routing strategies. At this stage, design choices such as trace spacing, via placement, and routing angles can significantly impact signal behavior, making it essential to carefully consider their effects on signal integrity. Finally, in the post-layout phase, designers utilize the actual PCB layout to perform detailed signal integrity simulations. These post-layout analyses are crucial for validating the real-world performance of the design, identifying potential issues introduced during routing, and ensuring that the final product meets stringent electrical and reliability requirements. This structured, simulation-driven approach is fundamental to reducing design risks and achieving robust, high-speed system performance.
This paper examines the differences between various simulation algorithms applied to the same PCB layout design, aiming to understand the strengths and limitations of each methodology. In practical product development, designers must often strike a balance between simulation accuracy and computational efficiency, selecting appropriate algorithms for board-level signal integrity evaluation. Two-dimension (2D) and Pseudo Three-dimension which also called 2.5D simulation algorithms are commonly used due to their ability to significantly reduce analysis time. However, these methods often suffer from limited accuracy, particularly in modeling vertical structures such as vias. For instance, due to insufficient resolution along the z-axis, via modeling in 2D/2.5D simulations can lead to deviations from actual performance, potentially introducing design risks. In contrast, full Three-dimension (3D) electromagnetic (EM) simulation algorithms offer much higher accuracy by capturing the complete spatial behavior of signals, including complex via transitions and coupling effects. Nevertheless, this improved precision comes at the cost of significantly longer simulation times. For complex server motherboard structures, 3D simulations may require several days to even weeks to complete, which can impact product timelines and delay design cycles. The study explores the pros and cons of different methodologies for post-layout simulation, as depicted in Table 1.

 

Bio:
Tan Wei Jern has been part of the semiconductor industry since 2012, working in both the Client and Server product segments. His focus has primarily been as Signal Integrity engineer in both platform design and customer product engineering. He has authored 8 papers and one patent.

Abstract:
This paper presents an efficient DDR5 memory channel electrical modeling and board solution analysis methodology without compromising accuracy on scalable server platforms. The work proposes a hybrid modeling methodology that covers accurate DDR5 channel electrical across high volume manufacturing (HVM) and the risk evaluation coverage on scalable systems based on a golden reference system channel profiler using typical corner models to monitor HVM solution risks. The use of both 3D and 2.5D model extraction methodologies enables a balance coverage between improved extraction accuracy for complex vertical channel structures using the 3D methodology and processing time efficiency for straightforward transmission line segments using the 2.5D methodology. Segments such as System-on-Chip (SOC) Ball-Grid Array (BGA) via region and the memory device connector that feature increased vertical crosstalk benefit from the accuracy of 3D model extraction, while segments such as the memory channel’s main route transmission line that do not exhibit this benefit from time efficiency of a 2.5D extraction method. This shows an overall accuracy improvement compared to a purely 2.5D extraction method and time-saving benefit compared to a purely 3D extraction method. The ability of a highly accurate simulation methodology to predict a feasible routing solution through pre-silicon simulation on platform topologies with high confidence is critical. This enables server hardware design to adapt to scalable and fast design times for cost-effective solutions while keeping system electrical healthiness throughout product development by performing reliable SI trade-off analyses and avoiding potential additional costs of a poorly designed system.

 

Bio:
- Sr. Manager of Signal Integrity Engineering at Wiwynn Corporation - Principle Field Application and Module Design Engineer at Astera Labs - Sr. Engineer of Signal/Power Integrity Engineering at Hewlett Packard Enterprise - A. Director of Signal/Power Integrity Engineering at Wistron Corporation

Abstract:
As the high-speed signal transmission lines routing density continues to increase in AI server systems, signal integrity has become a critical factor in PCB design. Additionally, with the PCIe Gen6 and Ultra Ethernet interfaces coming to be standard links in AI servers design, even minor variations in routing can significantly impact link performance. In these high-density designs, the high-speed routings are exactly combinations of many different routing patterns by segments. However, the normal PCB impedance verification and transmission loss evaluation in the manufacturing process are from one or two routing patterns on PCB test coupons only. That would trigger a thought-provoking question here: can the impedance and loss validation results from the one or two routing patterns’ coupons represent the characteristics on actual in-board routings? To answer this question, we’ve designed experiments with many different patterns’ coupons as DUTs to quantify the characteristics of different routing patterns in this paper. Eventually, we’ve characterized the behaviors of different routing patterns with some findings as routing patterns can impact impedance uniformity and signal loss, especially above 10 GHz.

 

Bio:
Kin Fei is a Principal Engineer at Tenasic Technology with 17 years of experience in electrical engineering. He received his B.Eng. and M.Sc. degrees in Electronic System Design Engineering from Universiti Sains Malaysia. His work focuses on signal and power integrity for advanced SoC platforms, including applications in autonomous vehicles, IoT, servers, and clients. He has extensive experience in X86, RISC-V, and FPGA-based package and board design, and currently leads cross-functional development in SIPI analysis and platform integration for next-generation systems.

Abstract:
Early-stage silicon power grid and Power Delivery Network (PDN) decoupling planning relies on Chip Power Model (CPM) and instances current profile, where the scenario selection of these profiles directly impacts MIM (Metal-Insulator-Metal) capacitor allocation and silicon floor planning. The challenge lies in selecting appropriate switching scenario, vectorless or vectored. Misestimating current demand leads to either overdesigned PDNs or silicon with insufficient IR drop margin.
Conventional methods rely on vectorless current profiles with toggle rate assumptions. This approach often lacks correlation with actual workload switching activity. In contrast, vectored simulations with gate netlist driven by real activity offer higher accuracy but are time consuming. The industry currently lacks a systematic method to select representative simulation windows for vectored analysis or to calibrate vectorless toggle rates in early assessments. As a result, the early PDN and MIM planning decisions made using these methods might risk misestimation.
To address this, we introduce a segmentation and concatenation technique that constructs an equivalent composite full cycle vectored current profile. It achieves up to 7x reduction in simulation time while maintaining comparable accuracy to full window vectored simulations. Based on this golden reference, we evaluate multiple current profiling used in IR drop analysis tool.
Our study includes vectorless profile using different toggle rates, and vectored profiles based on real switching activities. Each activity is evaluated for its impact on peak-to-peak voltage noise, minimum voltage, and overall Dynamic Voltage Drop (DVD) margin. While results converge, selective scenarios can still yield optimistic or pessimistic outcomes depending on context.
In our case study of a DDR5 controller, we observed that early vectorless estimates led to under allocation of MIM capacitance by up to 50%. We also found that DVD was highly sensitive to toggle rate assumptions, underscoring the limitations of uncalibrated vectorless methods. Conversely, vectored simulations yield more realistic DVD, bump level peak to peak voltage noise, and minimum voltage (Vmin), resulting in optimal MIM allocation. Our contributions include:
Segmented concatenation framework that stitches short duration vectored windows into a concatenated full workload current profile, achieving up to 7x runtime reduction.
Scenario coverage methodology that scores candidate vectored cycles based on toggling activity, power profiles, and electrical impact, enabling a judicious subset selection for high fidelity DVD correlation. Ditch the need for full vectored cycles simulation.
Toggle rate sensitivity study, evaluating vectorless parameters to help automate gross model generation for early signoff confidence.
This work offers practical guidance for Power Integrity (PI) and advanced package engineers to perform accurate MIM and decoupling cap planning, enabling SoC projects to converge faster while maintaining robust voltage stability.
This paper is organized into the following sections:
Section I: Full window vectored current profile segmentation and concatenation technique and the wall time reduction.
Section II: Vectorless and vectored current profiling methodology.
Section III: Simulation results with vectorless and vectored current profiles with different switching activities scenarios. It is shown that vectorless DVD was highly sensitive to toggle-rate.
Section IV: The current profiling impacts on on-chip decoupling cap and package decoupling cap strategy.

 

Bio:
Chew has 14+ years working experiences in platform electrical design and solution specializing in signal and power integrity pre-silicon analysis methodology enabling, package and system level HSIO design enablement and solution. She has proven technical and analytical skills with >50 international technical contribution to-date and she is also actively serve as member of technical program committee for various international journals and IEEE technical conferences. Chew graduated from The University of Nottingham, holding a PhD and MSc degree in Engineering where her research areas cover visual information processing such signal transformation and compression, object recognition and detection and motion estimation.

Abstract:
This paper provides an overview of GPU product Universal Baseboard (UBB) integration into data center system design including the introduction of common DC GPU system topology, channel electrical performance as well as methodology for signal performance evaluation and I/O performance tuning.

GPU loss, PCIe link drop and link instability often occur during system integration due to non-optimize PCIe preset selection which required a customize analysis of retimer tuning on each customer platform. Due to the uniqueness of the electrical performance such as system loss budget and impedance discontinuity of the channel in each customer platform, a comprehensive signal integrity (SI) simulation methodology which includes the consideration of worst corner cases and high-volume manufacturing (HVM) variation is introduced. Besides, a post-silicon retimer tuning process is also discussed to improve PCIe link performance during UBB system integration at customer data center.

A comprehensive data collection and analysis performed on actual customer platform shown that there is high correlation of SI simulation and post validation findings. The work presented here helps not only to enable end consumers for a smoother and quick time-to-market adoption of AI GPU products, it could also help to improve the working model efficiency and enlighten customer supports services.

 

Bio:

Jimmy Hsu serves as a Principal Engineer within Intel's Data Center and AI Group, where he leads the development of interconnect solutions for high-speed interfaces. He earned both his Bachelor of Science and Master of Science degrees in Control Engineering from National Chiao Tung University, in 1998 and 2000, respectively.
His research primarily focuses on high-speed design, with particular emphasis on power integrity, signal integrity, and electromagnetic interference (EMI). Throughout his career, he has contributed to 80 international publications and has been granted 16 US patents, underscoring his significant contributions to the field of high-speed interface technology.

Abstract:

• Evolution of High-Speed Technologies in Data Center and AI Applications

• Evolution of High-Speed Technologies in Data Center and AI Applications

• Challenges in High-Speed Design

• Advancements in PCB Electrical Characterization

• Enabling the PCB Ecosystem

• Summary

 

Bio:
1. Major in Chemical Engineering & Materials Science at Yuan Ze University. 2. Research expertise: Electrochemistry, Thermal Module Applications, Finite Element Analysis.

Abstract:
The continuous miniaturization of electronic devices along with the rapid increase in current density has led to a significant rise in power consumption and an urgent demand for thermal modules in recent years. Copper (Cu) is widely used as a conductive and heat-dissipating material in many PCBs and IC devices due to its low resistivity, high thermal conductivity, superior electromigration resistance, and excellent mechanical properties. Recently, a “bar via” structure, i.e., an array of slender Cu strips arranged in a trench-type layout, has gained a great deal of attention in the PCB’s thermal module design because it greatly raises the efficiency of thermal dissipation, while preserving process and routing flexibility. The surface flatness of electroplated Cu above the bar via structure is one of the critical factors, dominating the thermal dissipation efficiency of thermal module and affecting the reliability of PCB build-up process. The morphological modification of Cu electrodeposition in the bar via structure through electroplating parameters (e.g., organic additives or flow field) was therefore conducted in the present study. Our established electrochemical simulation model can well characterize the Cu electrodeposition behavior in the bar via structure and electroplating parameters (organic additives or flow field) may play critical roles in the Cu electrodeposition morphology in bar via structures. The electrochemical simulation techniques established in this study would facilitate the development of thermal module for high-power RF components.

 

Bio:
more than five years of signal integrity

Abstract:
As data rates for PCIe signals continue to rise and modulation shifts from Non-Return-to-Zero (NRZ) to Pulse Amplitude Modulation with 4 Levels(PAM4), DDR signaling is also advancing from 8800 MT/s to 12800 MT/s. These transitions significantly elevate the importance of channel quality. To meet these demands, more stringent electrical requirements have been proposed, and close collaboration with PCB vendors is underway to validate and manufacturing process variations. This collaboration ensures consistent and reliable production processes, enabling designers to more easily meet the new electrical specifications and achieve their design goals with high performance and reliability.
A comprehensive analysis will be conducted across multiple PCB vendors using Intel ® Automatic In-Board Characterization. This analysis will validate impedance and loss management across critical interconnect areas such as vias, pin fields, and main routing paths. Additionally, it will detect the impedance variation in transition areas and P/N skew for differential signals, highlighting the impedance mismatches are becoming increasingly critical for next generation data center platform. To support platform design optimization, an electrical design library will be developed serving as a reference for achieving consistent signal integrity and performance across diverse manufacturing processes.

By empowering the PCB ecosystem with not only advanced manufacturing capabilities and quality standards but also state-of-the-art measurement technologies, superior design outcomes have been achieved for platform designers. The next generation PCB design requirements emphasize high-speed application needs, particularly via and pin field impedance control, in addition to conventional open-field routing. This initiative supports ecosystem enablement by showcasing PCB vendor capabilities, promoting consistent design quality, and streamlining manufacturing management across diverse suppliers. Ultimately, this approach helps platform designers meet evolving electrical requirements and deliver high-performance, reliable products.

 

Bio:
More than 12 years of working experience in signal integrity

Abstract:
As high-speed signals evolve, PCI Express (PCIe) transitions from Gen5 to Gen6, and DDR5 RDIMM (Registered Dual In-line Memory Module) and MRDIMM (Multiplexed Rank Dual In-Line Memory Module) also increase to 8800 MT/s and 12800 MT/s, respectively. As a result, channel integrity has become more critical than ever, prompting an increase in the number of package pins in Intel’s upcoming platform to improve the SNR (Signal-to-Noise Ratio). This change has made the dual processor (a.k.a. 2 sockets, 2S) 16 channels (CH) configuration incompatible with standard 19-inch rack dimensions, presenting a significant integration challenge. Intel has launched a strategic initiative to support 16 channels within a 19-inch rack on its upcoming Server platform. This effort is intended to meet customer demands for high-density DDR deployment in a standard 2S 19-inch rack configuration.
This approach to addressing the challenge involves a carefully crafted proposal to reduce the DIMM pitch and processor keep-out zone. It is supported by a comprehensive risk assessment that covers the entire channel simulation, ensuring all potential issues are thoroughly evaluated and mitigated. The assessment includes crosstalk comparison between the standard and narrow DIMM pitches configurations, thereby ensuring the overall signal integrity (SI) quality of the channel design.
Two notable design enhancements are the integration of VIPPO (Via-In-Pad Plated Over) technology in the DDR connector area and the reduction of the DIMM-to-DIMM distance (also known as narrow DIMM pitch), as illustrated in Figure 1. VIPPO provides additional routing space, which is essential for maintaining signal integrity as DDR speeds increase, particularly for MRDIMM. By allowing vias to be placed directly inside the pad, VIPPO shortens path and improves signal integrity. This design not only enhances electrical performance but also optimizes the physical layout, enabling more channels to fit within a 19-inch chassis. The adoption of VIPPO underscores Intel’s commitment to pioneering advanced solutions that address complex technical challenges while meeting the evolving needs of its customers.
SI comparisons between non-VIPPO and VIPPO are shown, demonstrating that VIPPO not only preserves routing space but also significantly improves signal margin in the DDR channel, ensuring robust performance in high-speed applications. The comparison highlights the advantages of VIPPO, including reduced crosstalk, improved signal integrity, and elegant PCB routing, making it a key strategy for delivering high-performance computing solutions in next-generation 19-inch rack designs.

 

Bio:
Zi-An Huang received the B.S. degree from the Department of Mechanical and Computer-Aided Engineering, National Formosa University, Huwei, Taiwan, in 2018, and the M.S. degree in advanced intelligent manufacture for electric vehicle from National Tsing Hua University, Hsinchu, Taiwan, in 2024,He is currently a Engineer with Structural Design Section, Acbel Polytech Inc., His research interests include power supply structure design , electronic package designs and semiconductor-related manufacturing processes.

Abstract:
The reliability of the electronic is the important issue for the product. In this study, based on to the recent huge demand in artificial intelligence and big data applications, more technical researches are focused on how to improve and enhance the efficacy of data center design. Furthermore, the designs of IT equipment and power supplies system are influenced the specification of data center in the international tier systems, depended on maximum permitted downtime and backup power supply. In the study, mechanical estimation is utilized to assist the engineering development in MLCC of PCB floorplan design. On the other hand, enhancing the products life and reliability of power supply are critical role. In the hardware of power supply, one persistent headache is the mismatch in thermal coefficient expansion between different materials, especially during high temperature application environment especially aging conditions. Moreover, the plastic deformation associated with creep physical behavior progressively is accumulated, eventually causing mechanical issues like solder crack or delamination during the operation of power supply. From previous references, these mechanical failure behaviors influence electrical failures or even breakdowns. In addition, our experimental results show high reproducibility with physical behaviors from previous literatures.
Research indicates that the placement of components on the board has a measurable impact on their reliability and structural strength. these factors influence the lifetime of power supplies. However, tweaking the layout for reliability isn’t not without cost, these changes may sometimes reduce performance. Consequently, there is few perfect solutions for satisfying physical demand. It makes sense to consider multiple layout strategies MLCC of PCB floorplan design that balance lifetime with other design priorities. Product lifetime is an important parameter in reliability research, completion of validation experiments will enable effective control of product lifespan. In this study, we are aims to develop a practical framework that integrates Coffin Manson lifetime modeling via nonlinear finite element analysis (FEA) and multilayer perceptron of neural networks, all aiming to achieve a more accurate depiction of reliability and to identify novel approaches for prolonging product life. Furthermore, solder materials, integrated with Anand model, are considered in this study. After validated FEA via experiments, the difference is lower than 10%. The database from mechanical simulation accounts for 250 sets. 80% database is used for the training in Neural Networks. In addition, others are utilized to process the testing. This strategy enables to provide multiple robust designs for selection of design engineering between mechanical and electrical domains in MLCC of PCB floorplan design.

 

Bio:
Ph.D student from NCKU (Program on Semiconductor Packaging and Testing, Academy of Innovative Semiconductor and Sustainable Manufacturing)

Abstract:
Solid liquid interdiffusion (SLID) which was also well-known as
transient liquid phase (TLP) bonding derives from 1970s for
connecting high melting point Ni based alloy at relative low bonding
temperatures to reduce the cost of heating process. TLP process
includes interlayer melting, dissolution, isothermal solidification, and
homogenization. After the joint bonded, the interlayer will transform
into high melting point intermetallic compounds (IMCs). Advanced
packaging requires high stability in extreme operating conditions of
high temperatures, however due to the shrinkage of bonding size and
solder joints were fully transformed into IMCs, the traditional
soldering process poor reliability and brittle in thermal cycling tests.
Tin (Sn), Indium (In) and Gallium (Ga) are commonly selected as
interlayer materials because of their low melting point. Notably, Ga
exhibits a wide solubility in copper (Cu), which makes it highly
promising to form solid solution joint for Cu-to-Cu interconnection.
In our previous work, Cu/Ni/Ga/Ni/Cu sandwich couple will
transform into Cu/fcc-(Ni,Cu,Ga)/Cu structure and show great
thermal reliability in high temperature storage. In order to achieve Ga
solid solution TLP bonding, precise transfer for liquid Ga is required,
but it is very difficult because of its high surface tension. CuGa2,
Cu9Ga4, Ni3Ga7 and Ni2Ga3 these IMCs are commonly found in Cu
Ga or Cu-Ni-Ga bonding joints if Ga transfer isn’t properly controlled.
In this study we proposed an electroplating Ga method for Cu
substrate and Ni UBM to achieve precise transfer for Ga. The
interfacial reaction during electroplating will be disclosed, and the
effect of Ni UBM thickness on composition of electroplated thin films
will be studied. Surface and cross-sectional morphology will be
demonstrated by the field-emission SEM. Phase transformation at
different temperatures during heating process will be determined by
XRD. To achieve Ga TLP bonding for Cu-to-Cu interconnection, we
have to make sure that the interlayer can transform into Ga liquid
phase and react with substrates. Ga particles synthesis and Ga thin
film deposition technology of Ga and Ga-based alloy have been
widely studied for 3D IC packaging or TIM material owing to its low
melting point and non-toxic properties. Although electroplating Ga
technology still facing low current efficiency issue and coalescence
of the plated thin film which attributes to the poor wettability on
substrate, electrodeposition makes Ga TLP bonding a better chance to
fabricate high reliability joints. The solid solution TLP bonding was
considered to be one of the most potential methods in next generation
packaging technology for the power modules.

 

Bio:
Master’s student in Professor Jenn-Ming Song’s Laboratory, Department of Materials Science and Engineering, National Chung Hsing University, focusing on direct bonding research for advanced semiconductor packaging.

Abstract:
Solder mask, also called solder resist, refers to a thermally stable and thin polymeric coating applied to the non-soldered areas of printed circuit boards (PCBs) and component substrates, such as those used in flip-chip packaging and wire bonding. Additionally, solder mask plays a crucial role in advanced packaging due to their good insulation properties, which protect copper circuits from oxidation and prevent outside moisture from penetrating and corroding the circuitry. Once cured, solder mask doesn’t release emitted gases or moisture, contributing to its low volumetric shrinkage—an essential feature for high-precision applications. Considering the bond between polyimide (PI) and solder mask is crucial for the reliability of flexible printed circuits and other electronic assemblies, direct bonding between solder mask and PI was developed in this studied. Surface treatments were performed using three different irradiation wavelengths: vacuum ultraviolet (VUV, 172 nm), UV-C (254 nm)/VUV (185 nm), and UV-C (220 nm), followed by thermal compression bonding (TCB). Experimental results show that a greater amount of surface functional groups did not consistently lead to enhanced interfacial bonding strength between these two polymer materials. For further understanding, nanoindentation techniques were conducted to characterize the mechanical properties of the treated surfaces and the discussion was made with the chemical characteristics.

 

Bio:

Tetsuy Onishi is the managing director of process engineering consulting company Grand Joint Technology Ltd (G.J.Tech).
  Older chemical background semiconductor packaging Japanese engineer* involved in materials, design, process, quality, reliability & analysis for bare die products, COB device, IC packaging, COF, LCD module, memory Modules, EL products, LED packaging & lighting products, IR device, gas sensor device, RF device, Cu TGV metallization & special chemicals. He has been researching the Glass PKG for more than 10 years. T. Onishi received the “Die Products Industry Achievement award“ at the 8th Annual International KGD Packaging and Test Workshop 2001, in Napa, California. He is a senior member at the Japan Institute of Electronics Packaging (JIEP) and a director of Nagano Jisso Forum Japan.
*45-years in electronics assembly packaging field life with failure analysis +packaging process improvement

Abstract:

For applications such as high-speed transmission, 5G communication, HPC for Ai, and new optical devices, a substrate that does not absorb moisture, has small CTE, and has less warpage, the Glass core is required. This presentation will show Glass PKG technologies trends and key technologies.

Keywords— “Glass core ”, “Glass PKG application”, “TGV”

 

Bio:

  Frank Su brings a wealth of experience working on multiple industry products in the semiconductor capital equipment business, both in FEoL and BEoL. As the head of worldwide business development, panel product line, at Lam Research, Frank helps set the strategic path for continued market growth to increase penetration with various customer segments for this expanding technical area. Prior to his current role.
  Frank worked for over 25 years in different positions within sales, marketing, and general management. As part of the initial team at SEMSYSCO Asia where he served as managing director, Frank helped build the infrastructure to support customers across the region. He graduated from National Taiwan University with his M.S. degree in Industrial Engineering. Frank also received a M.S. degree in Business Administration of Technology Management from National Tsing Hua University.

Abstract:

 

Bio:

Education

Ruprecht-Karls University of Heidelberg Diploma in Physics, 1994

PhD thesis at the Institute for Solid State Physics, Heidelberg

Focus on research in solid-state physics 

Professional Experience

Since 2008

Vice President, Schmid Group, Freudenstadt, Germany

Executive responsibility for the business units Photovoltaics (PV), Glass Technology, and Business Development at the group's headquarters. Leading global strategic initiatives, innovation programs, and market expansion.

 2004 – 2008

Chief Executive Officer (CEO), Schmid Technology GmbH, Freudenstadt, Germany

Managing director of a Schmid Group subsidiary. Oversaw the development, production, and global sales of inkjet applications and related high-tech equipment.

1998 – 2004

Chief Executive Officer (CEO), Heidelberg Instruments, Heidelberg, Germany

Full responsibility for corporate strategy, product development, and international sales of laser lithography systems for the semiconductor and microtechnology sectors.

1994 – 1998

Sales Director, Heidelberg Instruments, Heidelberg, Germany

Built and led the international sales team for laser lithography solutions targeting the semiconductor industry. Key interface for R&D collaborations and strategic customers.

Abstract:

       The relentless demand for higher performance, miniaturization, and increased integration density in advanced packaging is driving fundamental shifts in IC substrate and AI server board manufacturing. The SCHMID Group’s glass substrate solutions introduces a high-volume manufacturing (HVM) platform specifically designed for next-generation glass-core substrates, enabling ultra-fine features, robust vertical interconnects, and excellent thermal and mechanical properties.
       This presentation highlights the comprehensive process integration of InfinityBoard, with a particular focus on Bottom-Up Plating—a critical technology for achieving reliable, high-aspect-ratio via metallization in glass substrates. The process begins with Through-Glass Via (TGV) formation, utilizing TRUMPF’s ultrashort-pulse laser drilling, followed by hydrofluoric acid etching to produce clean, debris-free sidewalls and exceptional aspect ratios. Metallization of the TGVs is achieved exclusively through bottom-up electroplating, delivering superior via fill quality for holes with diameters as small as 10 µm and aspect ratios exceeding 1:50. This capability is essential for product reliability and opens the door to more advanced design rules for the redistribution layer (RDL).

 

Bio:

  E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She was the editor of Recent Developments in Tape Automated Bonding published by IEEE Press. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She is a member of MEPTEC, SMTA, and SEMI. She serves on the JEDEC Task Force JESD-94 Working Group Application Specific Qualification Using Knowledge Based Test Methodology. She has served on the IEEE CPMT Board of Governors for two terms. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She received her M.A. from University of Texas, in 1981.

Abstract:

 

Bio:

Jyh-Long Jeng is the Manager of the Materials and Chemistry Laboratory at Industrial Technology Institute, Taiwan. His research area focus on the development and laminate materials for PCB appications and build-up film materials semiconductor packaging applications.

Abstract:

1. Laminate materials for PCB appications.


2. Build-up film materials for semiconductor packaging applications.


3. Evaluation platform for dielectric materials

 

Bio:

Masahiro Saito, Ph.D., is the Manager of the 2nd Surface Science Laboratories at Toray Research Center, Inc., Japan. He has over 20 years of experience in surface and interface analysis, specializing in ion beam techniques such as RBS and ERDA. Dr. Saito earned his Bachelor’s degree in Electrical and Electronic Engineering from Kyoto University, focusing on high-Tc superconductivity, and later received his Ph.D. in Material and Life Science from Kyoto Institute of Technology, where he studied ion beam interactions with polymeric materials. He also served as a guest researcher at Georg-August-Universität Göttingen, Germany, developing external ion beam systems.

Abstract:

Hybrid bonding is essential for 3D semiconductor integration, but optimizing reliability requires detailed interface analysis. This study introduces a multi-technique approach using CD-XPS, STEM, SIMS, XPS, RBS, and XAFS to investigate SiO₂/Si bonded interfaces. Special sample preparation enabled precise access to buried regions. SIMS and XPS revealed hydrogen-rich zones and contamination, while STEM and XAFS clarified structural and chemical bonding states. These findings provide insights into bonding mechanisms and offer practical guidance for process optimization in wafer-to-wafer and die-to-wafer bonding, contributing to the advancement of low-temperature, high-density semiconductor packaging.

 

Bio:

1985-1988

Candela Laser Inc

1988-2002

BOSCH Corp 

2002-2022

Waseda University

Professor, Research Organization for Nano & Life Innovation

Kyushu University, Visiting Professor

Hamamatsu University School of Medicine, Visiting Professor

National Chung Hsing University, Visiting Professor

2022-Current

National Cheng Kung University Professor

Academy of Innovative Semiconductor and Sustainable Manufacturing

Abstract:

We will explain recent technological trends in COWOS-L and CPO in heterogeneous integration.
Next, we will introduce research results on thermal management using microchannels, RDL, hybrid bonding using resin, fluxless bonding, TGV, thermal management for AR glasses, and artificial intervertebral discs using semiconductor devices.

 

Bio:

• Career

       -Working in overseas business for 26 years at ZUKEN as:

       -Application Engineer

       -Project manager working with global major customers

       -Product marketing

       -Application Engineer Manager at Zuken Taiwan

        -Asia-Pacific Regional Engineering Manager at Zuken Singapore

        -Manager of Asia Business Unit at Zuken Inc. (Japan)

• Specialized field

       –Schematic & PCB design

       –Package design

       –Electro-mechanical collaborative design

Abstract:

In the near future, electrical and mechanical design will be integrated, and a design environment that smoothly links with analysis will become important. Based on this idea, I will introduce ZUKEN’s 3D design environment "Design Force".

 

Bio:

・ 2012 to 2018 he was a professor at the Institute of Microelectronics Assembling and Packaging at the Fukuoka University, Japan.

    And since 2019 he had been the guest professor at the Fukuoka University.
・He received Ph. D degree from Shizuoka University in 2011.
・He is chair of the Device Embedding Technology Committee, established by JIEP(The Japan Institute of Electronics Packaging).
・He has been working on device embedded substrates and high density wiring of Printed Wiring Board throughout his working career in      companies and university.

・ He is chairman of "The research committee of standardization for device embedded technology" in Japan.
・He is co-convener of IEC TC91 WG6.

Abstract:

I will present the International Standard activities for 3D devise embedded module at the IEC (International Electrotechnical Commission).

 

Bio:

2021 Completed a master's degree in engineering at Hokkaido University
2021/4~ Work at Mitsubishi Materials Corporation.
Research Electroplating and Pacaging Process

Abstract:

・Fine pitch interconnects
・Direct Bonding
・Porous Structures

 

Bio:

In March 2022, I graduated from Tohoku University with a Master's degree in Environmental Science.
In April 2022, I joined Kao Corporation and have been responsible for my current duties since then.

Abstract:

We present our work on copper particles that exhibit high dispersibility and can be sintered at low temperatures. These particles can be stably dispersed at high concentrations in a wide range of solvents. When used as copper bonding materials for power semiconductor
applications, the resulting bonded structures demonstrate excellent thermal stability.
We are currently evaluating their performance as bonding materials for power semiconductors.
We also plan to investigate their potential as conductive paste used in semiconductor packaging and multilayer ceramic capacitors (MLCCs).

 

Bio:

Kejun Wu is a Research and Development Engineer at Ushio Inc., specializing in the applied development of 172 nm wavelength ultraviolet light generated by excimer lamp. He graduated from the Graduate School of Tokushima University with a degree in Optical Systems. During his first three years at Ushio, he focused on the surface modification of fluororesins and the formation of copper plating using excimer lamps. Currently, in his fourth year, he is engaged in developing activation processes for hybrid bonding through excimer lamp treatment. Originally from Taiwan, Wu is now based in Japan and has presented his research at various conferences, including The Surface Finishing Society of Japan, the Microelectronics Symposium 2024, and The Japan Institute of Electronics Packaging.

Abstract:

Three-dimensional integration technology has emerged as a promising solution to overcome scaling challenges in advanced semiconductor device technologies. This approach involves vertically stacking multiple chips, which shortens interconnect lengths and enable higher integration density. A crucial method within 3D integration is hybrid bonding (HB), which facilitates fine-pitch wiring connections necessary for advanced semiconductor devices.
In the HB process, it is essential to remove organic contaminants from the Cu/SiO2 surface and modify the SiO2 surface with functional groups such as OH species, while preventing surface roughening and avoiding oxidation of the Cu electrodes. Plasma treatment effectively achieves such surface cleaning and introduction of OH, but it induces surface roughening due to high-energy particles.
As an alternative process, vacuum ultraviolet (VUV) cleaning has been proposed. Conventional VUV cleaning process under water vapor environments dissociates O2 and H2O to generate reactive species that eliminate organic contaminants but oxidize metal electrodes. To solve this problem, VUV treatment under an N2/H2 atmosphere with added H2O was reported, which effectively removed organic contaminants and reduced copper oxide. Here, we investigated the effects of VUV light irradiation under an N2/H2 + H2O atmosphere on the surface activation and bonding strength of Cu/SiO2 samples that simulate actual semiconductor materials for hybrid bonding.
VUV light with a central wavelength of 172 nm, emitted from a xenon excimer lamp (STN3-317, Ushio Inc.), was irradiated onto SiO2 substrates with copper patterns (Cu/SiO2) under a gas atmosphere that was prepared by bubbling a mixed gas of N2 and 4 % H2 through liquid water (N2/H2+H2O atmosphere). The surface chemical states were analyzed by X-ray photoelectron spectroscopy (ULVAC-PHI, PHI Quantera II). The surface roughness was measured by atomic force microscopy (SPM-9700HT, Shimadzu).
The XPS spectra after VUV treatment for 45 s under the N2/H2 + H2O atmosphere significantly decreased surface organic contaminants and effectively reduced copper oxide. The XPS analysis confirmed the presence of OH species on the surface after treatment. The surface roughness showed no appreciable change on the Cu electrode and a reduced arithmetic mean roughness (Ra) of SiO2 surface after the treatment. Finally, bonding strength was evaluated using die shear testing. The VUV treated Cu/SiO2 samples were pre-bonded at room temperature, achieving a maximum shear bonding strength of 10.68 MPa. After heating to promote the expansion and diffusion bonding of the Cu electrodes, the bonding strength increased to a maximum of 17.71 MPa.
These results demonstrate that VUV treatment under N2/H2 + H2O atmosphere is a promising activation method for hybrid bonding, offering effective contaminant removal, surface activation, and enhanced bonding strength without surface damage within a short processing time.

 

Bio:

Takashi Tasaki graduated from the Department of Materials Science and Engineering at the Graduate School of Engineering at Kyushu University in 2003, after which he joined Arakawa Chemical Industries, Ltd. Since then, he has specialised in developing and marketing electronic insulation materials.

Abstract:

Digital transformation in various industries has led to an increased demand for processing large amounts of data, resulting in a demand for higher performance in electronic devices. To meet these requirements, the semiconductor industry is adopting heterogeneous chiplet integration technology. In this context, redistribution layers (RDLs) are critical components for heterogeneous integration. In the future, higher performance will require insulating materials with low dielectric properties for high-speed transmission and good flexibility for warpage control of the heterogeneously integrated package. In response to these technical trends, we have developed novel polyimide compositions for RDLs. Firstly, our polyimide compositions have a low Dk/Df of 2.4/0.002 at millimetre frequency. Secondly, they have good flexibility, i.e. a low modulus of approximately 1 GPa and a high elongation of around 100%. These properties are effective for warpage control by stress relaxation. Finally, the layers of our polyimide compositions are suitable for a semi-additive process, enabling us to produce fine lines and spaces of 2/2 µm on our polyimide layers. We can also create vias through solvent development following i-line exposure. Therefore, we conclude that our polyimide compositions are suitable for use as dielectric materials in RDLs for future HPC applications.

 

Bio:

Mr. Reito Kobayashi is the part of JCU Corporation which produces equipment and chemicals for plating industry both decorative and
electronics. Since he joined electronics technology development, he has been developing the additives for copper plating process.

Abstract:

As limitations of the Si interposer due to insertion loss at high frequencies are expected in the future, new structures, such as glass interposers and fan-out interposers, are being considered as substitutes. These new structures require brand new chemicals to achieve large-scale filling, void-free deposition, and high uniformity in TGV, TSV, and RDL, respectively. To meet future demand, we have developed surface treatment chemicals for each application.

 

Bio:

Masafumi Wakai received his Bachelor's degree from the Department of Electrical and Electronic Engineering from University of Shinshu, Japan, in 2006. Since then, he has been working at the research institute of ULVAC, Inc., where he has contributed to the development of CVD for electrical devices and flat panel display. After that he developed sputtering targets for oxide semiconductors and alloys. Since 2023, he has been responsible for the development of sputtering technology for GaN devices and panel level packaging at ULVAC. Outside of work, he enjoys soft tennis and scuba diving.

Abstract:

The next era of AI-driven information and communications technology (ICT) systems will be powered by an infrastructure that integrates Cloud Computing, Fog and Edge Computing, and Massive IoT. New semiconductor devices are necessary for artificial intelligence (AI) that require real-time or low-latency performance (less than 1ms), as well as low power consumption. High-density packaging technologies, including 3D chiplet integration with wafer-level packaging (WLP) and panel-level packaging (PLP), are essential to meet the manufacturing requirements of these high-performance semiconductor devices. ULVAC has been continuously developing manufacturing solutions to achieve heterogeneous integration through substrate packaging, 2.5D interposers, and 3D-IC technologies, including through-glass vias (TGV), through-silicon vias (TSV) and hybrid bonding. In this presentation, ULVAC will outline our efforts in heterogeneous chiplet integration, which involve PVD (Physical Vapor Deposition) sputtering techniques and plasma etching/ashing to achieve high-density interconnections.

 

Bio:

Dr. De-Shin Liu obtained his Ph.D. in Engineering Mechanics from the University of Missouri-Rolla in 1989. He then served as a senior structural safety project engineer at General Motors in Warren, Michigan, from 1989 to 1991. Currently, he is a full professor in the Department of Mechanical Engineering at National Chung Cheng University in Chia-Yi, Taiwan. His research interests include computational mechanics, micro-impact testing methods, 3D printing techniques for soft materials, and structural failure mode analysis, with applications in electronic packaging design and medical device development.

Abstract:

Three-dimensional (3D) chip stacking has become a key technology in Taiwan’s advanced semiconductor industry, driven by the trend toward System-on-Chip (SoC) integration. Through-Silicon Via (TSV) technology is central to this development, enabling vertical interconnections between chips with reduced signal path lengths, lower resistance, and improved signal integrity. However, TSV structures present reliability challenges. The formation of vias reduces the mechanical strength of the silicon die, and thermal-mechanical mismatches between the silicon substrate and metal filler can induce high interfacial stresses, especially under thermal cycling, potentially leading to structural failure. To address these concerns, the presentation will introduce the Heterogeneous Infinite Element Method (HIEM), a novel simulation approach for analyzing heterogeneous 3D structures. HIEM significantly reduces the degrees of freedom in global models without simplifying the Through-Silicon Via (TSV) interlayer configuration, thereby maintaining high accuracy and computational efficiency. Numerical examples will be presented to demonstrate that HIEM is a powerful tool for optimizing TSV layouts and enhancing the reliability of 3D integrated circuits.
Keywords (Through-Silicon Via, Numerical Method, 3D Packaging Reliability)

 

Bio:
Professor Yu-Lin Shen received his Ph.D. in engineering from Brown University in 1994, and M.S. and B.S. in materials science and engineering from National Tsing Hua University in Taiwan. He was a post-doctoral research associate at Massachusetts Institute of Technology before joining University of New Mexico (UNM) in 1996. He is currently Professor and Chair of the Department of Mechanical Engineering at UNM. Professor Shen has been active in research and teaching in the areas of mechanical behavior of materials and solid mechanics. He is particularly well versed in applying modeling techniques to address micro-mechanical problems related to thin films, microelectronic devices and packages, and composite materials. He has published about 200 research papers, mostly in the form of journal articles. His book titled “Constrained Deformation of Materials” was published by Springer in 2010. In 2005 Professor Shen was elected Fellow of the American Society of Mechanical Engineers (ASME). He has been rated among the World's Top 2% Most Influential Scientists List (Career Impact and Single-year Impact ) by Elsevier/Stanford University.

Abstract:
The pursuit of miniaturization, enhanced performance, and energy efficiency in semiconductor devices has driven innovations in advanced packaging technologies. Among these, glass substrates and through glass vias (TGVs) have emerged as promising solutions, due to their advantages in enhancing device functionality and performance. Traditional organic substrates and silicon-based interposers face limitations in electrical performance and scalability. Glass substrates offer several benefits. Their inherently low dielectric loss and high electrical resistivity make them suitable for high-frequency and radio-frequency (RF) applications. Glass is non-conductive, thus eliminating crosstalk in dense circuits. Additionally, glass provides exceptional dimensional stability and surface flatness, enabling precise lithography for fine-pitch interconnects. The transparency of glass also opens doors to photonic integration. Glass’s thermal stability further ensures reliability during high-temperature processes such as reflow soldering, while its tunable coefficient of thermal expansion (CTE) can be better matched to adjacent materials to minimize thermal stress. TGVs complement these advantages by enabling vertical interconnections in 3D packaging, enhancing device density and shortening electrical pathways. Compared to through-silicon vias (TSVs), TGVs can achieve lower parasitic capacitance, therefore improving signal integrity.

Despite their potential benefits, glass substrates and TGVs still face significant hurdles. The brittleness of glass raises concerns about mechanical reliability during handling, dicing, and thermal cycling. Fabricating high-aspect-ratio TGVs is technically challenging; processes like laser drilling or chemical etching must balance precision with cost-effectiveness. Metallization of TGVs also poses adhesion issues, requiring novel deposition techniques. Furthermore, CTE mismatch with external materials still exist, and internal CTE mismatch and modulus mismatch between glass and copper TGVs also lead to localized stresses, risking delamination or cracking. As in all substrates in electronic packaging, shape change caused by warpage has always been a concern for structural integrity.

In this presentation we highlight our recent numerical study on the warpage resistance of glass substrate containing TGVs. The resistance is characterized by the bending rigidity of the plate-like structure. A series of finite element analyses are performed, taking into account the square array of TGVs inside the glass matrix. The simulations utilize a representative composite structure, with appropriate boundary conditions imposed to ensure symmetry and periodicity. Various TGV concentrations under both the unidirectional bending and biaxial bending are considered. Bending rigidity is determined by the prescribed curvature and the reaction moment obtained from the computational analysis. It is found that a higher TGV fraction results in a greater bending rigidity and thus warpage resistance, which is due to the higher stiffness of copper compared to glass. A higher TGV fraction, however, leads to higher magnitudes of local normal stresses. When plastic yielding of copper is taken into consideration in the modeling, the TGV/glass interface region near the free surfaces is prone to localized plastic deformation. Permanent warpage occurs after the bending moment is completely removed. Implications of the numerical findings on potential damage of the TGV structure are discussed.

 

Bio:
The speaker is a graduate student at National Tsing Hua University, focusing on reliability simulation of packaging structures. Her work involves finite element analysis and the use of equivalent modeling methods to closely reflect real-world conditions.

Abstract:
Three-dimensional finite element analysis (FEA) is commonly used to assess solder joint fatigue, a frequent failure mechanism in wafer-level packaging (WLP) under thermal cycling conditions. However, such simulations typically involve hundreds of thousands of elements, resulting in high computational costs. To resolve this issue, multi-point constraints (MPC) and equivalent beam elements are introduced to reduce the element and make the simulation efficiently.
A 3D FEA model incorporating MPC and equivalent beams is developed in this study. MPC is applied to the four solder balls located farthest from the neutral point, while non-critical solder joints are substituted with equivalent beam elements. The cross-sectional area of the equivalent beam was modified to align its mechanical response with that of the solder ball under realistic conditions. All materials are assumed to behave linearly, except for the solder joint. The solder joint follows the Chaboche kinematic hardening model, and the geometry of the solder joint is derived using Surface Evolver. The model is subjected to thermal cycling based on JESD22-A104D Condition G. Finally, the Coffin-Manson equation is used to estimate fatigue life.

 

Bio:
Dr. Cadmus Chang-Ann Yuan is currently a Professor at the Department of Mechanical and Computer Aid Engineering, Feng Chia University in Taichung City, Taiwan, investigating the AI algorithms and finite element methods for industrial applications.

Abstract:
AI-driven applications have rapidly become a major force in semiconductor development, leading to increased demand for advanced packaging solutions. Among these, heterogeneous integration (HI) has emerged as a critical enabler for high-performance computing due to its capacity to support complex interconnect architectures and high-density component integration. One notable example is the Chip-on-Wafer-on-Substrate (CoWoS) technology, which leverages silicon interposers to integrate logic and memory dies for enhanced bandwidth and system performance.

However, accurately modeling HI structures using finite element (FE) methods remains computationally expensive due to their geometric and material complexity. To mitigate this, prior studies have proposed using equivalent beam models as simplified representations of solder joints. Banijamali et al. demonstrated their application in 3D IC packages, while Cheng et al. and Yuan & Chiang extended the methodology to BGA and WLCSP packages, respectively. These beam models, especially when constructed with multiple sections, can replicate key thermo-mechanical behaviors such as temperature-dependent stiffness and creep response.

This study builds a full vertical stack, comprising the molding compound, chip, substrate, solder joint (or its equivalent beam), and PCB. Moreover, this study builds the equivalent beam models under various boundary conditions, including conventional node merging, multi-point constraints (MPC), and full column integration. The solder joint is modeled using the Anand viscoplastic law, while the equivalent beam adopts the Chaboche nonlinear hardening model. Through external nodal loading (shear, axial, and moment), the mechanical responses—expressed as reaction forces and moments—are compared between the solid solder model and the simplified beam models.

The results aim to find the most suitable configuration for efficiently and accurately predicting solder joint behavior in complex HI packages. Furthermore, the methodology is extendable to other interconnect types such as flip-chip and micro-bumps, offering a scalable framework for reliability prediction in next-generation semiconductor systems.

 

Bio:
Prof. Yu-Jui Liang is an Assistant Professor in the Department of Aeronautics and Astronautics at National Cheng Kung University (NCKU), Taiwan. His research expertise includes finite element modeling (FEM), composite materials, computer-aided engineering (CAE), and electronic packaging analysis. Dr. Liang is actively engaged in interdisciplinary research combining structural mechanics, numerical simulation, and advanced material design, with applications ranging from aerospace systems to semiconductor packaging. He also leads collaborative projects with both academic institutions and industry partners.

Abstract:
As semiconductor IC packaging advances, increasing design complexity necessitates higher resolution in numerical model meshes, leading to an exponential growth in computational demands. Traditional Computer-Aided Engineering (CAE) methods, which rely on constructing model with detailed geometries, are becoming impractical due to hardware limitations. To address this challenge, a novel equivalent finite element model is proposed for warpage prediction in printed circuit boards (PCBs) by using the pixel-based approach of equivalent material properties. This approach streamlines simulation by optimizing mesh handling and computational efficiency, significantly reducing processing time while maintaining predictive accuracy.

 

Bio:
The speaker is currently a graduate student at National Tsing Hua University, specializing in reliability simulation of advanced packaging structures. Her research focuses on finite element modeling and thermomechanical analysis to assess structural integrity and failure risk under actual operating conditions.

Abstract:
As Moore’s Law steadily approaches its physical and economic limits, the semiconductor industry is undergoing a paradigm shift—moving beyond traditional transistor scaling toward advanced packaging technologies that can enhance performance at the system level. In this context, the “More-than-Moore” roadmap has gained significant traction, particularly with the rise of heterogeneous integration and chiplet-based architectures. These approaches allow multiple functional dies to be modularized and integrated within a single package, offering improved design flexibility, enhanced manufacturing yield, and greater integration density. However, this structural evolution also introduces a range of reliability challenges. Complex packaging configurations give rise to issues such as thermomechanical stress accumulation, coefficient of thermal expansion (CTE) mismatches, mechanical warpage, and solder joint fatigue failures—factors that can severely impact device fatigue life and operational stability.
To address these reliability concerns, this study proposes a simulation framework that combines the Global-Local Finite Element Method (FEM) with Equivalent Beam Theory. The framework incorporates Multi-Point Constraints (MPC) and refined meshing techniques to enhance both simulation accuracy and computational efficiency. SAC305 is employed as the solder material, and thermal cycling conditions are defined from –40 °C to 125 °C based on JEDEC standards. Thermal-mechanical coupled simulations are conducted using ANSYS APDL, enabling the precise identification of high-stress concentration areas and probable failure location within the package.
Moreover, this study investigates how the proposed methodology can be effectively applied to the rapidly evolving field of chiplet-based package designs. These packaging technologies are widely considered critical to the next-generation semiconductor ecosystem, particularly in high-performance computing. The ultimate objective of this research is to establish a validated and practical finite element model capable of predicting the reliability and failure mechanisms of advanced chiplet packages. By comparing simulation results with empirical data from real package structures, the model's accuracy and practical utility are confirmed. This FEM framework not only provides powerful design assistance, significantly shortens development cycles and reduces trial and error costs, but also improves overall design robustness and market competitiveness. Ultimately, it empowers engineers to conduct early-stage risk assessments and design optimizations, meeting the growing demand for reliability and performance in advanced semiconductor packaging.
Keywords – Chiplet Packaging, Global-local Finite Element Method, Failure Analysis, Thermo-mechanical Stress.

 

Bio:
Jed Chien is a simulation specialist with over 10 years of experience in CFD and FEM, focusing on semiconductor packaging, underfill processes, and digital twin technologies to improve design efficiency, reduce development cycles, and enhance product reliability through advanced modeling and process optimization. Previously, Jed in charge of mold flow simulations Lab for fluid fields at ASE-CL, applying software verification to semiconductor engineering across various flow and fluid mechanics scenarios.

Abstract:
This paper focuses on predicting and optimizing flux residue and process parameters in packaging products using flux, without being limited by scale model constraints, such as simulating a 1/10,000 size difference (bump size/pitch <5µm versus space height >50,000µm). The study aims to assess how various factors—such as nozzle size, angle, distance, and flow parameters—affect the flux residue during flux cleaning, particularly for products with large, small, or fine-pitch bumps. The use of common parameters across all products may not achieve effective cleaning results, and residual flux ions in high humidity conditions could cause ionic migration, leading to metal deposition between electrodes and short circuits. Additionally, halogen compounds in residues may cause electroplating corrosion, affecting wire bonding strength and curing quality.

This study employs CFD software to analyze flow fields, construct working space models in a part of strip, and evaluate multiple conditions, including the nozzle of cone angle, spacing, movement speed, distance, and flow rate. Observations are made on the flux through bumps and the effects of nozzle diffusion on each package. The transient moving simulation with varying angles examines how water flow rates impact the bumps under the die.

The technical breakthrough lies in modeling the multiphase interaction of water and air flows, accurately reflecting the actual conditions within water tubes and mixing nozzles. Conventional approaches often result in initial divergence due to design limitations such as diffusion angles and splashing effects. In contrast, the patented nozzle utilizes a multi-arc conical geometry instead of a traditional cone. This design, when interacting with the bump mesh layer—characterized by a 1/10,000 scale difference it can induce abnormal momentum inversion due to angular diffusion and Finite Volume Method (FVM) cell zone discretization. Through optimization of geometric configurations and refinement of governing equations, the simulation achieved significantly improved convergence behavior.

This methodology enables a comparison of flux residue in FC device cleaning processes, taking into account varying process parameters and equipment capabilities across different package types particularly in fine-pitch bump configurations. The simulation results indicate that packages oriented perpendicularly to the cleaning nozzle experience the lowest water mass flow rates 0~90kg/(m^2 s). In contrast, packages with a pitch distance of 8 mm or greater from the nozzle demonstrated enhanced flow penetration within the bump regions. Furthermore, the bumps located at the center of three adjacent packages exhibited the least exposure to cleaning flow, suggesting a potential risk of incomplete flux removal in those areas.

 

Bio:
Akihiro Shimizu received his B.E. and M.E. degrees in electrical and electronics engineering in 2005 and 2007 from Okayama University respectively, and his M.S. degree in electrical engineering from University of Colorado at Boulder in 2013. He is currently enrolled in the doctoral program at Gifu University as a working professional and is expected to receive his Ph.D. in September 2025. He joined Ushio Inc. in 2007 and is currently working as a chief engineer, focuing on the surface treatment techniques of polymer materials using xenon excimer lamps and atmospheric pressure plasma, with applications in the packaging and automotive industries.

Abstract:
INTRODUCTION
The wet desmear [1]—comprising swelling, permanganate, and reduction treatments—remains the industry standard for effective smear removal in printed circuit board (PCB) manufacturing. Nevertheless, challenges persist regarding efficiency and environmental impact, as permanganate treatment produces manganese dioxide sludge that requires frequent solution replacement, increasing costs, waste, and safety risks due to its strong oxidizing nature.
To address these issues, the author previously reported at IMPACT 2024 that vacuum ultraviolet (VUV) irradiation using an excimer lamp as pretreatment reduced permanganate time from 15 to 10 min at a VUV irradiation dose of 0.3 J/cm2 or greater [2]. This improvement was attributed to VUV-induced photochemical decomposition of smear, enhancing swelling solution permeability and smear removal efficiency during permanganate treatment. However, excessive VUV irradiation may partially degrade the epoxy resin surface, leading to increased surface roughness during subsequent permanganate treatment.
This study presents a novel approach that balances permanganate time reduction with the preservation of epoxy resin surface quality by optimizing the VUV irradiation dose—a critical trade-off optimization of VUV pretreatment conditions not explored in the IMPACT 2024 study.

EXPERIMENT
A 30 µm-thick glass epoxy resin film (ABF GX-T31) was vacuum-laminated onto both sides of a copper-clad laminate and thermally cured. Blind via holes (80 µm diameter) were formed by CO2 laser drilling. Samples were subjected to VUV irradiation using an excimer transfer device, with the VUV irradiation dose varied from 0.3 to 3 J/cm2. Following VUV irradiation, the wet desmear was performed under the conditions of swelling (60 °C, 5 min), permanganate (80 °C, 10 min), and reduction (40 °C, 5 min) treatments. Surface roughness (Sa) over a 10 × 10 µm area was measured using an atomic force microscope after VUV irradiation followed by permanganate treatment (including reduction treatment) (Fig. 1).

RESULTS AND DISCUSSION
Fig. 2 shows the relationship between the VUV irradiation dose and the Sa, following 10 min of permanganate treatment after VUV irradiation. The Sa increased markedly with increasing VUV irradiation dose, rising from 42.9 nm at 0.3 J/cm2 to 52.9 nm at 0.5 J/cm2, 72.4 nm at 1 J/cm2, and reaching 110 nm at 3 J/cm2. This significant increase in surface roughness at higher VUV doses is attributed to VUV-induced epoxy degradation.
The solid line represents an Sa of 50.7 nm after 15 min of permanganate treatment alone. Remarkably, at VUV irradiation doses of 0.5 J/cm2 or higher, the Sa exceeded this reference, suggesting that the surface may have been roughened more than necessary.
The appropriate VUV irradiation dose should be determined based on the desired Sa, which varies depending on subsequent process requirements. Assuming an acceptable Sa range of 80–120% relative to that from 15 min permanganate treatment alone (41–61 nm, shown by dashed lines), the suitable VUV irradiation dose lies between 0.3 and 0.7 J/cm2.

CONCLUSION
This study demonstrated that excessive VUV irradiation leads to significant surface roughening. Therefore, precise optimization of the VUV irradiation dose—for example, between 0.3 and 0.7 J/cm2—is essential for achieving an effective and balanced pretreatment in the wet desmear PCB manufacturing.

 

Bio:
Dr. Frank Xu, Global Product Manager at MacDermid Alpha Electronics Solutions, brings 18 years of experience to the field of PCB final finishes product development and management. Throughout his tenure, he has been responsible for overseeing research and development of new products, providing crucial on-site support for beta testing and applications, and facilitating direct technical and strategic roadmap discussions with both direct and OEM clients. His expertise is further highlighted by his presentations at numerous technical conferences and his holding of multiple patents.

Abstract:
Printed Circuit Boards (PCBs) are essential components in modern electronics, serving as the backbone for electrical connections. The final finish of a PCB is crucial for reliable solder joint formation, manufacturing yields, and performance of the PCBA. As the industry has moved towards lead-free technology, fabricators have largely abandoned Hot-Air Solder Leveling (HASL). Instead, several alternative finishes - such as Immersion Silver (ImAg), Immersion Tin (ImSn), Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), and Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) - have become well established, each meeting fabricators' specific cost and performance requirements.

Both electroless nickel and traditional immersion gold processes operate at high temperatures (~80 °C) and require long plating times (>10 minutes), making them among the least sustainable of the alternative surface finishes. ENIG and ENEPIG are also the most expensive and complex finishes to implement. Despite this, they remain the most widely used surface finishes by sales revenue, thanks to their excellent shelf life, reliable solderability, wire bond capability, and the rising value of precious metals.

This paper explores strategies to improve the sustainability of ENIG and ENEPIG processes. Each step of the process is examined to identify opportunities for optimization. For electroless nickel, sustainability enhancements include the elimination of dummy plating and a reduction in minimum bath loading requirements. For electroless palladium and immersion gold, the focus is on optimizing precious metal concentrations and controlling thickness distribution. These improvements aim to enhance environmental sustainability while also lowering the cost of ownership. The investigation encompasses both flexible and rigid PCB applications of ENIG and ENEPIG.

Key words: Sustainability, ENIG, ENEPIG, electroless nickel, electroless palladium, immersion gold, cyanide free gold.

 

Bio:
Professor Tzu-Chien Wei is a Chair Professor in the Department of Chemical Engineeringat National Tsing Hua University (Hsinchu, Taiwan). He received his Ph.D. degree in2007, followed by four years of industrial experience (2007–2011), and completed hispostdoctoral training in 2012. Since then, he has been with National Tsing Hua University,focusing on renewable energy and advanced electroless plating technologies. Professor Wei’s research interests include perovskite solar cells, dye-sensitized solarcells, and advanced electroless plating processes. He has published more than 100 peer-reviewed articles in these fields and has received numerous academic honors, such as theProfessor Kao Kwang Memorial Award, the Ministry of Science and Technology Outstanding Research Award, the Environmental Protection Administration Green Chemistry Education Award, the National Tsing Hua University Outstanding Teaching Award, the Future Technology Award, the Wu Ta-You Memorial Award, and the NTHU New Faculty Research Award. In addition to his academic achievements, Professor Wei is also an entrepreneur, having founded three start-up companies: Taiwan Perovskite Technology, Chinghui Perovskite Consulting, and Nihe Advanced Materials.

Abstract:
Palladium (Pd)-based catalysts are indispensable in the electroless plating process of printed circuit board (PCB) fabrication, particularly for initiating copper deposition on non-conductive substrates. However, the deactivation of these catalysts generates Pd-containing wastewater, which is typically outsourced to third-party recyclers. This open-loop approach offers limited material traceability, suboptimal recovery efficiency, and incurs significant cost burdens. To address these challenges, this study presents a simple, in-house method for recovering Pd from electroless plating wastewater and converting it into reusable, active catalysts. Using sodium borohydride reduction followed by nitric acid dissolution and polyvinyl alcohol (PVA) stabilization, we synthesized polyvinyl alcohol-stabilized recycled Pd nanoparticles (R-PVA-Pd). The optimal PVA to recycled Pd (PVA: R-pd) mass ratio of 11.4:1 yielded stable colloidal nanoparticles suitable for catalytic applications. Characterization revealed that R-PVA-Pd derived from two different waste sources maintained consistent particle size distribution and catalytic performance.
Catalytic activity tests demonstrated that R-PVA-Pd exhibited slightly lower activity than laboratory-synthesized pure PVA-Pd but significantly outperformed commercial Pd-based catalysts. Scanning transmission electron microscopy coupled with energy-dispersive spectroscopy (STEM-EDS) confirmed the presence of Pd–Cu bimetallic nanoparticles. Despite a slightly larger average particle size, the R-PVA-Pd catalysts remained highly effective. Their long-term stability was enhanced through ultrasonic dispersion, low-temperature storage, and dilution prior to use. Importantly, the recovered catalyst successfully enabled the plated through-hole (PTH) activation process, validating its industrial applicability. Economic analysis showed that the production cost of R-PVA-Pd was only 1.16% of the market price of equivalent Pd, indicating substantial cost savings and a viable path to circular resource utilization within the PCB manufacturing workflow. This approach not only reduces raw material consumption and waste handling costs but also enhances supply chain transparency and process control—key enablers of sustainable and circular electronics production.

 

Bio:
I am from the Department of Materials Science and Technology of National Yang Ming Chao Tung University and am currently in the first year of my doctoral program. My main research areas are advanced packaging materials and hybrid bonding technology. In this report, I will explain how to use the CSR system platform to optimize the process parameters to produce high-strength copper foils and demonstrate its potential as a collector for lithium batteries in the future.

Abstract:
This study presents the development of high-strength nanotwinned copper (NT-Cu) foils through the optimization of electroplating parameters using the Complex System Response (CSR) platform. By systematically tuning four key parameters—copper ion concentration (0.5 M), chloride ion concentration (49.13 ppm), electrolyte temperature (10°C), and current density (7.11 ASD)—an NT-Cu foil with an ultimate tensile strength (UTS) of 826 MPa, electrical conductivity of ~70% IACS, and ductility of 2.46% was fabricated. The CSR approach significantly reduced the number of experimental iterations required to achieve optimal results. Advanced microstructural characterization using FIB revealed a refined grain structure and high twin boundary density, both of which contributed to the enhanced mechanical performance. Subsequent low-temperature annealing further improved ductility without compromising tensile strength, achieving a peak UTS of 828 MPa. These results demonstrate the efficacy of the CSR methodology in optimizing multi-parameter electroplating systems and underscore the suitability of NT-Cu foils for next-generation lithium-ion battery current collectors.

 

Bio:
I am currently a student at the Academy of Circular Economy, National Chung Hsing University (NCHU), under the supervision of Professor Jenn-Ming Song. I conduct my research in the Advanced Interconnect Materials Lab. My research focuses on nanotechnology, Cu–Cu direct bonding, surface treatment, copper oxide control, and electrochemical analysis. In particular, I am dedicated to developing low-temperature, high-reliability Cu–Cu bonding processes for advanced packaging applications through surface modification and interfacial oxide control strategies.

Abstract:
To address the critical challenge of copper oxidation in Cu–Cu direct bonding for 2.5D/3D semiconductor packaging, this study proposes a novel temporary surface protection approach using molecular nanolayers (MNLs), combined with an effective removal strategy prior to bonding. Three MNLs featuring different chain lengths and functional groups, were chemically grafted onto Cu surfaces to suppress oxidation. Systematic surface characterization revealed that all three MNLs were successfully grafted onto the Cu surface, as indicated by significant increases in water contact angle (from 15° to 98°), confirming uniform molecular coverage. Subsequent electrochemical and XPS analyses demonstrated their effectiveness in delaying surface oxidation. However, residual organics from MNLs can compromise bonding quality. To overcome this, we developed an innovative, contact-free removal technique using VUV irradiation under organic acid atmosphere. This method leverages high-energy photon-assisted decomposition, where VUV irradiation cleaves molecular bonds, while organic acid vapor not only facilitates the generation of hydroxyl radicals (OH•), but also lowers the bond dissociation energy of the molecular nanolayers through chemical interaction, thereby enhancing their photodegradability. The resulting OH• species react with the Cu surface to form Cu(OH)₂, which upon heating dehydrates to Cu–O–Cu linkages, serving as an interfacial bridge that promotes atomic diffusion and strengthens metallurgical bonding. This approach offers a reliable and environmentally friendly solution for enhancing bonding performance and interconnect integrity in advanced packaging.

 

Bio:
2023 – Present Master student, National Cheng Kung University, Tainan, Taiwan 2019 – 2023 bachelor's degree, Feng Chia University, Taichung, Taiwan

Abstract:
Moore's Law claims that transistor density doubles approximately every two years. As transistor sizes shrink and density increases, the performance of electronic devices continues to improve. To meet these demands, optical lithography has become a key technology in semiconductor manufacturing. Early generations of lithography employed mercury lamps with g-line (436 nm) and i-line (365 nm) wavelengths. As feature sizes continued to decrease, these sources were replaced by Deep Ultraviolet (DUV) lithography using 248 nm (KrF) and 193 nm (ArF) excimer lasers. To further extend the resolution limit, immersion DUV lithography was introduced, in which a high-refractive-index fluid is inserted between the lens and the wafer to enhance the numerical aperture. However, even with immersion techniques and resolution enhancement strategies, DUV systems have approached their physical limitations.
As semiconductor devices continue to evolve with shrinking dimensions and narrower line widths, Extreme Ultraviolet Lithography (EUVL) has become a critical process in advanced manufacturing. In this process, tin is used as the light source material. It is excited by a CO2 laser into a plasma state, emitting EUV light with a wavelength of 13.5 nm. Ruthenium is commonly deposited as a capping layer on the EUV mask to protect the Mo/Si reflective layer from contamination and oxidation. The Ru capping layer is easily contaminated by Sn droplets from the light source, which can react with Ru at the interface, leading to Sn contamination and deteriorating the quality of the exposure mask pattern. This interfacial reaction not only reduces the reflectivity of the multilayer mirror but also complicates Sn removal due to the formation of intermetallic compounds. Therefore, understanding the interfacial behavior between Sn and Ru is essential for improving mask durability and ensuring stable EUV lithography performance.
However, the interfacial reaction between ruthenium and tin has not been studied yet. Therefore, this study will investigate the morphology, growth rates, and evolution process of intermetallic compounds (IMCs) of this system at different temperatures and reflow times, and the reaction mechanism under thermodynamics and kinetics will be clarified. This study investigates the reflow process under a vacuum environment of 1 Pa at reflow temperatures of 300°C and 350°C for different reaction times: 24 h, 18h, 12 h, 6 h, and 3 h. The research finds that at the Sn/Ru interface, the Ru3Sn7 intermetallic compound was formed. As the reflow time increases, the IMC thickness increases linearly, exhibiting reaction-controlled behavior. Within this IMC layer, three distinct microstructures are observed: a dense layer, a loose layer, and a solidified precipitate layer, respectively.
This study provides a fundamental understanding of the interfacial reactions between Sn and Ru. Through phase diagrams, thermodynamics, and kinetic analysis, the mechanisms of the interfacial reactions and the growth kinetics of the intermetallic compounds (IMC) will be revealed. This research can help to develop effective processes for removing Sn contamination from the Ru substrate and dealing with the Sn contamination issue.

 

Bio:
Yu Sheng received his B.S. degree in Materials Engineering from Ming Chi University of Technology, New Taipei City, Taiwan, in 2024, and is currently an M.S. student in Materials of Science and Engineering at National Taiwan University of Science and Technology, Taipei, Taiwan. His research interests include electroplating and interface reactions.

Abstract:
This study aims to develop high-temperature lead-free solder alloys. Traditional Pb-Sn solders, with a lead content of about 85–97 wt.%, are widely used for internal electronic connections and high heat-resistant joints, operating at temperatures between 300 and 350°C. These are commonly referred to as high-temperature solders and are applied in electronics, optical devices, and automotive components. However, due to environmental concerns, the European Union has enacted the WEEE (Waste Electrical and Electronic Equipment) and RoHS (Restriction of Hazardous Substances) directives, which restrict the use of lead in electronic products. This study investigates Sn-Zn-Al-Cu base alloys with trace Ni and Ge additions to refine microstructure, control solidification phases, adjust liquidus temperature, and correlate mechanical properties with alloying elements. High-purity Zn, Sn, and Al were weighed in different proportions to prepare 18 groups of Sn-Zn-Al alloys, each with a total weight of approximately 5 grams. Each alloy composition was individually doped with 0.01 wt.% Ni, 0.002 wt.% Ge, and 5 wt.% Cu. To prevent oxidation-reduction reactions between Al in the alloy and the quartz glass, the prepared alloys were first placed in graphite crucibles, which were then inserted into quartz tubes. The tubes were evacuated to a pressure below 10-3torr and vacuum sealed. The sealed samples were placed in a high-temperature furnace at 950°C for 72 hours to ensure uniform mixing of all elements. Subsequently, the alloys were quenched in ice water and extracted. The alloys were mounted in conductive phenolic resin powder and subjected to metallographic preparation. The surface morphology of the alloys was observed using a scanning electron microscope (SEM), and the microstructural composition was analyzed using energy dispersive spectrometry (EDS) or electron probe micro-analyzer (EPMA). X-ray diffraction (XRD) analysis was employed for phase identification of the solidified precipitates, with diffraction peaks compared against the Joint Committee on Powder Diffraction Standards (JCPDS) database. Thermal analysis was conducted using differential scanning calorimetry (DSC) with a heating rate of 5°C/min. The DSC heating curves were used to determine phase transformations and liquidus temperatures. After metallographic preparation, the hardness of the prepared alloys was measured using a hardness tester with a load of 200 gf applied for 10 seconds, and the average hardness values were calculated. Tensile testing was performed using a universal testing machine with a tensile rate of 1 mm/min. Experimental results show that the Sn-Zn-Al-Cu-based alloy produces phases such as (Zn), β-Sn, and CuZn5. The liquidus temperature ranges from 275°C to 375°C, and an increase in Zn content raises the liquidus point accordingly. In addition, the increase of Zn content promotes the formation of (Zn) and CuZn5 phases, which are associated with improved hardness and tensile strength. Al also plays a significant role in mechanically strengthening the alloy. The tested hardness values range from 27 to 85 HV, while the ultimate tensile strength lies between 50 and 86 MPa. Both hardness and tensile strength increase with higher Zn and Al contents.

 

Bio:
Zhi-Chen Ai is a Master’s student in the Department of Mechanical Engineering at National Cheng Kung University. He specializes in the design of low-temperature solder alloys and the analysis of their mechanical properties. In this presentation, he will share his latest advances in applying machine learning to optimize material compositions in the Sn–Bi–X system.

Abstract:
As electronic packaging advances toward fine-pitch technologies, substrate warpage during the 230–250 °C reflow soldering process causes misalignment of solder joints, severely affecting product yield [1]. Low-temperature solders (LTS) such as Sn–Bi (eutectic melting point 139 °C) and Sn–In can significantly reduce thermal stress and have therefore attracted considerable attention [2]; however, the Bi phase in Sn–Bi systems coarsens during thermal aging, leading to decreased ductility and reliability [3]. Traditional composition optimization by adding ternary elements such as Zn, Ge, Al, Ag, and Sb [4-6] can enhance performance but requires extensive trial-and-error, which is both time-consuming and labor-intensive. In recent years, machine learning has demonstrated high efficiency in new-material development, markedly shortening research and development cycles [7]. Therefore, this study employs machine learning to design high-shear-strength alloys and validates the predictions experimentally. Sn–Bi–X (X = Zn, Ge, Al, Ag, Sb) solder alloys were prepared by rapid thermal annealing (RTA). Reflow soldering followed a preheat at 100 °C for 3 min and a reflow temperature of 170 °C for 1 min. Shear strength of the solder joints on Cu substrates was measured at a shear rate of 1 mm/min. The resulting shear-strength data were used to train machine-learning models, which were evaluated based on the coefficient of determination (R²) and root-mean-square error (RMSE). Model predictions and experimental measurements showed high concordance as Ge content increased, indicating that Sn–Bi–Ge solder alloys can potentially reach shear strengths of approximately 70 MPa. This study demonstrates that machine learning can efficiently screen and optimize the composition of Sn–Bi–X low-temperature solders, achieving high shear strength after reflow soldering on Cu substrates.

 

Bio:

Hidenori Abe is CTO for semiconductor materials at Resonac Holdings Corporation and Executive director of Electronics Business Headquarters at Resonac Corporation. He leads electronics materials R&D and strategy for semiconductors, substrates and displays. He was previously head of the Electronics R&D Center and Packaging Solution Center, which is an open innovation hub in advanced packaging development. In that role, he directed the launch of JOINT2 in 2021, an advanced packaging consortium targeting 2.xD and 3D packages.
He served as General Manager of CMP Slurry Business Sector for three years and, before that, was Manager of the Marketing Promotion Group in the Innovation Promotion Center. In his role with the Marketing Promotion Group, he promoted new R&D projects, especially those targeting new market segments using new technologies. He also served as Manager of the Business Development Group in the Packaging Solution Center where he had responsibility for promoting the company’s open laboratory to partners such as customers and equipment makers, and for marketing wearable-related materials.

Abstract:

The cutting-edge semiconductors necessary for the evolution of AI are supported by advances in equipment and material technology. The emergence of chiplet package structures has led to increased complexity in packaging, making collaboration between materials manufacturers and equipment manufacturers more critical than ever.
Resonac, a co-creative chemical company that provides a variety of semiconductor materials such as CMP slurry, etching gas, materials for HBM, epoxy molding compounds, substrate core materials, and more, is advancing materials technology development through open innovation activities. Resonac has started a Packaging Solution Center to propose one-stop solutions for customers and has established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment, and substrates for 2.xD and 3D packages, especially large panel level interposer and large packages. Additionally, we will soon start an open innovation activity in Silicon Valley called “US-JOINT.” In this presentation, we will describe our co-creation strategy.

 

Bio:

Yoshihisa Kagawa is a general manager of Research Division in Sony Semiconductor Solutions Corporation. He joined Sony Corporation in 2004 and he has been a specialist for BEOL and 3D chip stacking process integration. Currently he manages the development of process integration for stacked CMOS image sensors.

Abstract:

Evolution of CMOS image sensors has been realized by the heterogenous integration technologies such as CuCu hybrid bonding, TSV, multi-layers stacking, μ-bump, CoW and so on. Current trends of 3D integrated CMOS image sensors will be discussed.

 

Bio:

Academic Background:
Ph.D. and M.S., Political Science, National Taiwan University
M.S., Electrical Engineering and Computer Science, University of Michigan
B.S., Electrical Engineering, National Taiwan University

Abstract:

Whether in the cloud—inside massive data centers and AI factories—or at the edge, in our smartphones, laptops, and wearables, users everywhere demand energy efficiency.
In today’s world, electricity is computing power, and computing power is national power.
That’s why every major nation now races on two fronts: expanding its energy supply, while also building ever more efficient AI infrastructures. At the very peak of this pursuit lies one goal — the creation of the world’s most energy-efficient logic chips.
And yet, only one foundry on Earth — TSMC in Taiwan — possesses the capability to mass-produce such advanced AI chips.
On the surface, this is a source of national pride. But beneath that pride lies growing pressure — pressure born from the “struggle of Power Transition” between the US and China.
So where should Taiwan go from here?
What international and domestic forces will shape the fate of Taiwan, TSMC, its vast supply chain — and even the great-power rivalry between the United States and China?
Let’s hear Dr. Wu’s analysis…

 

Bio:

M.Bilal HACHEMI, Ph.D., is a Senior Market and Technology Analyst at Yole Group and currently works within the Manufacturing & Global Supply Chain activities. He contributes on a day-to-day basis to the analysis of semiconductor packaging and IC substrates, Glass Core substrate technologies, their related materials, manufacturing processes, and supply chains.

Prior to joining Yole Group, Bilal conducted experimental research in nanoelectronics and nanotechnologies, with a focus on emerging dielectric materials and their ferroelectric sustainable applications. Over the course of his career, he (co-)authored several papers published in high-impact scientific journals and participated in numerous international conferences. Bilal received a Ph.D. in Nanoelectronics and nanotechnologies from Grenoble Alpes University, France. He also completed a management master’s degree at IAE Grenoble.

Abstract:

The impact of the current megatrends driven by Generative AI (GenAI), HPC and data center hardware is spreading over all the segments of the semiconductor value chain, redefining design requirements from Si die to packaging and system-level assembly, and challenging the manufacturing capabilities, from yield to metrology. Among the most strategically impacted industries, yet historically underappreciated, is the advanced IC substrates (AICS). As computing and memory-hungry applications drive increasing demand, IC substrates are no longer just passive mechanical support, they have become a key number in the equation of high-end performance products due to the added functionalities to AICS, and its contribution to enlarging the packaging size while keeping the same level of stability and controlled warpage. This paper provides a comprehensive overview of the IC substrates’ market and technology trends while being at one of the most challenging periods of its history.
We begin by mapping the recent AI accelerators and HPC processors, from AICS’ perspective, and few AICS’ cross sections of NVIDIA’s H100 & H200 to AMD’s MI300X, where the shift toward large-scale sizes, has imposed a new set of functional and physical requirements on AICS. These include significantly increased substrate sizes (exceeding 120 mm x 120 mm), L/S, and layer counts, interconnect densities, power distribution networks, and embedded passive components. From a market standpoint, we identify a split of the AICS industry. On one end, legacy FC-BGA organic IC substrates, continue to serve the highly demanding markets like AI in high-volume data centers. On the other, a new class of large-format, ultra-high-density substrates is emerging, led by glass core substrate and not only. We map these market and technology trends into a roadmap per technology, extending to 2030. We also assess geopolitical and economic influences, including governmental incentives, CAPEX expansions, that are reshaping IC substrate R&D and manufacturing priorities.
In conclusion, this paper frames advanced IC substrates as no longer just mechanical enablers, but as co-design partners in the age of GenAI. With AICS absorbing growing complexity in signal integrity, power delivery, thermal management, and even photonic integration, they are now central to performance scaling in AI systems.

 

Bio:

Ning-Cheng Lee is founder of ShinePure Hi-Tech. Before that, he has been with Indium from 1986-2021, and with Morton Chemical and SCM from 1982 to 1986. He has more than 30 years of experience in the development of fluxes and solder materials for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973.

Abstract:

For electronic industry, due to miniaturization trend, low temperature soldering received great attention mainly attributable to low yield caused by thermal warpage. Obviously the lower the soldering temperature, the lower the thermal warpage.
On the low temperature solder alloys, the most popular system is Bi-Sn based alloys, mainly due to cost consideration. While In-Sn system is also feasible to alleviate the thermal warpage issue, the high cost of In confined it to specialty applications where the cost is no longer a major concern.
During the course of adopting Bi-Sn system, industry experienced a series of significant challenges mainly on the reliabilities. In the first place, the brittleness of Bi-Sn made the handling of manufactured devices being vulnerable, particularly for portable devices. Hot tear is another major issue, which often is associated with Bi-stratification of BGA joints.
In this presentation, the challenges on Low Temperature Soldering will be discussed.

 

Bio:

Charles Lin, founder of Bridge Semiconductor, began his career in 1987 at MCC in Texas. He joined the IME of Singapore in 1993 and moved back to Taiwan to lead the Packaging Division of ERSO/ITRI in 1994. After two years, he returned to Singapore as the CTO of Gul Tech, and then CEO of APS, before assuming the roles of Chairman and CEO of Bridge since 2000.
Charles did his post-doctoral fellowship at the University of Texas, Austin, received his Ph.D. from Case Western Reserve University in 1985, and graduated with a Bachelor’s Degree in Chemistry from the National Taiwan University in 1977.

Abstract:

In recent years, several advanced packaging architectures—driven largely by the demands of high-performance computing—have been introduced by wafer fabs and packaging subcontractors. These approaches utilize “ultra-fine interconnects” as a crucial element to connect logic and high-bandwidth memory chips. Such interconnects are typically realized in different forms, for example: silicon interposers with through-silicon vias (TSVs), currently the most prevalent; organic RDL, offering a more cost-effective alternative; and embedded silicon bridges, regarded as the most balanced option in terms of both performance and cost.

Apart from high-performance computing that embeds a silicon bridge, embedding active chips in a substrate also offers distinct advantages over conventional technologies. This face-to-face stacking structure enables highly compact modules and extremely short current loops, resulting in lower interconnect resistance and parasitic inductance. These improvements can reduce both conduction and switching losses, thereby enhancing overall system efficiency.

Fabrication of an embedded die substrate essentially means building a circuit board around the semiconductor die. There are many ways to achieve this goal. Still, the predominant issues are die placement accuracy, substrate warpage, die cracking, dimensional stability, and many more. In this paper, we present a low-cost approach to overcome these drawbacks by embedding the die in a pre-formed cavity of a molded lead frame. The dimension of the cavity is defined by the etched portion of a metal slug, which is surrounded by a plurality of etched-formed pillar arrays in the molding compound. With a typical thickness of 0.15–0.25 mm, the molded lead frame serves as a free-standing metal core, allowing buildup layers to be deposited on both sides, therefore effectively minimizing substrate warpage.  

 

Bio:

Experience
Taiwan Foresight Co.Ltd
President
September 2010- Present (12 years 4 months)

Zygo Corporation
Field Technical Director
February 2004- September 2009 (5 years 8 months)

Corning Incorporated
Assist Product Engineering Mgr.
April 2003- January 2004 (10 months)

E Ink Corporation
process engineer
1998- 2000 (2 years)

Education
NCTU
Master's degree (1994- 1996)

Abstract:

Selective laser etching (SLE) is a technique we conduct for making through glass via (TGV), that allows the fabrication of straight, taper and even arbitrary shaped via path. In this work we attempt to achieve both via quality and throughput with unique Advanced Optical Engine (AOE) femtosecond laser modification and following by in-house KOH wet etching. As an extensive variety of works have been dedicated that perfect straight via at range 15um~100um diameter (up to 1:100 aspect ratio and >>100 selectivity) at high throughput as result. The AOE optimized to maximize throughput in TGV (Through Glass Via) processing. By transforming the intensity distribution of a high-energy femtosecond laser beam from a Gaussian profile to elongated cylindrical beams, in order to achieve superior precision and efficiency. The use of AOE facilitates cylindrical modifications within the glass volume, utilizing single or burst-mode laser pulses. Its adjustable ring size allows precise control over the diameter of the modified cylinder volume. Coordinating it with fully motorize fix gantry Z and XY high speed high accuracy air bearing motion control stage, AOE is compatible with various types of glass, enabling seamless processing of materials volume up to 600mm x 600mm in 1 mm in thickness. This work utilized AOE femtosecond laser system and in-house KOH wet bench etching system with in situ AOI to illustrate volume production stability in TGV specification of top/bottom diameter, roundness, and position accuracy over thousands of >10K Ø100um TGV 1.1t samples @ 1000 shot/second.

 

Bio:

1.SMTA TAIWAN CHAPTER President
2.IMPACT technical Committee
3.ECTC Technical Committee
4.TPCA Semiconductor Committee
5.IMAPS Taiwan BoD
6.IPC/JEDEC /AEC /SEMI Standard Committee
7.iST Group AVP
8.NCTU Polymer MS /EMBA

Abstract:

 With the AI/HPC coming, high performance server, network and telecom products are required to support increasing infrastructure performance demands. The package size for above application will be getting bigger and bigger to afford GPU/CPU/ASIC plus multiple HBMs on one organic substrate. The mechanical and thermal-mechanical strain on PCB pad caused by the big AI/HPC package will be far more than that from conventional flip chip package. In additional, the ultra-low loss material and Cu foil of PCB are introduced for the high speed/ high frequency requirement, which will be concerned with the interfacial adhesion among low loss resin, glass fiber surface treatment and Cu surface roughness. Therefore, find methodology to characterize PCB pad cratering risk will be necessary for potential risk prediction in the service life field.

Cold ball pull testing is used to validate the resistance of PCB pad cratering for the different ultra-low loss dielectric materials (Dk=3~4.2 and Df <= 0.005 @ 1GHz) in the study. The materials were fabricated in multiple PCB shops using a common test board design utilizing a coupon to result in a 16 mil nominal pad size for the pulls. After fabrication, a 20 mil SAC305 ball was SMT attached to the 16 mil nominal pads for pulling. Each material had 3 coupons with 50 pull locations on each to generate 150 data points for statistical analysis. The peak pull force differences of the material builds can be compared to differentiate the results. As a result, the different ultra-low loss dielectric material’s performance to withstand PCB pad cratering can be compared comprehensively with the cold ball pull test.

 

Bio:

Dr. Kuan Neng Chen is Dean of International College of Semiconductor Technology and Chair Professor at Institute of Electronics at National Yang Ming Chiao Tung University (NYCU) in Taiwan. He received his Ph.D. degree in Electrical Engineering and Computer Science, as well as his M.S. degree in Materials Science and Engineering, both from Massachusetts Institute of Technology (MIT). Dr. Chen has held several prominent positions including Vice President for International Affairs, Associate Dean of International College of Semiconductor Technology at NYCU, Program Director of the Micro-Electronics Program at National Science and Technology Council in Taiwan, Adjunct R&D Director at Industrial Technology and Research Institute (ITRI), and Research Staff Member at IBM Thomas J. Watson Research Center.
Dr. Chen has received numerous awards and honors throughout his career, including IEEE EPS Exceptional Technical Achievement Award, IMAPS William D. Ashmon – John A. Wagnon Technical Achievement Award, Simon M. Sze Heritage Lecture, National Industrial Innovation Award, MOST/NSTC Outstanding Research Award (twice), MOST/NSTC Futuristic Breakthrough Technology Award (twice), Pan Wen Yuan Foundation Outstanding Research Award, CIE Outstanding Professor Award, CIEE Outstanding Professor Award, and IBM Invention Achievement Awards (5 times). He has authored over 400 publications, including 3 books and 7 book chapters, and holds 88 patents. Dr. Chen served as Guest Editor for the MRS Bulletin, IEEE Transactions on Components, Packaging, and Manufacturing Technology, and Materials Science in Semiconductor Processing, and has held leadership roles in various conferences and committees, such as IEEE IITC General Chair. Dr. Chen is Fellow of National Academy of Inventors (NAI), IEEE, IET, IMAPS, and CIEE and member of Phi Tau Phi Scholastic Honor Society.
Additionally, Dr. Chen is Specially Appointed Professor at Institute of Tokyo Science (previously Tokyo Tech). His current research interests focus on three-dimensional integrated circuits (3D IC), advanced packaging, and heterogeneous integration.

Abstract:

Introduction to 3D IC and Advanced Packaging
• Main Schemes and Platforms
• Key Technologies and Fabrication
• Bonding and Hybrid Bonding
• Innovations and Research Achievements
• Applications, Current Status, and Challenges
• Future Perspectives

 

Bio:

Dr. Andrew Tay is currently an Adjunct Professor in the Department of Electrical and Computer Engineering, National University of Singapore (NUS) and a Visiting Scientist at the Singapore Hybrid-Integrated Next-Generation μ-Electronics Centre (SHINE), NUS. Prior to this he was a Professor of Mechanical Engineering at NUS. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include electronics packaging (thermo-mechanical failures, delamination, effects of moisture, solder joint reliability); thermal management of electronic systems and EV batteries, infrared and thermo-reflectance thermography, solar photovoltaics reliability, and fracture mechanics.
He is currently a member of the Board of Governors of the IEEE Electronics Packaging Society (EPS), the EPS Director of Chapter Programs, and a Distinguished Lecturer of EPS. He was the inaugural General Chair of the 1st Electronics Packaging Technology Conference (EPTC) in 1997 and currently the Chairman of the EPTC Board. He was awarded the 2019 IEEE EPS David Feldman Outstanding Contribution Award, the 2012 IEEE CPMT Exceptional Technical Achievement Award, and the 2012 IEEE CPMT Regional Contributions Award. For his outstanding contributions in the application of engineering mechanics to electronics and/or photonics packaging, he was awarded the ASME EPPD Engineering Mechanics Award in 2004. He was also awarded an IEEE Third Millennium Medal in 2000. He is a Fellow of ASME and a Life Fellow of IEEE.

Abstract:

1. Mechanical Properties and Failure of Materials.
2. Hygrothermal Stresses in Microelectronics Packages.
3. Finite Element Analysis and Stress Singularities.
4. Fundamentals of Fracture Mechanics Methodology.
5. Determination of Fracture Mechanics Parameters.
6. Measurement of Fracture Toughness.
7. Experimental Verification of the Fracture Mechanics Methodology.
8. Case Studies on delamination of pad-encapsulant interfaces, die-attach layers and on-chip interconnect structures (BEOL).
9. Cohesive Zone Modelling of Delamination and Case Studies.