Sessions Index

Bio:

Takao Iwaki received his B.Sc. and M.Sc. degrees in Physics from the University of Tokyo, Japan, in 1995 and 1997, respectively, and a Ph.D. degree in Engineering from the University of Warwick, U.K., in 2008.

He has been with DENSO CORPORATION since 1997, where he has primarily engaged in the research and development of MEMS (Micro Electro Mechanical Systems)-based automotive sensors, working both in business units and research laboratories. Since 2020, he has been seconded to MIRISE Technologies Corporation, an automotive semiconductor R&D company jointly funded by Toyota and DENSO. At MIRISE, he has led the research and development of automotive SoCs (Systems on Chip), initially as Director of the Planning and Administration Division and currently as Director of the SoC R&D Division. In 2023, he　began working concurrently with ASRA (Advanced SoC Research for Automotive), focusing on chiplet-based SoC technologies for automotive applications.

Abstract:

In advanced driver assistance systems and autonomous driving, sophisticated AI technologies are employed for functions such as object recognition, self-localization, and trajectory planning. Since the required AI performance varies depending on vehicle type, a wide range of SoCs (Systems on Chip) is needed—from a few TOPS to over 1,000 TOPS per generation. Developing each of these individually is impractical, which is why chiplet technology—where multiple chips are modularly combined like LEGO blocks—is attracting growing interest.

For automotive applications, key technical challenges include ensuring package reliability under harsh environmental conditions and maintaining stable, high-bandwidth communication between chiplets. Addressing these issues is essential for the successful deployment of chiplet-based SoCs in vehicles. This presentation will explore the challenges and potential solutions surrounding chiplet integration in the automotive domain.

 

Bio:

Professor Nogita graduated as an Engineer in Japan in 1990 and worked in the nuclear power industry with Hitachi Ltd. He was awarded a PhD from Kyushu University in 1997. He migrated to Australia in 1999 after accepting a position at the University of Queensland, where he became the founding director of the Nihon Superior Centre for the Manufacture of Electronic Materials (NS CMEM) in 2012 as well as project manager of the University of Queensland – Kyushu University Oceania project (UQ-KU project) at the School of Mechanical and Mining Engineering. He is also an invited Professor at Kyushu University and a Research Adviser at the University of Malaysia Perlis. His research is in three major areas, namely lead-free solders and interconnect materials, energy materials such as hydrogen-storage alloys, and structural and coating alloy development. He holds 20 international patents and has authored over 250 refereed scientific papers. He is a deputy chair for the Electronic Packaging and Interconnection Materials (EPIM) Committee (since 2022), and Leading organiser (2019 and 2023) and Co-organiser of the “Emerging interconnect and Pb-free materials for advanced packaging technology” symposium at TMS in the USA, from 2015 to the current date. He is the recipient of the TMS Research to Industrial Practice Award in 2021.

Abstract:

If electronics manufacturers and users are to have confidence in the reliability of the solder joints on which electronic devices and systems rely, it is essential to have an understanding of the solder joint failure mechanisms and the role of dynamic recrystallisation in failure. However, due to difficulties in real-time atomistic scale analysis during deformation, we still do not fully understand these mechanisms. Here, we report the development of an innovative in-situ method using high voltage transmission electron microscopy (HV-TEM) for observation of the microstructural response of a solder joint to room temperature tensile loading.  This technique was used to observe events including dislocation formation, dynamic recrystallisation, grain boundary separation, and crack formation and propagation in a Sn-3wt.%Ag-0.5wt.%Cu (SAC305) alloy joint formed between copper substrates.

This invited talk provides recent progress introduced at ICEP2025 in Nagano, Japan, detailing how advanced characterisation approaches such as HV-TEM can be used to optimise and develop Pb-free solder alloys and associated intermetallics that form between the solder alloys and substrates of electronic interconnects.

 

Bio:

Yukako Ikegami received her BS and MS degrees from Tokyo Institute of Technology. She worked as a process engineer at Toshiba Corporation. At Toshiba, she was primarily involved in process development, including the development of 3D-NAND.Since 2022, she has been in charge of being a lead process engineer for WoW hybrid bonding for Image Sensors at Sony Semiconductor Solutions Corporation.

Abstract:

Three-dimensional (3D) stacking is a significant trend in advanced semiconductor technology. In structures with three layers, Cu-Cu hybrid bonding is introduced on face-to-face and face-to-back surfaces, electrically connecting through silicon vias that penetrate the middle substrate. During Cu-Cu hybrid bonding shrinkage at the face-to-back interface, the presence of two bonding interfaces makes alignment control critical.
This study investigates the development of face-to-back Cu-Cu hybrid bonding in a three-layer structure and evaluates the impact of wafer warpage on its bonding properties. We examined fine and large-scale Cu-Cu connections with a pitch of 1.4 μm and two million connections, establishing two warpage levels: Process A and Process B. The results showed that Process A had poorer alignment accuracy, leading to open defects at a 1.4 μm pitch, which significantly affected the reliability of the connections. Additionally, we evaluated the connectivity of long daisy chains with 0.7 μm pads, achieving over 90% yield, demonstrating the effectiveness of the bonding process under controlled conditions.
This research emphasizes the critical role of managing wafer warpage to enhance bonding precision and electrical performance. By systematically analyzing the effects of warpage, we provided insights into how variations can impact the overall performance of the bonding process.

 

Bio:

Takumi Yumoto is an engineer of the Products Development Department at Shinko electric industries CO.LTD.
He has been working on Packaging technology development.
Recently, he has also been working on the development of packaging technologies for power semiconductors known as POL (Power Overlay).

Abstract:

In pursuit of developing a low-inductance power module, we engineered a module featuring a POL double-layer facing structure. This design demonstrated a mutual inductance cancellation effect of 14.9 nH, reducing the module’s parasitic inductance to 8.7 nH. Furthermore, by decreasing the inter-module distance to 1.0mm in the simulation, the mutual inductance cancellation effect was enhanced, resulting in a reduction of the module‘s parasitic inductance to 5.5 nH.

 

Bio:

Toshiyuki Takasaki is the manager of the Process Equipment Development Department at Panasonic Connect Co., Ltd, and is responsible for the development of plasma process equipment and respective processes, as well as the total process integration of Plasma Dicing.
In 2017, he joined Panasonic Connect Co., Ltd, as a process engineer. Scince then. he has been in charge of R&D activity and product development of plasma dicing processes.
He received Master's degree of Electrical Engineering from Kyushu University, Japan, and MBA from Graduate school of management, GLOBIS university, Japan.

Abstract:

Hybrid bonding is an essential technology for 3D stacking, and particularly in Die-to-Wafer (D2W) bonding, the die requires an extremely high level of cleanliness equivalent to that of the Front End of Line (FEOL). Plasma dicing has features such as being particle-free and chip-free compared to existing blade dicing methods, making it an indispensable dicing technology for next-generation 3D stacking technology. This presentation will introduce plasma dicing technology that achieves particle-free process and its total solution.

 

Bio:

Kai Takeuchi received his Ph.D. degree from the University of Tokyo in 2020 and currently is assistant professor in Tohoku University, Japan. He has been working on low temperature bonding technologies for electronics packaging inclusing surface activated bonding, plasma activation bonding, ans polysilazane-mediated bonding.

Abstract:

Room temperature wafer bonding using polysilazane as a bonding layer offers significant advantages for advanced semiconductor and MEMS packaging. This study demonstrates strong and reliable bonding of silicon wafers at ambient temperature by converting the polysilazane layer to silicon dioxide through plasma-assisted hydrolysis. The process enables void-free interfaces, reduces thermal budget, and avoids substrate warping typical of high-temperature bonding. Infrared imaging and mechanical tests confirm high adhesion and interface quality. The method is compatible with standard wafer substrates and promises improved yield and process flexibility. These results highlight its potential for next-generation electronic device integration.

 

Bio:

Education:
Master of National Taiwan University (NTU) Executive MBA Program B.A.of Chemical Engineering at NTU

Experience:
Sr. VP of Central Development Engineering in ASE since 2015
Staff Engineering Manager at Motorola Electronics Taiwan. (1999)
Process Engineer in Texas Instruments Taiwan.
Vice Chairman of MEMS Committee , Taiwan Semiconductor Industry Association (2013-2014)
Supplier-chain committee Chair of HiSPA ( Heterogeneously Integrated Silicon Photonics Alliance ) since 2024"

Abstract:

Advanced package by heterogeneous integration has been enable AI related application. Not only high performance computing , but also Optics connection and transmission.
CO packaging Optics (CPO) is the best solution to improve the band width and reducing power consumption. ASE's VIPack (vertical integration packaging) platform would offers the core solution of CPO.

 

Bio:

Akihiro Horibe received his Ph.D. in Materials Science from Keio University in 1998. His early research focused on optical polymer materials for high-speed communication and display systems. He joined the IBM Display Business Unit in 1998 and has been engaged in advanced packaging technologies within the research division since 2007. He is currently a Master Inventor, Senior Research Scientist, and Manager of the Chiplet Interconnect team at IBM Research – Tokyo. His current research interests include advanced chiplet packaging technologies and co-packaged optics. He has presented 10 original papers as lead author at the ECTC Packaging Conferences and holds more than 50 granted patents as lead inventor. He also serves as Chair of the 3D Chiplet Research Working Group of the Japan Institute of Electronics Packaging (JIEP).

Abstract:

Recent advancements in chiplet packaging technologies featuring high-density interconnects for the AI era are presented. These interconnect technologies include not only electrical solutions such as RDL or silicon bridge, but also optical communication technologies, including co-packaged optics.

 

Bio:

Dr. Yung-Jr Hung is a Distinguished Professor in the Department of Photonics at National Sun Yat-sen University, Taiwan. He is internationally recognized for his contributions to silicon photonics, semiconductor lasers, and fiber-optic gyroscopes. Dr. Hung has published more than 160 papers, holds 17 patents, and has played a leading role in advancing Taiwan’s photonics research and industry collaboration. His achievements have been honored with numerous awards, including the National Invention and Creation Award (Gold Medal, 2025), the Future Tech Award (2023), the Da-You Wu Memorial Award (2020), and the IEEE Best Young Professional Member Award (2019).

Abstract:

This talk presents recent progress at NSYSU on multi-fiber and multi-color silicon photonics, offering scalable solutions toward next-generation co-packaged optics and high-speed optical engines.

 

Bio:

With over 30 years of experience in optical communication research and industrial applications, Paul Wu has served as a faculty member in the Department of Optoelectronics at National Central University and has held leadership roles in, and founded, several companies in the photonics sector. His recent focus includes the development of External Laser Source (ELS) modules for AI GPU Link in Co-Packaged Optics (CPO), Meta-Lens Arrays for CPO integration, and advanced Silicon Photonics platforms featuring meta-structures.

Abstract:

In response to the growing demand for CPO (Co-Packaged Optics) modules in AI data centers, the development of scalable optical packaging technologies has become increasingly critical. Among these, the packaging of micro-optical components—particularly those involving Photonic Integrated Circuits (PICs) and Fiber Array Units (FAUs)—plays a pivotal role.
The Meta Lens Array presents a promising solution to streamline the assembly and testing of CPO modules. It offers high-efficiency optical coupling and enables more compact system designs. This presentation will showcase simulation and experimental results related to the integration of meta lens arrays with PICs and FAUs, highlighting their potential to enhance CPO module performance and manufacturability.

 

Bio:

Abstract:

 

Bio:

  E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She was the editor of Recent Developments in Tape Automated Bonding published by IEEE Press. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She is a member of MEPTEC, SMTA, and SEMI. She serves on the JEDEC Task Force JESD-94 Working Group Application Specific Qualification Using Knowledge Based Test Methodology. She has served on the IEEE CPMT Board of Governors for two terms. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium. She received her M.A. from University of Texas, in 1981.

Abstract:

The need for energy efficient AI will be addressed and projections for the future will be provided. This presentation will examine the current trends in power dissipation for today’s AI products. Package options in production and under developing will be presented. Tradeoffs in package architectures, materials (including thermal interface materials), and colling options are described.

 

Bio:

     Terrence Tan is a Senior Director at Microsoft, based in Penang, Malaysia, where he leads the Custom Silicon Test and Manufacturing Operations within the Silicon, Manufacturing and Packaging Engineering group. His responsibilities span Product, Test, Assembly, Quality, and Debug Engineering. With over 20 years of experience in silicon manufacturing, Terrence specializes in co-optimizing packaging, assembly, and test, and has led multiple high-volume manufacturing ramps for advanced silicon products.

Abstract:

     As global computation increasingly shifts to the cloud, Microsoft Azure stands at the forefront with massive infrastructure powering this transformation. To deliver optimal performance, efficiency, and scalability, end-to-end system optimization has become essential. Microsoft is investing in custom silicon to build a vertically integrated solution stack—from software to hardware—tailored for the demands of cloud and AI workloads. This presentation will delve into the silicon, packaging, and manufacturing strategies driving this vision, with a focus on the critical need for co-design optimization across packaging, design, and test. As traditional boundaries between these domains blur, collaborative engineering becomes vital to meet aggressive power, performance, area, and reliability (PPAR) targets.

 

Bio:

     Dr. Suresh Ramalingam is currently VP for Disruptive Packaging Platforms, Office of CTO at Applied Materials. Prior to Applied Materials he was a Corporate Fellow at AMD. His career spans 31 years in Flip chip /Photonics/2.5D & 3D/CPO Packaging Development at Intel, JDS Uniphase, Xilinx, and AMD respectively. He is an IEEE Fellow for his leadership and technology innovation to commercialize 2.5D Silicon Interposer. Dr. Ramalingam holds 137 patents, 50+ publications, SEMI and Ross Freeman Awards for Technical Innovation, ECTC and IMAPS Best Paper Awards and contributed a book chapter on 3D Integration in VLSI Circuits. He graduated in 1994 with a Ph.D. in Chemical Engineering from Massachusetts Institute of Technology, Cambridge after completing his bachelor’s degree from Indian Institute of Technology, Chennai.

Abstract:

     With the remorseless pace of LLM and generative AI model evolution, Advanced Packaging scaling is stressed like never before. TSMC public roadmaps project the need for being ready with >7X reticle CoWoS integration by 2027 and even larger beyond. CPO connectivity for scale out switches is an emerging trend, and future roadmaps could see a need in the scale up domain as well. Power delivery density is another challenging area as GPU compute devices are expected to push well beyond 2kW.
     With these trends, current packaging approaches to scaling 2.5D large integration sizes, assembling on ever larger substrates including photonic connectivity will be challenged and new approaches may need to be explored. In this talk we will explore the challenges, future roadmaps, and the potential of silicon-core based packaging platform

 

Bio:

Abstract:

As AI applications expand from cloud-based data centers to edge computing, TSMC’s 3DFabric^® plays a crucial role in advancing AI and edge technologies. While chip designs increase in density, size, and functionality, challenges such as HBM integration, reliability, and thermal management arise.

CoWoS-R technology offers greater flexibility, enhanced rout-ability, and effective thermal solutions for high-power, high-integration systems.  However, finer pitches lead to higher resistance and RC delay, creating SI/PI performance trade-offs. Designers must co-optimize SoC and HBM integration to fully leverage CoWoS-R technology, carefully balancing the benefits and challenges associated with finer pitch advancements. 

 

Bio:

Dr. Cadmus Yuan is currently a Professor in the Department of Mechanical and Computer-Aided Engineering at Feng Chia University. Dr. Yuan graduated from National Tsing Hua University in Hsinchu, obtaining his Ph.D. in Power Mechanics in 2005, with a major in Solid Mechanics. After graduation, he conducted postdoctoral research at the Technology University of Delft in the Netherlands. He is focusing on applying AI method and Finite Element Method (FEM) to semiconductor packaging design, reliability issues, and smart manufacturing technologies.

Abstract:

  With the advent of cutting-edge technologies such as artificial intelligence (AI), autonomous driving, and heterogeneous integration, electronic packaging has evolved toward more complex and miniaturized architectures—such as chiplet-based systems and high-density interconnects. These advances bring significant challenges to mechanical reliability, particularly concerning solder joint fatigue in plastic ball grid array (PBGA) packages under thermal and mechanical loads.
  To address such reliability concerns, finite element modeling (FEM) has become a widely adopted tool for virtual prototyping. While FEM offers high-fidelity simulations, it remains computationally intensive and requires domain expertise for material calibration, boundary condition settings, and result interpretation. These constraints render FEM impractical for early-stage design iterations that demand rapid evaluation over vast design spaces.
 This invited talk introduces a hybrid framework that integrates AI-based surrogate models with conventional FEM simulation workflows. Rather than replacing FEM, our framework leverages the complementary strengths of both approaches: AI models for rapid inference and exploration, and FEM for high-accuracy validation and critical case analysis. This co-existence strategy enables scalable, cost-effective reliability design in industrial settings.
  A deep neural network (DNN) architecture is proposed as the core surrogate engine. The model is trained on deterministic FEM-generated datasets and designed to capture multi-dimensional, nonlinear design-to-response mappings. Once trained, the surrogate model enables fast approximations, optimization via gradient descent (GD) or particle swarm optimization (PSO), and large-scale Monte Carlo simulations for sensitivity analysis and uncertainty quantification. The resulting insights can be used to filter and prioritize design candidates before passing them to FEM for detailed verification.
This talk will highlight:
The motivation and architecture of the AI-FEM co-design framework.
The methods to train the AI model with new training indicators
The application of the surrogate model in reliability optimization and uncertainty assessment within the AI-FEM loop.
By embedding intelligence early in the design process, this framework bridges physics-based modeling and data-driven inference, enabling more efficient and informed design decisions for next-generation electronic packaging.

 

Bio:
Wataru Doi received joined Murata Manufacturing Co., Ltd. in 2009. He specializes in sealing and bonding technologies for packaging. Since 2021, he has been involved in warpage control for 300 mm COW as part of the WOW Alliance at Tokyo Institute of Technology (Institute of Science Tokyo).

Abstract:
■Introduction
The combination of WOW (Wafer-on-Wafer) and COW (Chip-on-Wafer) has high potential for 3D manufactruing by using well-established BEOL technology [1]. In the previous study, we developed face-down bumpless COW using Via-last TSVs in order to reduce connection impeadance and total packaging volume as shown in Fig. 1 [2][3][4]. Further stacking using such COW technology is expected to enable high-density chiplet systems and is drawing increasing attention [5]. However, the prediction of warpage induced by each stacking layer has not been studied so far. This paper presents FEM-based evaluation of warpage behavior in a double-stacked 3D structure fabricated using a die-patterned waffle wafer, aiming to establish predictive guidelines for multi-layer COW integration.
Double-Stacked 3D Structure
Figure 2 shows the process flow for fabricating a double-stacked 3D structure using a waffle wafer: a) waffle wafer preparation by dry etching, b) mold resin coating, c) thinning back of the Si and resin layers, d) carrier wafer bonding, e) backside Si thinning of the waffle wafer, f) die bonding onto the backside of the waffle wafer, g) resin molding, and f) carrier wafer debonding. The wafer shape at each process step was monitored, and SEM cross-sectional observation was conducted after final carrier debonding in step h.
Warpage analysis
Figure 3 shows the top of view waffle pattern. The waffle wafer is patterned with trenches measuring 3 mm × 3 mm and 70 µm deep, with die-shaped patterns formed inside each trench on the wafer surface [6]. The silicon thickness from the trench bottom to the wafer backside was 705 µm before thinning and 130 µm after thinning. A large die bonded onto the backside of the waffle wafer has a size of 2.8 mm × 2.8 mm × 200 µm. In the FEM analysis, the temperature was varied from 125 °C to 25 °C, with the resin molding temperature assumed as the stress-free reference state.
■Results and discussion
Figure 4 shows the wafer shape at each step during the stacking process. Since there was no supporting substrate, wafer rigidity was reduced, resulting in significant warpage at step h) due to the remaining thick mold layer. Nevertheless, a double-stacked 3D structure was successfully achieved, as shown in Fig. 5. Except for the secondary molding steps, i.e., f) and h), wafer warpage was measured and compared with simulation results, as shown in Figure 6. Up to step e), which corresponds to Si thinning, the simulation predicted wafer warpage with approximately 5% accuracy, indicating that the FEM analysis is effective for warpage prediction. In the case of secondary molding (step g), the measured wafer warpage differed from the simulation by about 20%, which is attributed to non-uniform mold thickness.
■Conclusion
A double-stacked 3D structure using a waffle wafer is demonstrated for the first time to enable prediction of wafer warpage in multi-COW stacking applications. FEM analysis allowed estimation of wafer warpage with approximately 5% accuracy during the stacking process. These results show that warpage can be predicted in advance, facilitating process design for multi-layer COW stacking.

 

Bio:
Master of Material Science and Engineering, NCTU

Abstract:
To achieve miniaturization in module level and board level, component pitch and terminals are getting
finer, denser, and smaller, in which the solder joint are getting less to provide a reliable joint strength, thus
encapsulation is required to protect the joint to achieve reliability requirement. As wireless products begin to
adapt System in Package (SiP) product architecture which use different board material (substrate, substrate
like and FR4), chip design and encapsulation methods (underfill, transfer molding and compression molding).
To achieve products with high stability and reliability, where molded underfill (MUF) by transfer molding
(T-Mold) or compression molding (C-Mold) has been recognized to provide robust reliability and
miniaturization for high density and fine pitch components. Due to the high process temperature (175C) and
high mold flow pressure (5~8Mpa), the thermal and mechanical stress is not only sever to sensitive
component but also requires BT substrate as a MUST. Unfortunately, the lead-time and cost of BT substrate
and the mold tools usually become a bump in the road to innovations, especially in emerging or hi-mix
low-volume early applications. Therefore, a method of low temperature, low pressure and quick lead time
encapsulation is required. In this paper, a vacuum printing encapsulation (VPE) is developed with liquid
printable compound. Three wireless products were selectd with different module sizes and PCB structures
(BT substrate, substrate like and FR4) as test vehicles. Reliability tests (MSL3 and TCT) and function test
(FCT) were conducted to verify the developed VPE for SiP capable of achieving the comparable
performance as the standard T-Mold and C-Mold. It also demonstrates the advantages of the developed VPE
in lead-time saving up to 12+ weeks from mold tools and BT substrate preparation compared with standard
T-mold or C-mold, which provides a miniaturization competence of time-to-POC, time-to-delivery,
time-to-quality, time-to-cost and consequently.

 

Bio:
Hualong Fu is currently pursuing a master's degree at the Institute of Microelectronics of the Chinese Academy of Sciences. His research focuses on fundamental research on the reliability of advanced packaging, especially in the field of fracture mechanics.

Abstract:
The redistribution layer (RDL) enables electrical interconnections between internal and external pins, reducing package size. The fracture resistance of PI-Cu interface in RDL is crucial for interconnection reliability in wafer-level packaging. However, existing studies lack a quantitative evaluation of the location-dependent CZM fracture parameter of PI-Cu interfaces during RDL fabrication, which hinders process optimization for RDL. To address this gap, this study compared and analyzed the shear fracture mechanical behavior of PI-Cu interfaces across various wafer regions using shear testing, combined with simulation-based inversion methods. The results demonstrate that the PI-Cu interface in central wafer region exhibits a mean shear strength (τ) of 109.67 MPa and critical energy release rate (Gc) of 19.5 J/m², both values exceeding the edge. The degree of dispersion of these parameters follows the same trend, confirming that the central interface possesses stronger fracture resistance but greater performance variability. Additionally, the CZM parameters for the central and edge regions were characterized: the maximum τ was 3.4 MPa, the stiffness was 250 MPa/mm, and the relative shear separation displacement was 0.0112 mm, indicating differences from the edge region. This research provides support for optimizing the PI-Cu interfaces.

 

Bio:
I have worked at ASE for over 5 years, specializing in mechanical simulation of advanced package technologies.

Abstract:
With the rapid advancement of high-performance computing and heterogeneous integration, advanced packaging technologies continue to evolve to meet the increasing demand for high I/O density and superior electrical performance. ASE’s Fan-Out Chip on Substrate-Bridge (FOCoS-B) is a promising solution. This structure integrates multiple chiplets through an embedded bridge within a fan-out module, which is then mounted onto a high-density organic substrate. The architecture enables fine-pitch interconnects while offering excellent signal integrity and design flexibility.
Due to the complex material stack and multi-layer assembly process, mechanical reliability especially warpage control has become a critical challenge in FOCoS-B packaging. This study focuses on the warpage behavior at two key manufacturing stages: the wafer-level process and the post-dicing fan-out module step. Finite Element Analysis (FEA) is used to simulate thermal-mechanical deformation and assess key contributing factors including structural and material conditions. Structural factors consider top die thickness, bridge die thickness, and different fan-out RDL stack-up designs. The material factors involve epoxy molding compound (EMC), underfill (UF), and wafer-level carrier. A design of experiments (DOE) approach is applied to systematically analyze the impact and interaction of these variables.
During the wafer process, the properties of the EMC and carrier are crucial and expectedly have a significant impact on warpage. After singulation into individual modules, the combination of the top and bottom EMC becomes even more important. Inappropriate combinations of materials and structure may lead to severe warpage and stress concentration, particularly around the embedded bridge area, posing potential reliability risks.
This study provides key insights into warpage control and mechanical behavior in FOCoS-B structures and serves as a design guideline for improving process yield and long-term reliability in next-generation fan-out packaging.

 

Bio:
Professional Profile: Currently serving as a Manager at the Industrial Technology Research Institute (ITRI), I hold a Ph.D. in Materials Science from National Chiao Tung University. I bring over a decade of hands-on experience in advanced materials analysis, semiconductor device development, and integrated IC packaging technologies. Areas of Expertise: Nanomaterial characterization, including thin-film defect control, thermal stability, and microstructure analysis Semiconductor devices and circuit design, with a focus on flexible LTPS-TFT and advanced thin-film integrated passive and active components IC packaging materials and process development, including Fan-Out Panel Level Packaging (FOPLP) and advanced IC substrates Proven record of innovation with 43 granted patents, 45 academic publications, and 27 technical reports My work bridges research and industry, combining deep technical knowledge with practical engineering solutions to advance semiconductor and packaging technologies.

Abstract:
To meet the demands of high-end IC packaging, the advancement of IC packaging will focus on the re-distribution layer structure in wafer-level packages (WLP) and panel-level packages (PLP). Enhancing computing power requires integrating multiple chips into a single module, which involves establishing high-density connections for communication signals between chips. Thus, the chip-first approach is preferred for achieving these high-density traces. However, scaling line width and via with good reliability is a significant challenge for PLP due to undercut issues and adhesion with Copper. Additionally, the chip placement and molding processes can destabilize IC spacing, leading to die shift, which may disrupt communication signals. To address these issues, adjust seed layer thickness and improve the adhesion between seed layer and dielectric for fine line RDL with good reliability, along with digital dynamic correction during lithography to compensate for die shift. This research successfully demonstrates the feasibility of this structure using low temperature sputtering and Digital Lithography Technology (DLT). The technology has been verified to provide patterning compensation for the RDLs in the chip-first IC packaging structure. The results indicate that the maximum displacement of the chip which can be corrected a horizontal displacement (XY) of 50 μm and an angular displacement (θ) of 0.3° in 4 chips packaging structure. Furthermore, in this case, we also have studies about die shift compensation at high frequency signal (2GHz ~ 20GHz). The result shows the signal loss will be decreased by dynamic tuning ground signal trace width and angle with Digital Dynamic Connection (DDC™) technology. In addition, the 3D4M RDL stacking has good reliability in panel level package structure. Those results show the great potential of high resolution multi-RDLs for chip-first FOPLP application. Moreover, besides its applicability to high-end panel-level packaging in the future.

 

Bio:
Yu-hao Lo is a first-year M.S. student at the Academy of Innovative Semiconductor and Sustainable Manufacturing, NCKU, under the supervision of Prof. Jun Mizuno. His research focuses on microfluidic cooling, bonding technology, and thermal analysis. He previously interned at Tokyo Electron and participated in an exchange program at Tohoku University’s MEMS Laboratory, gaining international and industrial experience in semiconductor processes.

Abstract:
With the rising power density in heterogeneous chiplet packages, thermal management has become a critical challenge for ensuring reliable operation. High-power ASICs with thermal design powers exceeding 400 W demand localized and efficient cooling beyond the capability of conventional air-cooled solutions. This work proposes a microfluidic cooling structure mounted directly above two 400 W ASICs and four 15 W HBM2E modules within a 50 mm × 40 mm package, totaling nearly 900 W of heat dissipation. To enable reliable high-temperature integration, the structure is bonded using Au–Au diffusion bonding. Two device types with identical microchannel geometry were fabricated: one on a silicon substrate using photolithography and deep reactive ion etching, and the other on copper using precision mechanical milling. CFD simulations showed that the Cu–Cu structure achieved better cooling performance, with a maximum surface temperature of 74 °C, compared to 92 °C for the Si–Si structure, consistent with copper’s higher thermal conductivity. Thermal testing was performed by placing the Cu-based device on a 100 °C ceramic heater and recording temperature decay using four thermocouples. Time constants ranged from 5.3 to 63.8 seconds depending on location, with the fastest cooling observed at the center of the channel. Infrared imaging confirmed directional temperature gradients consistent with fluid flow. 3D X-ray imaging verified that both bonded devices had continuous microchannels without collapse, though the Si-based device exhibited edge delamination. These results demonstrate a high-power microfluidic cooling concept using Au–Au bonded structures. Si-based thermal validation is ongoing to confirm simulation trends.

 

Bio:

Dr. Andrew Tay is currently an Adjunct Professor in the Department of Electrical and Computer Engineering, National University of Singapore (NUS) and a Visiting Scientist at the Singapore Hybrid-Integrated Next-Generation μ-Electronics Centre (SHINE), NUS. Prior to this he was a Professor of Mechanical Engineering at NUS. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include electronics packaging (thermo-mechanical failures, delamination, effects of moisture, solder joint reliability); thermal management of electronic systems and EV batteries, infrared and thermo-reflectance thermography, solar photovoltaics reliability, and fracture mechanics.
He is currently a member of the Board of Governors of the IEEE Electronics Packaging Society (EPS), the EPS Director of Chapter Programs, and a Distinguished Lecturer of EPS. He was the inaugural General Chair of the 1st Electronics Packaging Technology Conference (EPTC) in 1997 and currently the Chairman of the EPTC Board. He was awarded the 2019 IEEE EPS David Feldman Outstanding Contribution Award, the 2012 IEEE CPMT Exceptional Technical Achievement Award, and the 2012 IEEE CPMT Regional Contributions Award. For his outstanding contributions in the application of engineering mechanics to electronics and/or photonics packaging, he was awarded the ASME EPPD Engineering Mechanics Award in 2004. He was also awarded an IEEE Third Millennium Medal in 2000. He is a Fellow of ASME and a Life Fellow of IEEE.

Abstract:

Shrinking features and growing device complexity in today’s advanced devices have led to increased challenges in characterizing the thermal behaviour of these devices and their failure. With higher power densities, having a full understanding of the static and dynamic thermal behaviour of the devices is essential for ensuring optimal trade-offs between performance and device reliability. With sub-micron devices, the challenge is even greater as high spatial and temporal resolutions are required. In this presentation, some of the latest techniques of thermal analysis will be described and compared. Two popular non-contacting techniques will be dealt with in greater detail. It was found that thermoreflectance thermography can best meet the challenges imposed by these advanced devices by providing sub-micron spatial resolution and temporal resolution in the picosecond range. When failures occur in a device, a hot spots are usually generated. Thermal analysis can be used to determine the location of hot spots and hence aid in the failure analysis of the device. It can also help to characterize the thermal behaviour, thermal properties, and the thickness of thin films in the device in situ and non-destructively. Using a novel quantum spin crossover
(SCO) material, electromagnetic power intensity can be correlated with temperature. Hence,via a SCO coating, a thermal imaging system can be adapted to characterize the electromagnetic power intensity field of antennas in a much quicker and cheaper manner than current methods. Several case studies will be presented.

 

Bio:
Susmita Mistri is currently pursuing a Ph.D. in the International Program in Photonics at the College of Electrical and Computer Science Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan. She is affiliated with the Institute of Electro-Optical Engineering. Her research focuses on power semiconductor circuit design, high-speed PCB layout, and wide-bandgap devices, particularly GaN and SiC technologies. Her current work involves evaluating the switching characteristics of GaN transistors in advanced converter topologies for high-frequency, high-efficiency power applications.

Abstract:
The ongoing advancements in wide-bandgap semiconductors (WBG), particularly Gallium Nitride (GaN) power devices, have opened new possibilities in high-efficiency, high-frequency power conversion. GaN transistors offer remarkable advantages over traditional silicon-based (Si) MOSFETs, including lower switching losses, faster transition speeds, and improved thermal performance. To fully exploit these advantages in practical converter designs, it is essential to rigorously characterize their dynamic switching behavior under realistic operating conditions. This study presents an experimental evaluation of GaN device switching using a double pulse test (DPT) embedded within a DC-DC Fly-Buck converter topology. The objective of this work is to evaluate GaN switching characteristics under realistic converter stress conditions, rather than in an idealized test environment. The Fly-Buck converter is a modification of the traditional synchronous buck converter that provides isolated outputs through a coupled inductor. It offers a useful platform for evaluating switching devices, as it reflects many real-world effects, such as parasitic elements and coupled magnetic behavior. The test circuit applies a gate-source voltage (VGS) of -3.8V to 6V, typical for low-voltage GaN operation, while the drain-source voltage (VDS) of 50V represents isolated DC-DC converter applications. The double pulse sequence was carefully configured: a first pulse includes a 10 µs initial pulse (T1) to charge the inductor current, a 2.5 µs dead time (T2) allowing the energy to transfer and freewheel, followed by a 2.5 µs second pulse (T3) to trigger the transistor’s turn-on switching under load current conditions. This timing isolates the switching event, allowing accurate observation of transient behavior.
During testing, high-speed measurements of gate-source voltage, drain-source voltage, and current waveforms were captured to observe switching transients such as turn-on delay, turn – off delay, voltage overshoot, voltage ringing, current rise time, and reverse recovery effects of the output rectifier. The results showed that the GaN device switched cleanly and quickly, with minimal energy loss and low levels of overshoot. Fast switching also reduced the stress on the output diode, improving overall circuit performance. Additionally, the fast-switching speeds minimize diode reverse recovery, thereby reducing switching stress and improving overall converter efficiency. The use of a DC-DC Fly-Buck converter as a test platform offers several advantages, including realistic parasitic effects and device stress conditions, which are often absent in isolated device tests. This approach ensures the measured data is highly relevant for actual power converter designs. Furthermore, this work addresses practical challenges such as managing PCB layout parasitics and ensuring clean gate drive signals, which are protecting the device during high-speed switching. The study of Fly-Buck-based double pulse test (DPT) method provides a robust and application-relevant approach for characterizing GaN transistor switching behavior. These findings support the use of GaN technology in compact, high-frequency isolated converters and play a key role in advancing next-generation power supplies with higher efficiency and power density, driving progress in modern power electronics.

 

Bio:
Yi-Chun is currently a 2nd year MS student in the Department of Mechanical & Electro-mechanical Engineering at National Sun Yat-sen University. Her research project focus on understanding the relationship between laser parameters to the dicing quality of 4H-SiC, using a combination of microstructural and micromechanical characterization techniques. This work was funded by ASE and partly NSTC.

Abstract:
Silicon carbide (SiC) in its 4H hexagonal structure is an emerging semiconductor material with excellent thermal, mechanical, and electrical properties. However, due to its high hardness, SiC wafer is also extremely difficult to cut via conventional mechanical methods due to rapid wear and surface damages from the diamond blade. Therefore, a laser-based non-contact technique were developed for dicing the SiC wafer more efficiently but also precisely.
This study focuses on establishing the relationship between laser scribing parameters (speed, power, and frequency) with dicing quality (surface roughness, fracture strength, and Weibull modulus) using a combination of microscopy and mechanical testing techniques.
We first analyzed how the depth and tip distribution of the laser-induced grooves affect the fracture surface roughness. The stress values obtained from the three-point bending tests were then subjected to Weibull analysis, through which we explored the correlation between the statistical parameters and the quality of the resulting fracture surfaces. As shown in Figure 1, varying laser scanning speeds result in different groove depths and fracture surface roughness. Higher laser speeds tend to produce more distinct and uniformly distributed tip features. According to the data in Figure 2 and Table 1, specimens processed at higher laser speeds exhibit improved Weibull plots, indicating that fracture can be initiated under a lower applied load (σth), while achieving higher average fracture stress (σavg) and reliability (Weibull modulus, m)
Experimental results indicate that deeper grooves with sharper and more uniformly distributed tip features lead to improved fracture surface roughness quality. The statistical parameters obtained from Weibull analysis further reveal the differences caused by varying laser scanning speeds and demonstrate a clear correlation with surface roughness characteristics.
The findings of this study contribute to enhancing the cleaving quality of semiconductor wafers and improving surface integrity and process stability. Moreover, the Weibull analysis method adopted here is broadly applicable to other material systems, providing a scientific basis for evaluating and improving the stability, reliability, and performance of manufacturing processes.

 

Bio:
Ayumi Saito was born in Osaka, Japan, in 1999. She received the bachelor's degree in engineering science from Kyoto University, Kyoto, Japan in 2022, the master's degree in micro engineering from Kyoto University, Kyoto, Japan, in 2024. She is currently a group member of the reliability technology group, ROHM company Ltd., Kyoto. Her current research topic includes the study of mechanical properties of epoxy resin for improving the reliability of the power modulus.

Abstract:
We investigated changes in the tensile mechanical properties of EMCs at 150°C by creating different oxidation levels. Please refer to the attached PDF file for the details.

 

Bio:
Ji-Min Lin born in Taichung, Taiwan, in 1985 and received the B.S. and M.S. degrees of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan in 2009. He is currently working in the RF and Signal integrity simulation design field with 15 years of experience for USI, Universal Global Scientific Industrial Co., Ltd

Abstract:
This paper presents an effective approach for identifying the root cause of design issues in power module layouts through physical modeling. The study begins with a design case involving high switching loss and waveform ringing issues in a SiC-based power module, which is more sensitive to parasitic effects induced by the PCB layout due to its faster switching speed compared to IGBT-based power modules. To address this issue, we introduce a physical modeling methodology—commonly used in RF circuit analysis but relatively new in the field of power module design. This method enables engineers to analyze equivalent circuits by mapping them directly to the physical layout and understanding the impact of layout-induced parasitic effect.
Equivalent circuit modeling can generally be categorized into two types: numerical modeling and physical modeling. Numerical modeling is typically generated by simulation software, accurately representing frequency response and providing precise simulation results of circuit behavior. However, it is often difficult to figure out the location of design issues.
To overcome this challenge, we propose a physical modeling methodology that maps PCB layout structures directly to equivalent circuits. This approach helps designers visualize and quantify parasitic inductance and resistance in shared paths between control loop and power paths. Through simulation using a PCB model created by the physical modeling method, we demonstrate that parasitic inductance (Ls) in shared paths is a key factor contributing to increased Eon/Eoff switching losses and voltage ringing. In the SiC power module design, the high-side switching path exhibits nearly three times the parasitic inductance compared to the low-side, resulting in high switching loss issue.
The construction of the equivalent circuit is based on actual current flow. Each circuit element is calculated step-by-step using Z/Y matrix at switching frequencies. This process allows designers to trace current flow paths and identify layout-induced design issues. Based on acceptable switching loss, we define a threshold for the parasitic effect in critical paths and establish design guidelines for layout optimization. In order to avoid this issue completely, we propose the Kelvin connection to separate the control loop from the power path.
This study provides a comprehensive design flow for power module, particularly for SiC-based designs, which are more sensitive to layout-induced parasitic effects due to their faster switching speed. The proposed flow identifying the location of layout-induced issues, defining parasitic thresholds for critical paths, defining design guidelines for layout optimization, and finally proposing good circuit architectures.

 

Bio:
Keisuke Wakamoto was born in Hyogo, Japan, in 1989. He received the B.S. degree in applied physics from the Tokyo University of Science, Tokyo, Japan, in 2013, the M.Eng. degree from Kyoto University, Kyoto, Japan, in 2015, and the Ph.D. degree in engineering from the Kyoto University of Advanced Science, Kyoto, in 2023. He is currently the Group Manager of the Reliability Technology Group, ROHM Company Ltd., Kyoto. His current research interests include die attachment reliability studies by mechanical testing.

Abstract:
We attempted to suppress the CCM by intentionally creating anisotropic porosity in the horizontal direction of the sintered silver (s-Ag) die layer using two pressing methods. "FP" and "LP" refer to the s-Ag formed by pressing the entire top surface of a die attached assembly (DAA) or the SiC chip of a DAA, respectively. The applied force was adjusted to 60 MPa pressure on the pressed area. After DAA process, the DAAs were encapsulated with EMC using thermocompression. The relaiabitly testing methodologies used here were thermal shock tests (TST) and nine point bending tests (NBT). Scanning tomography images after 500 cycles of TST and NBT showed that the LP reduced the inner degradation ratio by up to 21.1% compared to the FP. Cross-sectionalscanning electron microscopy revealed that the FP progressed cracking in the s-Ag die layer, whereas the LP showed no evidence of cracking. The research results demonstrated that our anisotropically porous s-Ag is more reliable than an isotopically porous s-Ag.

 

Bio:
Dr. Yan-Cheng Liu is also the S8 Session Chair, who has long been dedicated to power module packaging topology design, reliability analysis, power system conversion, and power management technology development, and has made significant contributions to the field of power electronics research.

Abstract:
This study aims to expand the traditional lifetime model through correction terms and optimize the lifetime prediction platform. The lifetime model for power cycling (PC) is often limited to fixed module designs, such as specific semiconductor devices, module specifications, or substrate layout. As a result, the lifetime model is difficult to apply to different module variations. To address this limitation, this study focuses on improving the scalability and accuracy of the lifetime model. Considering the failure mechanism of the die-attach solder layer, the influence of power chip size on the number of power cycles is explored. A lifetime model that can be applied to a variety of module designs is established and verified using both commercial and ITRI-developed SiC half bridge power modules. This modified lifetime model can significantly reduce the prediction error between the traditional model and experimental results. It is expected that similar module types produced with different power chip size can still effectively use the modified lifetime model for accurate reliability evaluation.

 

Bio:

Chieh-Sen Lee received the Ph.D. degree in Electrical Engineering from National Cheng Kung University in Tainan, Taiwan, in 2015. He joined Elite Material Co., Ltd in Taiwan as an Assistant Manager in 2022, where he has been involved in projects related to CCL (Copper Clad Laminate) materials for signal integrity analysis, high-speed circuit design for commercial products, and the development of signal integrity test vehicles for high-frequency operations. He has published over 10 IEEE Transactions Journal papers as the first author on topics related to microwave technology.

Abstract:

AI Driving Demand for CCL Materials 

EMC’s Technology-Aligned CCL Portfolio 

Key Design Parameter : Dk

AI-Driven Performance Leader : EM-896 Series

 

Bio:
Joe Hasty is the Engineering Manager for the Flex product line at MKS Inc., where he leads multidisciplinary teams developing advanced laser drilling systems for the PCB industry. Approaching his 20-year anniversary at ESI and MKS, Joe has contributed to the development of flagship machine models such as CapStone, 5335, and RedStone. His background spans systems design, software engineering, and data-driven innovation, including holding multiple patents and a trade secrets. Joe’s current focus is the SPOT ON feature for ESI's CapStone Flex PCB laser drill machines, where he is driving efforts to harness large-scale sensor data and analytics, combined with real-time machine control, to unlock new capabilities, improved quality, and reliability in precision manufacturing. A graduate of Texas A&M University, Joe brings a global perspective shaped by his early years in Tokyo and a lifelong passion for technology. Outside of work, he enjoys soccer, music, and exploring the Pacific Northwest.

Abstract:
The ESI brand has historically dominated the flexible printed circuit board (FPCB) blind via hole (BVH) drilling market by continuously developing cutting-edge technology to enable superior throughput, quality, and yield for high-volume manufacturing (HVM). SPOT ON, a recent technological advancement, is now available as an upgrade for the flagship CapStone product line to deliver even higher yields. Additional benefits include potential increases in throughput, due to decreased dependency on large process windows, and reductions in system downtime, due to a more predictive assessment of beam path degradation over time.

SPOT ON consists of three complementary subsystems: a Beam Characterization Tool (BCT), a Z-height mapping system, and real-time Z-height control. Together, they enable the CapStone to dynamically maintain ideal laser focus during processing.

The BCT is an automatic beam measurement system utilizing knife-edge scans of the focused beam at the chuck. The data gathered describes beam waist location and shape in the X,Y and Z axes. This data is then used to calculate ideal focus, spot roundness, and spot size at the work surface.

The Z-height mapping system employs a capacitance probe to map the work surface. The scanning can be limited to a single map of the system chuck during calibration or expanded to characterize the topology of each panel prior to processing. Preliminary data suggests that significant improvement comes from the chuck calibration alone with no impact to throughput.

Realtime Z-height implements next generation control of the stock Z-stage and motor to smoothly position the focus height to the topology of the workpiece.

Traditional HVM processes rely on large process windows (+/-500um) to maximize yield. This need is due, in part, to a large Z-height budgets comprised of inputs from variations in chuck height, overlays/fixturing, workpiece thickness. ESI legacy systems are designed assuming budgets of hundreds of microns. With the SPOT ON upgrade, CapStone systems can now control focus location to within tens of microns. Large process windows could be a thing of the past and current processes times could be reduced to achieve comparable yields.

Traditional preventative maintenance schedules of laser via drilling systems are based on estimates drawn from statistical data. Greater control and precision can now be achieved with SPOT ON by monitoring beam path health at a configurable cadence without the need for invasive measurements resulting in downtime and loss of productivity.

 

Bio:
Master's student in Professor Jenn-Ming Song's Laboratory, Department of Materials Science and Engineering, National Chung Hsing University, focusing on direct bonding research for advanced semiconductor packaging.

Abstract:
With the rapid advancement of 2.5D/3D IC packaging technologies, the demand for efficient bonding of organic materials has significantly increased. To enable vertical stacking and high-density integration, packaging interfaces must not only possess excellent mechanical stability and thermal conductivity but also satisfy process requirements such as low temperature and short duration. Polyimide (PI), due to its superior thermomechanical properties, electrical insulation, and process compatibility, has been widely adopted as a dielectric and passivation layer in advanced packaging. However, the high curing temperature and substantial thermal budget associated with conventional PI significantly limit its reliability and applicability in hybrid bonding processes. In particular, during low-temperature heterogeneous integration, the chemically inert surface of fully cured PI often leads to incomplete bonding or interfacial delamination, posing a major challenge for the realization of robust integration. In this study, a surface modification technique combining vacuum ultraviolet (VUV) irradiation under different atmospheric conditions, including nitrogen and ammonium hydroxide (NH₄OH), was proposed to tailor the surface chemistry and bonding mechanisms of highly cured PI. Experimental results indicate that VUV treatment effectively modulates the chemical functionality of the PI surface and enables high-strength PI-to-PI direct bonding under low processing temperature (220 °C), short duration (15 sec), and low bonding load conditions (1 MPa). VUV irradiations in N₂ induced phenyl condensation and decarbonylation on the PI surface, while those in NH₄OH led to the formation of amide functional groups, promoting enhanced intermolecular crosslinking and significantly improving bonding strength after thermal compression. Nevertheless, excessive atmospheric treatment leads to residual reactants on the surface and a substantial increase in surface roughness, thereby reducing the joint strength. Moreover, the bonding strength of the jointed samples subjected to post-annealing will be also investigated.

 

Bio:
2018 - 2025 Business Development Manager at RENA Technologies GmbH 2013- 2018 PhD Chemistry, Humboldt University zu Berlin, Max-Planck Institute of Colloid Chemistry and Surface Science 2009 - 2011 Master of Science, Chemiestry, EU-funded master program "Advanced Spectroscopy in Chemistry", University Leipzig Germany, University Lille France

Abstract:
Glass-core substrates are emerging as a next generation packaging substrates offering significant improvements over traditional organic-based substrates. These advancements address critical issues such as warpage, thermal management, and thermal expansion, among other challenges.
The glass panels utilized in new packaging substrates must incorporate a high density of micro-holes, known as through-glass vias (TGVs). These TGVs are subsequently filled with conductive materials, functioning as vertical interconnects for electrical signals or thermal management. The manufacturing process for TGVs, ranging from 30 to 150 micrometers in diameter, necessitates specialized fabrication technologies.
The predominant technique for creating vias involves laser-induced selective etching. This process entails the modification of the glass material via laser treatment, followed by an etching procedure. The laser modification alters the structural properties of the glass, resulting in differential etching rates between the modified regions and the unaltered material, thus enabling enhanced etching selectivity.
At the heart of these glass-core substrates is the glass itself. The possibility to change the CTE (coefficient of thermal expansion) of the glass is one of the biggest advantages of this material coupled with availability in different formats and dimensional stability. Variety of CTE of glasses needed leads to a range of glass types potentially suitable for this application. Each glass type evidences different behavior with respect to processing resulting in diverse types of vias which consequently impact properties of final product. Two extreme examples of this phenomena are straight and X-shape vias. The shapes of vias are significantly influenced by the etching process. Generally, there are two etching processes available for this application: acidic and alkaline etching Hydrofluoric acid (HF)-based etchants are typically used in this context, given their widespread application in conventional glass thinning processes. Although acidic processes are fast, they bring significant drawbacks to the via forms.
In this paper, we present an innovative etching technology based on special alkaline processes. This technology allows precise tuning of via forms. This advanced method achieves significantly higher selectivity compared to traditional acidic etching, while maintaining a processing time that is comparable. Our technology enables the creation of vias with precisely defined shapes and remarkably narrow taper angles, reaching below 1 degree. This is extremely important to achieve close positioning of vias and allows high density. Additionally we show reaction of different glass types to various etching conditions and based on that via form modulation
With our advanced alkaline etching solution combined with laser modification, we are able to manufacture high-density through glass vias (TGVs) substrates for emerging glass-core substrates market. This etching technology allows precise processing of all considered glass types and creating of high density vias for glass-core substrates.

 

Bio:
My name is Tzu-Hsiang Peng, and I am currently studying in the Department of Electronic Engineering at National Yunlin University of Science and Technology, under the supervision of Professor Shih-Hung Lin.

Abstract:
With the rapid advancement of 5G technologies and low Earth orbit (LEO) satellite systems, there is a growing demand for high-frequency, low-loss, and miniaturized circuit substrate materials. However, existing ceramic materials often face challenges such as high dielectric loss, bulky dimensions, and poor temperature stability at millimeter-wave frequencies, limiting their application in high-frequency PCB packaging. This study aims to develop novel microwave dielectric ceramics with optimized structural and dielectric properties that offer high thermal stability, low dielectric loss (low Df), and excellent temperature compensation. The goal is to enhance compatibility with PCB manufacturing and address the performance needs of next-generation high-frequency communication systems.
A-site substituted perovskite-type Na2-2xSrxTa2O6 ceramics were synthesized via conventional solid-state reaction routes, with x ranging from 0.05 to 0.3 and sintering temperatures between 1400 °C and 1500 °C. Structural characteristics were analyzed using XRD, GSAS refinement, SEM, EDS, density measurements, and Raman spectroscopy. The optimized composition at x = 0.1 sintered at 1475 °C exhibited εr = 179, Qf = 12,000 GHz, and τf = +555 ppm/°C, demonstrating high dielectric constant and positive temperature coefficient suitable for compensation. However, the Qf value remains insufficient for direct deployment in high-frequency PCB applications.
To address this limitation, MgTiO3—featuring negative τf—was incorporated to form a composite system. Guided by phase-mixing theory and the high positive τf of the host material, both temperature compensation and loss minimization were achieved. The resulting composite exhibited a significantly enhanced Qf exceeding 80,000 GHz with near-zero τf. More importantly, the sintering temperature was successfully reduced from 1500 °C to 1350 °C through composition and process optimization. This reduction lowers the thermal budget by over 10% and is estimated to cut approximately 1.4 kg of CO2 emissions per sintering cycle, demonstrating substantial potential for low-carbon processing aligned with sustainable PCB manufacturing.
Furthermore, based on the optimized dielectric parameters and a reference filter layout from a 2021 IEEE publication, a microstrip bandpass filter with a center frequency of 3.5 GHz was designed. Simulated and measured results were compared using both the developed MT–NST substrate and commercial substrates (Rogers 4003C, FR-4, and Al2O3). The MT–NST substrate demonstrated superior miniaturization, lower insertion loss, and enhanced frequency stability. With its high dielectric constant (high Dk) and low dielectric loss (low Df), the proposed ceramic substrate exhibits promising potential for high-frequency PCB modules, millimeter-wave communication systems, and LEO satellite applications.

 

Bio:
Department of Materials Science and Engineering, National Chung Hsing University, Taichung 402, Taiwan

Abstract:
A crucial technology for sophisticated electronic packaging is copper-to-copper (Cu–Cu) bonding, especially for uses like high-power devices and 3D integration. Effective Cu–Cu bonding is, however, restricted by two main issues: the development of surface oxides (Cu2O/CuO) and the existence of organic contaminants from handling or cleaning procedures. Weak, voided, or unreliable junctions are the result of these surface imperfections, which also decrease interfacial contact and stop atomic diffusion across bonded surfaces. In this work, we provide a methodical examination of the removal of organic and copper oxide impurities from copper thin film surfaces using formic acid (HCOOH) vapor treatment before thermo-compression bonding (TCB). In order to improve the reduction reaction, copper samples were treated with 1% formic acid vapor at 200°C under a variety of conditions, such as variable flow rates, treatment times, cooling rates, and the use of platinum (Pt) catalysts. To verify chemical alterations and morphological impacts, surface characterization was carried out using FTIR, Raman spectroscopy, XRD, and AFM. Shear strength testing was used to assess the efficacy of thermo-compression bonding. The removal of Cu–O peaks in Raman and XRD data shows that copper oxides are efficiently reduced to metallic Cu by formic acid treatment. The chemical cleaning method was supported by FTIR and Raman, which also verified the elimination of organic pollutants and the emergence of formate-related peaks. Increased roughness (from 1.75 nm to 4.97 nm) on treated surfaces was revealed by AFM analysis, which might affect the interdiffusion between two faying faces. This study offers compelling proof that Cu–Cu bonding strength and reliability may be greatly increased through targeted chemical pretreatment with formic acid, providing a viable path to improving interconnect quality in high-density and high-performance electronic devices.
Keywords: Formic acid vapor treatment, FTIR, Raman spectroscopy, AFM, Organic contamination, Copper-to-Copper (Cu–Cu) Bonding.

 

Bio:
I am Kun-Yuan Zeng a master degree student from National Cheng Kung University material science and technology department investigativeing Cu/SiO2 hybrid bonding and Cu/Cu bonding. My Bachelor's degree is from National Yang Ming Chiao Tung University material science and technology department investigation High entropy alloy's magnetism

Abstract:
The semiconductor industry is facing an increasing demand for electronic components with higher computing performance, lower latency, and greater energy efficiency. This is driven by the development of applications such as artificial intelligence (AI), high-performance computing (HPC), and 5G communication. Hybrid bonding is considered as a key solution to meet these kind of demands.
In hybrid bonding, dielectric-to-dielectric bonding (SiO2-SiO2 bonding) occurs via a dehydration reaction, which create a high temperature and high relative humidity environment let the native copper oxide can easily growth on the copper surface. Additionally, due to different queue time in the production line, nano scale native copper oxide inevitably forms on the copper surfaces make the surface morphology becomes even worse. Therefore, in hybrid bonding process when dielectric-to-dielectric bonding (SiO2-SiO2 bonding) is finishing, and start to performing metal-to-metal bonding (Cu-Cu bonding), the native copper oxide will be exist on top of the copper surface. As a material perspect the ceramic material has a lower electrical conductivity, so that if the native oxide is still exist at the bonding interface it will make device has some serious issue such as Heat dissipation, Poor electrical conductivity and Yield problem. Therefore understanding the evolition mechanism of copper oxide during Cu/SiO2 hybrid bonding is critical.
This study explore critical copper native oxide problem in chip-level bonding structures for heterogeneous integration in microelectronics, focusing on Cu-Cu and Cu/SiO2 hybrid bonding. After the Cu-Cu bonding model was bonded at different temperature, bonding pressure, queue time, native oxide thickness and bonding duration in nitrogen atmosphere, the analysis of transmission electron microscope (TEM) were performed for the bonded structures to explore the bonding behavior of copper oxide evolution during different stage of the thermal compression bonding process(TCB).The result indicated that the copper oxide will become the isolated island structure at the bonding interface between Cu grain, which is transform from thin film structure Cu native oxide at the initial bonding stage in the begining. After the isolated island structure stage the copper island will decompose and dissolute in copper grain and grain boundary remain a void at the bonding interface at above 523K. Futhermore the analysis of Electron Backscatter Diffraction(EBSD) and Transmission Kikuchi Diffraction(TKD) were performed for the Cu grain measurement with different copper native thickness before bonding, the non cross copper grain and void ratio at the bonding interface are increase due to surface morphology and the thickness of native copper oxide

 

Bio:

Dr. Li-Cheng Shen is currently the AVP of Miniaturization Competence Center of USI, focusing on developing and researching cutting-edge technologies of miniaturization. With more than 20 years of experience in the semiconductor industry, Dr. Shen owned more than 30 patents in the fields of Fault Diagnosis System, 3D Package, Wafer Level Package, Opto-electronic Package, Electro-optical Circuit Board, Embedded Component Substrates, RF Module Testing and RF SiP/System Assembly. He is also the technical committee member of ED&A (Electrical Design and Analysis) of ECTC.
In 1998, Dr. Shen received a PH.D. degree in Electrical and Control Engineering from Nation Chiao-Tung University, Taiwan.

Abstract:

- why considering glass
- the system on module on glass (SoMoG)
- how the electrical property of the SoMoG behaves
- how the mechanical warpage of the SoMoG performs
- how the thermal dissipation of the SoMoG achieves
- key process challenges to be identified and solved

 

Bio:

Alex Liu has over 25 years of experience in the semiconductor packaging industry, specializing in equipment engineering, process integration, and advanced packaging technologies. He began his career as an Equipment Engineer and later advanced to process development leadership, pioneering multi-chip stacking and high-density package integration. In 2012, he led 3DIC and TSV technology development with leading IDMs, building a strong foundation for future high-end applications. Since 2016, he has driven the development and mass production of panel-level fan-out packaging, enabling heterogeneous device integration, and has devoted his career to continuously learning and advancing new technology development.

Abstract:

In this talk, we share how the Hi-CHIP Alliance, together with our industry partners, embarked on an accelerated effort to explore glass interposer process integration within a three-month timeframe. By coordinating across multiple companies, we combined expertise and resources to investigate some of the most demanding challenges in advanced packaging.
The presentation will guide the audience through critical process modules—such as precision TGV drilling and wet etching, deposition of Ti/Cu seed layers using advanced PVD, and copper filling strategies with electroplating chemistry. Along the way, we will highlight key technical observations, integration sensitivities, and lessons learned that are highly relevant to manufacturability and reliability.
Rather than focusing on final hardware, this session emphasizes insights gained from tackling real-world hurdles and aligning multi-company collaboration toward common goals. These experiences not only deepen understanding of glass interposer technology but also provide guidance for future development paths in advanced packaging.

 

Bio:

Dr. Jack, Wen-Liang Yeh has a bachelor’s degree and master’s degree in chemical engineering from the National Cheng Kong University, Taiwan and a Ph.D degree in chemical engineering from the National Tsing Hua University, Taiwan in 2008. He started his career job as R&D researcher in the chemical industry and joined Unimicron in 2013 for the development of glass core substrate till now.

Abstract:

Substrate warpage and metal junction are key factors in assembling advanced heterogeneously integrated products. Glass cores can provide dimensional stability, and Cu-Cu direct bonding has the potential to improve power/signal integrity. In this talk, we share our exploration of the Glass Interposer M2M-bonded Core, focusing on design considerations, process flow, and key technical insights gained from integration efforts.

 

Bio:

Dr. Jeng-Ting Li is a Deputy Project Manager in the New Business Department at Unimicron, where he has been engaged since 2018 in the development of advanced glass core substrate processes and Fan-Out Panel Level Packaging (FOPLP) redistribution layer (RDL) technologies. His work focuses on process evaluation, integration, and reliability improvement for next-generation substrate solutions. He holds a Ph.D. from the Department of Materials Science and Engineering at National Cheng Kung University in Taiwan.

Abstract:

Glass core substrate (GCS) technology is emerging as a promising solution for high-density interconnection in advanced packaging. Its inherent advantages such as low dielectric loss, high dimensional stability, and mechanical robustness make it suitable for next-generation electronic systems. A key challenge in GCS fabrication is the reliable formation and filling of Through Glass Vias (TGVs), which require precise control over via drilling, metallization, and dielectric filling. This study demonstrates a panel-level process for building a GCS test vehicle (TV) with dual-side redistribution layers (RDLs). The structure includes six RDL layers and six dielectric layers on a 200 mm × 200 mm glass panel with 400 µm thickness. The TGVs were metallized using conformal copper plating, and the via centers were filled with a vacuum-laminated photo-imageable dielectric. Fine-line patterning was achieved using a dry semi-additive process with a minimum line/space of 10/10 µm. The results confirm the feasibility of integrating materials and processes for scalable glass-based packaging.

 

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Abstract:

In the last 25 years, Chip Package Interaction (CPI) has grown from infancy to necessary consideration for any advanced Si packaging and assembly. The early days saw packaging as an afterthought to protect the valuable high-technology chip. The landscape has clearly changed with Advanced Packaging product architectures bringing raw product performance. Today, advancements in 3DIC’s require broad consideration of substrates, materials, package layout, assembly thermomechanical, and electrical wear out factors to ensure product performance and reliability.

 

Bio:

  Dr. Shin-Puu Jeng currently serves as Vice President of Technology for Heterogeneous Integration Products at Applied Materials. Prior to joining Applied Materials, he was a Director in the New Technology and System Integration, 3DIC, and Special ASIC Divisions at TSMC.
  He received the National Industrial Innovation Award from Taiwan’s Ministry of Economic Affairs and the Outstanding Engineer Award from the Chinese Institute of Engineers (Taiwan) for his contributions to the development of TSMC’s industry-leading CoWoS technology.   He also received TSMC’s Prolific Inventor Award and Best Disclosure Award.
Dr. Jeng has 676 USPTO granted patents, more than 120 conference and journal papers and a long list of awards and professional society affiliations. He received his Ph.D from the University of Florida and conducted his postdoctoral studies at Yale University.

Abstract:

In this presentation, I will provide an overview of current trends in advanced packaging technologies. Drawing on my personal experience transitioning from a foundry to an equipment company, I will share insights into how different sectors within the ecosystem contribute to technology development. In particular, I will discuss the importance of cross-disciplinary collaboration, especially amongfoundries/OSATs, equipment makers, and material suppliers.

 

Bio:

Chieh-Ju Li is the R&D chemist for the electroplating segment at Qnity™, DuPont Electronics. With over eight years of experience in the semiconductor industry, he possesses strong technical and process engineering expertise. Drawing on his experience at TSMC, he has developed critical problem-solving skills that encompass a systematic approach: starting with observation, followed by analysis, hypothesis formulation, and ultimately verification.
Chieh-Ju joined DuPont in 2022 as a scientist and took the lead in developing through-hole conformal plating. In August 2023, he also assumed responsibility for the via-filling copper application. By 2025, his via-filling product successfully penetrated the HDI market, gaining acceptance from customers in China and gradually becoming a staple on their production lines. Currently, he is managing increased customer engagements.
Simultaneously, at the end of 2024, he initiated a new product development project. This promising product has the potential to revolutionize the IC substrate market, achieving exceptional X-via-filling performance with a one-bath solution. It aims to maximize production efficiency while providing greater flexibility in the production arrangements within the PCB industry.
He earned both his Bachelor's and Master’s degrees in Materials Science and Engineering from National Tsing Hua University (NTHU).

Abstract:

With the rapid advancement of high-tech applications such as 5G networks, artificial intelligence, and automotives, the importance of the PCB industry is becoming increasingly apparent. Among these developments, Flip Chip-Chip Scale Package (FC-CSP) technology stands out as a critical driver of innovation. In particular, the hottest topic in the semiconductor field today—IC substrates—features complex structures, where the quality of through-hole filling plays a pivotal role in determining the speed and efficiency of electronic signal transmission. Therefore, the industry is in urgent need of advanced electroplating solutions to meet the demands of next-generation technologies.With the rapid advancement of high-tech applications such as 5G networks, artificial intelligence, and automotives, the importance of the PCB industry is becoming increasingly apparent. Among these developments, Flip Chip-Chip Scale Package (FC-CSP) technology stands out as a critical driver of innovation. In particular, the hottest topic in the semiconductor field today—IC substrates—features complex structures, where the quality of through-hole filling plays a pivotal role in determining the speed and efficiency of electronic signal transmission. Therefore, the industry is in urgent need of advanced electroplating solutions to meet the demands of next-generation technologies.
     At this year’s TPCA Show, we are proud to present our newly developed high-performance copper electroplating formulation designed specifically for FC-CSP applications with a focus on through-hole filling. Our research centers on through-hole filling with one-bath, not only maximize production efficiency but also create flexibility for productive arrangements in PCB factory. By employing Design of Experiments (DOE), electrochemical analysis, and plating validation techniques, we have successfully developed an innovative copper additive system. This formulation features proprietary organic additives that deliver outstanding performance.Moreover, our solution offers simplified bath maintenance, helping manufacturers reduce operational complexity and cost—an increasingly critical factor in today’s competitive PCB market. 

 

Bio:

Michael Chang, Business Development Consultant for Qnity™, DuPont Electronics, brings over 25 years of experience in high-performance film materials for flexible printed circuits (FPC) and advanced packaging applications. With a Master’s in Material Science from National Cheng Kung University (NCKU) and an MBA from National Chengchi University (NCCU), he combines deep technical knowledge with strong business acumen.
As a Business Development Consultant since 2016, Michael focuses on low-Dk PI films for 5G/6G, colorless polyimide (PI) films for flexible displays, and materials enabling electric vehicles. He previously led APAC sales and marketing for PI films (2004–2016) and provided technical support for polyester and PI applications (1997–2004).
Michael is a trusted partner to companies seeking advanced material solutions for next-generation electronics.

Abstract:

As artificial intelligence (AI) applications continue to evolve across both cloud and edge platforms, the hardware demands behind them are rapidly intensifying. High data throughput, efficient thermal management, and space-conscious design are now essential in the development of next-generation servers, AI accelerators, edge devices, and wearables. These demands have driven a renewed focus on advanced flexible interconnects, where material selection is becoming just as critical as circuit design. Kapton ® polyimide (PI) films have emerged as a foundational material in this transformation. Known for their outstanding thermal stability, chemical resistance, electrical insulation, and mechanical durability, Kapton ® films are widely adopted in the production of flexible copper clad laminates (FCCLs) and high-density flexible printed circuits (FPCs). These films are proving critical in high- reliability applications where AI computing modules must withstand repeated thermal cycling, tight bend radii, and increasingly compact footprints.
This presentation is designed specifically for FPC shop engineers and OEM engineers involved in the manufacturing and design integration of flexible electronics for AI systems. It will explore the key performance advantages of Kapton ® PI films in FCCL constructions, highlighting their role in improving lamination quality, signal integrity, dimensional stability, and laser/chemical process compatibility. We will examine the full process chain—from lamination to drilling, etching, and testing—along with design rules and material considerations that help mitigate defects and ensure long-term reliability.
Real-world case studies will showcase the deployment of Kapton ® -based FPCs in cloud server hardware, edge AI modules, and wearable devices. From managing heat in GPU accelerator boards to enabling ultra-thin flexible connections in AIoT sensors, Kapton ® PI plays a critical role in meeting both performance and production requirements.

 

Bio:
Owen Law is a Principal Engineer from Package R&D – Package Design and Modeling, Nexperia Hong Kong. He got his PhD degree from Hong Kong University of Science and Technology. Before he join Nexperia HK, he worked in ASM Hong Kong around 14 years. He focused on semiconductor machine design, manufacturing, and reliability testing. Owen has two granted IPs and is Charted Engineer in IET.

Abstract:
The design of power packages with both high efficiency and high-power density performance while maintaining the highest possible reliability is a challenge. Cu-pillar bumping is a next-generation flip chip interconnection between chip & packages (FCBGA/FCCSP), especially for fine pitch applications. Therefore, one of concerns is the relationship between the initial solder height, pillar shape and solder height after reflowing processes . Especially when mixing bump shapes are used in a die without resulting in too large differences in height after reflowing. To reduce the workload of designers to do technical simulation and working time, artificial neural network prediction and third order polynomial surface fitting are used to predict the reflowed solder height and inter-comparison. Both can be obtained <5% error by comparison with surface evolver simulation results.

 

Bio:
Professor Sheng-Jye Hwang received the Ph.D. degree in mechanical engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 1992. He has been a Faculty Member with National Cheng Kung University, Tainan, Taiwan, since 1992, where he is currently a professor. He has more than 96 SCI journal articles published in the areas of polymer processing, electronic packaging, 3D printing and computer-aided engineering. He is actively involved in industry-academic cooperating researches and has several technology transfers to the industry.

Abstract:
With the advancement of IC advanced packaging technology, improving the process yield and reliability of packaging products has become a significant challenge. For manufacturers, experimental testing and verification require considerable time, financial investment, and production equipment utilization. In recent years, to reduce R&D and testing costs, simulation-based process prediction and analysis have become a key investment focus. Therefore, this study utilizes Moldex3D molding simulation software to analyze System in Packaging (SiP) and establish an optimization process based on Taguchi methods while investigating the importance of interaction effects on process parameters.
To optimize the process, various models are employed to describe the flow and deformation behavior of the package. During the simulation, the Cross-Castro-Macosko viscosity model and Kamal’s cure kinetics model are used to simulate the effects of temperature and degree of cure on the flow behavior of EMC. Meanwhile, Post-Mold Curing (PMC) solver is adopted for warpage prediction, integrating the two-domain modified Tait P-V-T-C model and the dual shift factor model to account for curing shrinkage, CTE mismatch, and viscoelastic behavior. This approach enables more accurate simulation and prediction. The initial parameter analysis identifies that air traps issues predominantly occur behind large chips, attributed to the uniform flow front reaching multiple components simultaneously, leading to air traps phenomena. Furthermore, the study accurately predicts warpage and von Mises stress distribution, which serves as the basis for subsequent multi-objective optimization.
The multi-objective optimization is conducted in two stages: without considering interaction effects and considering interaction effects. In the first stage, key quality indicators including air traps quantity, after PMC warpage, and after PMC average von Mises stress, are optimized using Taguchi methods to evaluate the influence of different process parameters on quality characteristics. A low-resolution orthogonal array (three-level resolution) is initially used for optimization analysis, revealing that the optimal parameter sets for different quality characteristics vary. In the air traps analysis, the most influential factor is the component placement angle; in the warpage analysis, the most significant factor is the ratio of solder mask to prepreg; and in the von Mises stress analysis, the most critical factor is the mold temperature, indicating conflicts and trade-offs among them. However, since low-resolution orthogonal arrays may lead to confounding effects between main effects and interaction effects, the study further considers interaction effects using a high-resolution orthogonal array (five-level resolution) for in-depth analysis.
Results indicate that when interaction effects are considered, the optimized parameter sets differ from the initial analysis and successfully reduce all quality indicator values. The verification simulations confirm that the optimized parameters meet expectations. Additionally, the analysis reveals that PMC duration alone does not significantly affect quality characteristics but exhibits strong interaction effects with Solder Mask and Prepreg ratio, and mold temperature. This finding emphasizes that both main effects and interaction effects jointly influence quality characteristics, highlighting the critical role of considering interaction effects in determining optimized process parameters.

 

Bio:
Kohei Motojima earned his Master's degree in Materials Informatics from Meiji University in Japan, graduating in 2023. Since joining Taiyo Holdings Co., Ltd. in the same year, he has been focused on research involving AI and simulation technologies for packaging materials.

Abstract:
Recently, with the development of AI and Big Data, semiconductor packages are required to have high computation capability. To achieve this, semiconductors are miniaturized, and semiconductor packages are becoming denser and larger. Therefore, controlling the pattern shapes of package materials is essential because they affect long-term reliability. To control pattern shapes, it is necessary to polish and observe cross-sections. The time cost of polishing and observation is over 70% in the observation process of package materials. Additionally, polishing depends on the operator's skill. Hence, to speed up process establishment, it's desirable to reduce the number of experiments and polishing.
In the field of semiconductor resist, there is pattern shape simulation. Using this, we can reduce the number of experiments because we can calculate pattern shapes before conducting them. However, in the field of package materials, there is no simulation of pattern shape. Package materials don’t have the theory of pattern shape to construct simulations because they are complex materials.
In this study. We tried to construct a novel system that reduces destructive cross-sectional observation. To achieve this objective, we used machine learning. Machine learning doesn't require a theory because AI learns the relationship between input data and output data. Novel system combines regression analysis (RA) and variational autoencoder (VAE) which is a type of deep neural network that specializes in image generation. VAE consists of two models: encoder and decoder. The encoder reduces high-dimensional input data to lower-dimensional latent variables Z. By inputting Z into the decoder, the original high-dimensional data is reconstructed. We constructed a VAE model trained with cross-sectional images and RA models that predict Z from experimental conditions. By inputting the predicted Z into the decoder, we can predict pattern shape in cross-sectional images.
As a case study, we dealt with solder resist (SR) cross-sectional images. SR is a negative photosensitive material and has many required functional properties among packaging materials. Generally, it takes several days to several weeks to observe cross-sections from substrate fabrications. The theory of pattern shape has not yet been established.
We constructed the VAE model and RA models. Experimental conditions were spectra and other conditions. Spectra consists of SR absorbance, PET absorbance, substrate reflectance, and exposure intensity. Other conditions consist of dose, development temperature, water temperature, etc. We successfully predict cross-sectional images from experimental conditions.
Next, we tried to optimize process conditions. By inputting the cross-sectional image that we wanted into our system. Our system searched and proposed some process conditions to achieve the inputting cross-sectional image. We experimented under proposal experimental conditions. We got the wanted pattern shape in only a few days.
We succeeded in constructing a novel system to predict pattern shape. It takes only a few seconds from inputting process conditions to outputting cross-section images. The system can reduce destructive cross-sectional observation, which is a significant experimental cost in processing process establishment for packaging materials.

 

Bio:
The speaker is currently a graduate student at National Tsing Hua University, specializing in the simulation of warpage behavior in Fan-Out Panel Level Packaging (FO-PLP). Her research combines nonlinear viscoelastic–plastic modeling and finite element analysis with machine learning techniques to efficiently predict thermomechanical deformation and improve packaging reliability.

Abstract:
As Moore’s Law approaches its limit, Fan-Out Panel Level Packaging (FO-PLP) has emerged as a promising solution, offering high I/O density and excellent area efficiency. However, during the FO-PLP process, the package undergoes multiple stages involving repeated heating and cooling cycles, which often lead to severe warpage. This deformation is primarily caused by two factors. First, the mismatch in coefficients of thermal expansion (CTE) between different materials generates internal stresses due to mutual constraint. Second, cure shrinkage occurs in thermosetting polymers, particularly the Epoxy Molding Compound (EMC), as crosslinking reactions progress under thermal loading. These combined effects can significantly reduce the package’s yield and reliability.
This study employs a nonlinear rheology viscoelastic–plastic material model to simulate the nonlinear behavior of EMC, a complex thermosetting polymer, under thermal cycling. A 3D FO-PLP package model (320 mm × 320 mm) is established using the Finite Element Method (FEM), which reflects actual processing conditions to capture the warpage profile after debonding.
While FEM provides accurate simulation results, its high computational cost makes it impractical to simulate each design condition individually. To overcome this, a hybrid machine learning framework is developed to efficiently predict warpage based on FEM-generated data. The framework integrates three key techniques in sequence: Random Forest (RF), K-means clustering, and Artificial Neural Networks (ANN). RF is first used to classify the warpage pattern based on design parameters and estimate the probability of each pattern. This step captures the complex relationships between geometric inputs and resulting warpage behaviors, and also provides probability estimates used to weight the outputs of pattern-specific prediction models.
Next, Cluster Analysis is applied to reduce the size of the dataset by selecting representative points. This step reduces training time while retaining essential differences in geometric parameters. Finally, two separate ANNs are constructed for different warpage shape categories. These models are trained independently on design parameters to capture detailed deformation behavior. Their outputs are aggregated using Ensemble Learning, with RF-estimated probabilities serving as weighting factors. This structure enables the model to use its classification probability to guide accurate prediction of each warpage pattern.
The proposed framework not only improves prediction precision but also significantly reduces the computational cost of traditional FEM analysis, enabling more efficient warpage evaluation across varying FO-PLP designs.

 

Bio:
Professor Chi-Hua Yu is a scholar in artificial intelligence and advanced semiconductor packaging, with expertise in multiscale modeling and computational mechanics. He earned his Ph.D. from National Taiwan University in 2014 and conducted postdoctoral research at the Massachusetts Institute of Technology (MIT) from 2018 to 2020. Since 2020, he has been a faculty member at National Cheng Kung University, where his research focuses on applying AI techniques—such as deep learning, reinforcement learning, and generative modeling—to the design and optimization of electronic packaging systems. His work addresses key challenges in thermal management, mechanical reliability, and structural innovation for 2.5D/3D IC and fan-out packaging technologies. In parallel with his academic role, Prof. Yu is the founder and Chief Technology Officer of NeuroShine Ltd. Co., a university spin-off committed to developing AI-driven EDA tools for intelligent semiconductor design and advanced manufacturing. His combined academic and entrepreneurial efforts seek to bridge artificial intelligence with next-generation electronic system design.

Abstract:
Flip-Chip Bonding (FCB) has become a cornerstone technology in the advancement of electronic packaging. By flipping the chip and directly attaching it to the substrate using micro-bumps, FCB significantly shortens interconnect lengths, lowers electrical impedance and signal delay, enhances bandwidth, improves heat dissipation, and increases packaging density. These advantages make FCB indispensable in high-performance electronic systems. However, one persistent challenge lies in the mismatch of coefficients of thermal expansion (CTE) between the chip and the substrate. During high-temperature processes such as reflow, this mismatch generates thermal stress concentrations, which can result in solder joint cracking, interfacial delamination, and excessive warpage—ultimately degrading the structural integrity and reliability of the package.
To address the issue of warpage induced by CTE mismatch, this study focuses on optimizing the geometric design of a magnetic cover jig used in the FCB assembly process. The cover jig plays a critical role in applying constraint forces during reflow to control deformation. Traditional optimization methods rely heavily on domain expertise and repeated simulations across diverse material and process conditions. Such trial-and-error strategies are often time-consuming and resource-intensive, making them impractical for rapid design iteration. To overcome this bottleneck, we propose a reinforcement learning (RL)-based design framework capable of autonomously exploring high-dimensional design spaces to identify optimal geometric parameters for the cover jig.
A high-fidelity finite element model was first established using Abaqus, incorporating realistic thermal loading profiles, fixed boundary conditions, and complex multi-surface contact interactions to faithfully replicate actual manufacturing scenarios. While Abaqus provides a graphical user interface (GUI), it also supports Python scripting, which we leveraged to automate the entire simulation process. Through seamless integration of Python-based geometry generation, simulation control, and result extraction, we constructed a fully automated design-evaluation loop. This loop is connected to an RL agent that iteratively learns from simulation feedback and adjusts the design parameters to improve warpage performance.
Importantly, our approach does not aim merely to minimize absolute warpage. In real-world conditions, a perfectly flat substrate does not necessarily guarantee successful bonding. Due to thermal stress, geometric asymmetry, or material heterogeneity, the die itself may exhibit intrinsic warpage. Over-flattening the substrate may lead to misalignment during bonding, causing local stress concentrations and potential reliability issues. Therefore, achieving warpage compatibility between the substrate and die is crucial for high-precision packaging.
To this end, we propose an engineering-oriented scoring system that enables the RL model to go beyond single-objective optimization. Instead of blindly pursuing minimal warpage, the model is trained to generate specific warpage profiles that align with the deformation contour of the die. By matching the spatial warpage distribution of the substrate to that of the die, we enable more effective mechanical coupling and stress mitigation during bonding. This strategy not only enhances the quality of die-to-substrate attachment but also improves overall yield and long-term package reliability.

 

Bio:
The speaker is a graduate student at National Tsing Hua University, focusing on reliability simulation of wafer-level packaging. His work involves finite element analysis and AI-assisted modeling methods to accurately predict solder fatigue life under thermal cycling.

Abstract:
Wafer-Level Packaging (WLP) has become a key technology in modern semiconductor manufacturing, enabling high-density integration, excellent thermal performance, and reduced form factors. However, solder joints in WLP are highly susceptible to fatigue failures under thermal cycling, making accurate lifetime prediction of solder balls essential for reliability assessment. While finite element analysis (FEA) provides accurate predictions, it is computationally expensive and inefficient when evaluating a wide range of design variations.
To address this issue, we propose an AI-assisted framework that integrates experimentally validated simulation models with machine learning techniques for efficient solder ball fatigue life prediction during the design phase. Initially, FEA models were manually constructed and validated against experimental thermal cycling test data across five WLP configurations (TV1–TV5). Once the accuracy of manual modeling was confirmed, a Python-based automated script was developed to generate 2D ANSYS models based on design parameters. The automatically generated model under the TV2 configuration was further validated by comparing results against both manual simulation and experimental data. Upon confirming that the prediction errors were sufficiently small, we generated a large dataset with varying solder ball geometries and package structures for machine learning training.
We then trained multiple supervised learning models using the simulated dataset, including Artificial Neural Networks (ANN), Recurrent Neural Networks (RNN), Support Vector Regression (SVR), Kernel Ridge Regression (KRR), Gaussian Process Regression (GPR), Random Forest (RF), Extra Trees (ET), k-Nearest Neighbors (KNN), and Polynomial Regression (PR). To explore the impact of dataset size on model performance, we designed six different training dataset sizes (256, 625, 1296, 2401, 4096, and 9000 samples). Each model underwent grid search-based hyperparameter tuning and was tested with various data preprocessing strategies.
The results show that, with appropriate model selection and training data size, prediction errors can be maintained within 1% of FEA simulation results, while significantly reducing the simulation time required during early-stage package design. We further conducted a systematic comparison of training time and prediction accuracy for each algorithm under different data scales, aiming to identify models that provide optimal trade-offs between computational efficiency and predictive precision. This study demonstrates the feasibility and practicality of data-driven AI models for solder ball fatigue life prediction, offering a scalable approach for future extension to 3D packaging or other complex reliability scenarios.

Keywords – Wafer-Level Packaging (WLP), Finite Element Method, Solder Ball Fatigue Life Prediction, Artificial Intelligence, Machine Learning.

 

Bio:
Professor Sheng-Jye Hwang received the Ph.D. degree in mechanical engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 1992. He has been a Faculty Member with National Cheng Kung University, Tainan, Taiwan, since 1992, where he is currently a professor. He has more than 96 SCI journal articles published in the areas of polymer processing, electronic packaging, 3D printing and computer-aided engineering. He is actively involved in industry-academic cooperating researches and has several technology transfers to the industry.

Abstract:
With the advent of artificial intelligence, semiconductor process nodes continue to advance to meet the demands of high-performance computing (HPC) chips for high-speed computation and massive data transmission. Chip packaging technologies have also evolved to address design challenges such as high bandwidth and large counts of I/O, extending from traditional 2D packaging to advanced 2.5D and 3D architectures. Among these, Fan-out Wafer-level Packaging (FOWLP), with its high routing density, excellent electrical performance, and effective heat dissipation capabilities, has been widely adopted in high-end chips and mobile devices, becoming one of the most prominent packaging technologies in recent years.

However, the FOWLP process involves multiple cycles of high-temperature heating and cooling, during which differences in the thermal properties of materials can lead to structural warpage. If the amount of warpage exceeds the allowable range, it can reduce process yield, cause packaging failures, or hinder subsequent process integration, ultimately affecting product reliability. Therefore, accurately predicting warpage behavior at each stage of the packaging process has become a key issue for improving process stability and packaging yield.

This study focuses on the FOWLP structure and conducts thermal stress simulation analyses of various stages in the RDL-first process, investigating the influence of different process temperature settings on warpage behavior. Using finite element simulation tools, six actual structural and material combinations were systematically analyzed and validated against experimental measurement data. The results show that the simulation process established in this study maintained a maximum error of within 20% across all cases, demonstrating good accuracy and reliability. Notably, simulations using the average reference temperature setting were the most consistent with experimental values, slightly overestimating the actual warpage, enhancing the warpage prediction's accuracy and credibility.

Building on this foundation, machine learning techniques were introduced. Based on data generated from simulations, warpage prediction models were trained using algorithms such as XGBoost and artificial neural networks (ANN). Feature selection and hyperparameter optimization were applied to improve model accuracy, successfully controlling the prediction error within 15%.
Compared with traditional approaches that construct separate prediction models for each specific structure type, this study proposes a recursive input modeling mechanism based on the number of structural layers. This enables the model to accommodate varying package stack designs and supports layer-by-layer recursive prediction.

To further enhance the generalizability and practical applicability of the model, a sequential prediction strategy was adopted to build a single recursive neural network architecture. It allows the model to estimate the warpage behavior of subsequent layers based on the predicted results of previous layers. This method overcomes the limitations of training separate models for each packaging configuration, significantly reducing the need for finite element simulation data and lowering the time cost of model training while improving model scalability and adaptability for multi-layer package designs.

This study combines finite element simulation with machine learning-based recursive prediction methods to establish an accurate and highly scalable warpage prediction framework. It is expected to serve as a valuable tool for early-stage warpage evaluation and process optimization in advanced packaging design, enhancing packaging development efficiency and process stability.

 

Bio:
You-Sheng Song is the Bachelor of Science (B.S.) in Department of Mechanical and Electro-mechanical Engineering at National Sun Yat-sen University. He is an IEEE Student Member in 2025. He has been working in the general areas of microelectronic packaging, simulation mechanics, and dynamic material response packaging since joining the member of the MOEMS laboratory group in 2024. His research involves analyzing, and modeling the failure mechanisms in Chemical Mechanical Polishing (CMP). The research is leading to practical approaches for microelectronic package design. Over the past 2 years, he has been working extensively in the area of dynamic loading of mechanical and CMP Retainer Rings for Wafer-Edge Integrity. In 2024, he has participated in an industry academia collaboration project with TSMC with Professor Mei-Ling Wu.

Abstract:
This study focuses on Chemical Mechanical Polishing (CMP), a process involving a three-body rotational system composed of a polishing pad, wafer, and retaining ring, working in conjunction with polishing slurry. Polishing pads form a stable grinding reference surface through high rigidity carrier platen, while wafer rely on independent airbags in multiple zones to clamp and rotate in synchronization with carriers or with a slight difference in speed to achieve fine and uniform material removal. Over prolonged polishing durations, retaining ring undergoes deformation, which causes uneven pressure distribution and thickness reduction at silicon wafer edge. This research employs finite element method simulation (LS-DYNA), experimental validation, and theoretical analysis to investigate mechanisms of retaining ring geometry and material properties affecting stress distribution and thickness thinning at wafer edge. Through analytical simulation strategies, we predict wear behavior and structural deformation of retaining ring under 100 hrs. of continuous polishing. By comparing simulation model with empirical data, study aims to extend lifespan of retaining ring and reduce wafer edge damage. Future results are expected to be applied to smart CMP process monitoring and fixing ring design optimization to improve wafer edge quality and production line reliability.

 

Bio:

Dr. Chong Leong, Gan received his B.S. degree in Chemical Engineering from National University of Malaysia in 2000, M.S. degree in Chemical Instrumentation in 2003 from University Science Malaysia, and Ph.D. in Nanoelectronic Engineering from University Malaysia Perlis, Malaysia in 2015. He is Senior Member of IEEE, Fellow of Institution of Engineering and Technology, Fellow of Institute of Materials, Minerals & Mining, UK., Fellow of Institute of Physics, UK., and Royal Society of Chemistry, UK. Since 2000, he has been with Silterra Malaysia, Quality and Reliability MTS with Altera, Product Engineering with Osram Opto-Semiconductors, Broadcom, R&D Engineering with SanDisk and currently working as Package Characterization Director with Micron Taiwan. He is recipient of IEEE EPS Distinguish Technical Leadership Certificate in 2021, Emerald Outstanding Journal Reviewer in 2021 and ASME JEP Reviewer of the Year in 2022. His research interests including semiconductor packaging reliability, electronic packaging materials characterization, nanomaterials, and radiation reliability. He has published more than 75 international journal articles, 1 book with Springer Publisher. CL serves as Editorial boards with more than 25 international journals, Guest Editor with Elsevier Materials Science in Semiconductor Processing and Emerald Microelectronics Internal journals. He has 30 patents issued/ filing in US and China patent offices.

Abstract:

  With the recent innovation of Open AI (Artificial Intelligence) and AI humanoid robots’ applications, this has triggered the growth of data center infrastructure as processing, storage, and communication system in the digital world. The data center itself has contributed 1.5 % to the total world electricity consumption and this is expected to increase with time. Continuous higher demand for low power, larger data storage and faster data rates are pushing the suppliers to provide the advanced packages solutions such as NAND-Based MCP (Multiple Chip Package), HBM (High Bandwidth Memory), immersion-cooled and future cryogenic memory computing in AI
deployments in datacenters, humanoid robots as well as future quantum computing.
  This talk lays out the technical requirements of semiconductor electronics materials roadmaps, development, and properties with closer interactions on packaging robustness. It encompasses its package strength, component and solder joint reliability, package warpage performance, thermal dissipation as well as radiation induced soft errors, which become more important due to higher susceptibility of these packages to external thermal-mechanical stresses in AI datacenter applications. Evolution of these key assembly materials will be discussed in terms of its technical challenges and enabling reasoning as well as possible failure modes and mechanisms to address the needs and callouts for identifying those key materials characteristics which are critical to memory system level packaging.

 

Bio:
Satoshi Osawa is a research and development engineer at NIHON GOSEI KAKO Co., Ltd., where he is engaged in the development of epoxy resin-based encapsulant compounds for electronic and electrical applications. His work focuses on optimizing the formulation of liquid-type epoxy compounds to meet stringent reliability requirements, such as heat shock resistance. In this presentation, he introduces the features and reliability performance of an existing liquid encapsulant developed by the company, highlighting its suitability for electronic applications and its potential to streamline manufacturing processes.

Abstract:
[Introduction]
Epoxy resin encapsulants play an important role in electronic and electrical applications such as semiconductors. Epoxy resin encapsulants has good providing vibration isolation, waterproofing, chemical resistance, and component protection. However, optimal resin compounding is required to pass long term reliability tests such as the heat shock tests.
In this study, we report on the design concept of materials that can withstand heat shock tests and the characteristics of our newly developed product.

[Investigation]
-material design concepts that can withstand heat shock tests-
1) design the material so that the Tg exceeds the required heat resistance temperature, and set the Tg within the α1 range.
2) blend in a flexible resin with a Tg below the required heat resistance temperature to allow it to follow changes in other components

[Representative issues with current flexible resins]
・silicone resin: excellent heat and water resistance, but issues include contact failure due to siloxane, adhesion, and cost
・urethane resin: reasonable price, but issues with heat resistance, water resistance, and chemical resistance
・epoxy resin: excellent in strength, toughness, chemical resistance, etc., but many filler-blended products are hard and flexible products are rare. In addition, two-liquid type epoxy resins entrap air when mixed, so air bubbles on the surface and inner cured product are an issue.

-characteristics of the newly developed product ER-6506-
Er-6506, which we developed, is a two-liquid type epoxy resin-based encapsulant, but the cured product is flexible, so it can be used as an encapsulant for electronic and electrical applications that satisfy reliability evaluations such as heat shock tests. Furthermore, er-6506 has high fluidity and good bubble breaking properties, so a cured product with excellent appearance can be obtained even without a degassing process. This may contribute to simplifying production lines and reducing manufacturing costs.

 

Bio:
Dr. Thomas is a highly qualified professional, having obtained his PhD in Chemistry from the prestigious Freie Universität Berlin in Germany. Dr. Thomas joined MKS Atotech as a R&D scientist in 2014. Since 2019, Dr. Thomas has held the position of Global Product Manager in the Electronics Business division at MKS Atotech.

Abstract:
As IC substrate technology advances towards fine lines and higher circuit densities, there is an increasing demand for copper (Cu) surface preparation to ensure reliable adhesion with lamination materials and resistance to external stress conditions. At the same time, it is essential to ensure process efficiency and support signal integrity. Conventional approaches often rely on multi-step roughening techniques to maintain adhesion in the presence of thermal, humid and chemical stresses between Cu and the dielectric. However, these techniques compromise the integrity of the Cu surface and are incompatible with the requirement for ultra-smooth conductors.
This study presents an innovative, self-synthesized, organo-silane-based adhesion promoter designed to form strong chemical bonds between dissimilar materials such as various dielectric laminates and Cu surfaces (including electrolytically plated Cu). Unlike traditional roughening-based systems, our non-etch solution enables a streamlined two-step process that simplifies manufacturing, reduces costs, and maintains the high bond strength required for next-generation packaging, eliminating the need for aggressive copper etching, our non-etch solution allows for the creation of narrower lines and spaces, which are essential for advanced IC substrate designs.
The system also demonstrates excellent chemical resistance to desmear process, which is necessary to clean blind microvias (BMVs) after laser drilling and prepare them for subsequent Cu filling. Smooth Cu surfaces typically struggle in these harsh conditions, but post-desmear testing of structured designs confirmed the integrity of the sidewalls and minimal wedge formation at the BMV interfaces. Roughness measurements show that our process does not alter the original surface topography. Extended IR Reflow and high-temperature accelerated stress testing (HAST) provide further validation of the durability of the interface. The effectiveness of the promoter in maintaining strong Cu-dielectric bonding under harsh stress conditions is demonstrated by FESEM and FIB analysis.
As a global leader in laser, desmear chemistry and surface treatment, our understanding of interfacial processes extends beyond adhesion alone. This allows us to support customers with fully integrated bonding solutions, combining advanced materials, process integration and application expertise to meet the evolving demands of IC substrate manufacturing.

 

Bio:
Kuan-Cheng Liu is presently Engineer of material technology department of R&D at Siliconware Precision Industries Co., Ltd. (SPIL) Over 1 years of job experience in semiconductor industry (focus on assembly field) and he is in charge of new advanced material development and management in SPIL currently. He has authored/co-authored 1 papers and 2 patents in the advanced packaging field.

Abstract:
In recent years, there has been a shift towards high-density layouts and multi-chip integration in semiconductor packaging technology, resulting in significant challenges regarding package reliability and process efficiency. Against this backdrop, Ball Grid Array (BGA) packages are widely used in high-end computing and communication applications thanks to their high pin count and excellent electrical and thermal performance. However, foreign particulate deposits appearing on the surface of solder balls after reflow can adversely affect the mechanical strength and electromagnetic behaviour of solder joints.
This study involved conducting a surface analysis of soldered balls using scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDS). The results revealed that the main component of these particulates is copper. A systematic comparison of different solder alloys and substrate surface finishes (Cu-OSP and Ni/Au) confirmed that copper particle precipitation occurs exclusively when substrates with a Cu-OSP finish are used. Further experimental analysis showed that during initial reflow, flux chemically activates and dissolves copper atoms from the Cu-OSP substrate. These copper atoms are then transported into the molten solder, where they become supersaturated and subsequently precipitate onto the solder ball surface during cooling. Increasing the number of reflow cycles facilitates the re-dissolution of these particles back into the solder. Conversely, reducing the flux acid value and application volume effectively suppresses their precipitation.
This work clearly identifies the Cu-OSP pad as the origin of the copper particles and explains how they are formed via flux-assisted dissolution and precipitation during reflow. These insights enable targeted process optimisation, such as adjusting the flux chemistry and thermal processes, to effectively eliminate copper precipitation. Implementing these measures can improve solder joint quality in BGA packages, thereby supporting the development of stable, high-performance packaging solutions for advanced electronic applications.

 

Bio:
Garian Lim is the Strategic Business Development Manager for Semiconductors at DELO Industrial Adhesives Singapore. With over 20 years of experience in the semiconductor industry, he has held various roles in product development, research and development, sales, and process integration. Before joining DELO, he held position in companies such as Amkor, Statschippac and MacdermidAlpha. Garian holds an B.Eng & M.Eng in Mechanical Engineering from Nanyang Technological University Singapore.

Abstract:
The advent of 5G and artificial intelligence (AI) has driven explosive growth in high-speed data communications, spurring the development of new packaging technologies such as 2.5D/3D advanced packaging for AI applications. Among these silicon photonics packaging is emerging as a promising technology.

Despite significant advancements in electronics packaging, the packaging of photonic integrated circuits (PICs) still faces substantial challenges in achieving high performance and reliability. The silicon photonic packaging process involves numerous technical hurdles, such as the necessity for highly precise and rapid active alignment for optical coupling, reflow and environmental reliability, and managing thermal performance effectively.

This paper provides a comprehensive overview of the key bonding tasks within a photonic package and explores the specific adhesive requirements. In this context the paper focuses on the optical and mechanical properties of adhesives and its capacity to maintain performance under diverse operational conditions with experimental data.

Furthermore, the paper introduces a novel wafer-level photonic packaging approach that preserves optical properties through wafer-level processing steps such as sawing and grinding with experimental data demonstrating its effectiveness.

 

Bio:
Dr. Yu received his Ph.D. in Chemical Engineering from Tsinghua University in 2002. He began his career at the Industrial Technology Research Institute (ITRI), working as a researcher in the Chemical Engineering Division from 2003 to 2007. He then joined Taiwan Semiconductor Manufacturing Company (TSMC), where he contributed to the development of advanced manufacturing processes and technologies. In 2015, Dr. Yu returned to ITRI and is currently with the Electronics and Optoelectronics Research Laboratories. His current research focuses on advanced packaging processes, where he continues to drive innovation and contribute to the semiconductor industry.

Abstract:
With the rapid development of AI technology, AI chips have become a cornerstone of high-end technological applications. A wide range of related products are actively exploring ways to integrate AI capabilities. A hallmark of innovative products and startups is their demand for diverse, small-batch manufacturing. To support the semiconductor industry in tapping into this highly dynamic and innovative market, it is essential to develop new small-batch production models. Our goal is to provide a shuttle service through an innovative platform that significantly reduces the cost and time required to develop new products via shared services. This service model enables startups and emerging products to experiment and iterate at lower costs and higher speeds, helping them reach the market faster and stand out in a competitive environment.
In this article, we present a shuttle service that effectively integrates various applications and structures through wafer layout design, enabling RDL (Redistribution Layer) process fabrication using a mask-sharing approach, as shown in Figure 1. Different applications may have significantly different copper densities. To address this, we further optimized the layout design and adjusted the process conditions, making it feasible to integrate applications with varying copper densities while maintaining excellent process uniformity. We fabricated a structure consisting of six copper metal layers and five corresponding passivation layers using polyimide (PI). Among these, four intermediate metal layers are used for RDL wiring (RDL = 4). From a process perspective, we employed a CTE (Coefficient of Thermal Expansion) compensation mechanism to reduce warpage and integrated low-stress, low-warping process technologies to complete the RDL fabrication. Further warpage reduction was achieved by thinning the PI layers and optimizing layout uniformity. Additionally, a comb structure test pattern was implemented in each metal layer to monitor leakage current, achieving picoampere (pA)-level sensitivity. After the RDL process, electrical testing of all circuits was conducted, resulting in a yield of over 90%. Furthermore, we demonstrate the capability to fabricate fine-pitch multilayer RDL stacks, featuring 2 μm/2 μm line/space and 8 μm via openings with fully copper-filled structures.

 

Bio:
Takanori Fukushima is a doctoral student at the Department of Science and Technology at Gunma University, Japan (2024⁓). His current research focuses on the influence of organic compounds on the sintering phenomenon of silver micro-fillers in resin-bonded conductive adhesives. In 2024, he received the JIEP Poster Award at the International Conference on Electronics Packaging (ICEP).

Abstract:
Sintering-type bonding materials have required improved connection reliability, such as mitigating thermal stress generated in the bonding area due to temperature change as the device operating temperature increases to realize higher device performance. We have been conducting fundamental research on sintering-type bonding, focusing on “low-temperature sintering of metal micro-fillers in resin-bonded conductive adhesives,” which can be used in large-area bonding applications such as module attachment.
In this study, we conducted fundamental research on applying the flexible epoxy resin as a conductive adhesive binder, expecting to enhance the stress-easing properties of the cured adhesive layer. We investigated the effects of application of the main component of flexible epoxy resin, the addition of reactive diluents, and the types of diluents on the low-temperature sintering behavior of silver micro-flakes and adhesive bonding properties.
The binder for the ECAs was prepared by using one of two types of two functional glycidyl ether epoxy resins, bisphenol A diglycidyl ether (BPA) and flexible-epoxy-resin as the primary component, with imidazole curing catalyst as hardener. Furthermore, various reactive diluents, including phenyl glycidyl ether (PGE), were added to the adhesive in specified amounts.
It has been found that applying flexible epoxy reduces electrical resistivity. In the flexible-epoxy resin based sample with 40 wt% PGE, the electrical resistivity of 10-6 ·cm, which was obtained by curing at 250 °C or higher in the BPA-resin based sample, could be obtained after curing at 190 °C.
Next, evolutions in the condition of cross-sectional microstructure cured at 190°C and 250 °C were evaluated. For both primary component samples, sintering between micro-flakes in the adhesive progressed depending on the curing temperature. Comparison of the applied primary components showed that sintering progressed more at both curing temperatures in the flexible epoxy resin-based samples than in the BPA resin samples. The results indicated that the application of flexible epoxy resin contributes to accelerated sintering.
The species of reactive diluent is also expected to influence resulting properties. Comparing the electrical resistivity of samples containing various reactive diluents with various structures, it was found that the effects of the added diluents varied. In samples containing the reactive diluent, which has a benzene ring and a carboxylic acid ester (EPGD) , it was found that electrical resistivity decreased more than in samples containing PGE.
Next, the electrical connection properties of the adhesion interface with the Cu electrode were evaluated by measuring the interfacial electrical resistivity. Using the flexible epoxy resin as the primary component was also found to improve the conductivity of the adhesion interface.
Furthermore, the viscoelastic properties of the freestanding samples of the adhesives to which each of the two main components was added were measured by dynamic mechanical analysis. Flexible epoxy as the primary component was more flexible.
It showed that the flexible epoxy resin binder composition designed to utilize chemical interactions between Ag fillers can be used to obtain a conductive adhesive that can be cured at low temperatures, is flexible, and has excellent bonding properties.

 

Bio:

Majored in mechanical engineering at Oklahoma State University. After graduation, joined Yaskawa Electric Corporation, where he was engaged in both technology development and business planning. In 2024, he joined Elephantech Inc. and was appointed Manager of the Business Development Division. He is currently focused on promoting next-generation PCB manufacturing technology, based on additive processes using inkjet technology and nanomaterials, with a particular emphasis on its potential for the semiconductor industry. His areas of expertise are the commercialization of new technologies and their application development within the semiconductor industry.

Abstract:

The electronics industry faces growing pressure to reduce its environmental footprint and improve resource efficiency. Conventional subtractive manufacturing processes, which are dominant in both PCB and semiconductor fabrication, lead to significant material waste and high energy consumption.

We introduce a revolutionary additive manufacturing process developed by Elephantech, which utilizes AI-powered inkjet technology and proprietary nanomaterials. Our technology has been successfully applied to PCB production, where it has demonstrated a remarkable reduction in material waste by over 95% and a decrease in CO2 emissions by more than 75% compared to traditional methods.

Based on these advancements, we believe our technology holds significant potential for addressing specific challenges and enabling new functionalities in the semiconductor industry.

We will share our experience and key insights gained from low-carbon PCB manufacturing. Our presentation will highlight how an additive, resource-efficient approach, already successful in the PCB field, could contribute to a more sustainable and innovative future for semiconductor manufacturing

 

Bio:
I pursue my bachelor's degree in Mechanical Engineering, University Malaya. I worked for 2 years in TF-AMD, a semiconductor packaging company in Penang, Malaysia as a process engineer in the underfill process. Now I am pursuing my master's degree in NCKU to specialize in the semiconductor industry.

Abstract:
The demand for high-power semiconductor devices continues to grow, driving the scaling of node sizes to accommodate a greater number of transistors within a single package. Cu is a commonly used material in semiconductor devices due to its excellent electrical conductivity and is employed in structures such as interconnects and Cu pillar bumps for solder joints. These structures experience mechanical loading during service. In Cu pillar structures, thermomechanical fatigue caused by the coefficient of thermal expansion (CTE) mismatch is a known reliability issue. However, the additional influence of electric current on Cu’s mechanical behaviour at the microscale remains insufficiently understood.

To address this, we employed micropillar compression, a technique capable of capturing uniaxial stress–strain behavior with crystallographic specificity at the microscale. Unlike nanoindentation, which provides modulus and hardness values, micropillar compression enables direct insight into elastic–plastic transition, strain bursts, and deformation mechanisms relevant to microbump reliability in 3D integrated circuits. Cu micropillars with diameter of 6µm and height of 15 µm were fabricated on a <111>-oriented single-crystal Cu substrate using focused ion beam (FIB) milling. Compression tests were conducted using a flat punch nanoindenter integrated with an electrical characterization module (ECM) inside a scanning electron microscope (SEM), allowing simultaneous application of mechanical stress and electric current. During compression, a displacement controlled programmed is used, with a strain rate of 3 × 10-3. The electric current density applied ranges from 0 to 4 × 103 A/cm2 .

The results show that the flow stress increases with current density, indicating electric current-induced strengthening in Cu. Post-compressed characterization using transmission electron microscopy (TEM) and transmission Kikuchi diffraction (TKD) revealed microstructural features linked to dislocation activity, offering insight into the underlying electromechanical deformation mechanisms.

 

Bio:
Currently a Ph.D. student in the Semiconductor and Green Technology Program at National Chung Hsing University, with research focusing on intermetallic compounds, nanoindentation, and nanoparticles.

Abstract:
In semiconductor packaging, the mechanical and structural characterization of interfacial intermetallic compounds (IMCs) is essential for assessing joint reliability. With ongoing technology scaling and structural miniaturization, nanoindentation has emerged as an effective technique for evaluating the mechanical properties of materials at the nanoscale. In this study, nanoindentation was employed to characterize the mechanical behavior of commonly observed IMCs in solder joints, and the correlation between the nanomechanical responses and solder joint performance was systematically investigated. The plastic deformability of IMCs is described by the ratio of elastic modulus to hardness (E/H), where a higher E/H indicates easier plastic deformation. Results show that E/H exhibits an inverse relationship with the work-hardening exponent (n) but positive correlation with strain rate sensitivity (m). Creep deformation plays a critical role under high-temperature operating conditions. Creep test results reveal that E/H is inversely related to the creep stress exponent (CSE), suggesting that IMCs with lower E/H exhibit better creep resistance. Furthermore, in high-speed ball shear testing the impact energy of solder joints was found to scale proportionally with the E/H value of the interfacial IMC. These findings demonstrate that mechanical behavior of IMCs dominates joint performance under various strain rate conditions. By controlling E/H values of IMCs, joint reliability can be further optimized from the aspect of material design.

 

Bio:
Master’s student in Professor Jenn-Ming Song’s Laboratory, Department of Materials Science and Engineering, National Chung Hsing University, focusing on direct bonding research for advanced semiconductor packaging.

Abstract:
By minimizing parasitic interconnect resistance and improving signal transmission efficiency between stacked dies, Cu-to-Cu bonding addresses key challenges in next-generation semiconductor systems, such as power delivery, data bandwidth, and form factor reduction. Its compatibility with low-profile, high-density integration makes it particularly suitable for AI accelerators and mobile devices. However, a key barrier to achieving high-reliability Cu-Cu bonding lies in the native oxide layer that inevitably forms on copper surfaces upon air exposure. Even at nanometer-scale thickness, this oxide can significantly hinder atomic diffusion across the bonding interface. This increases the required thermal budget and bonding pressure, and introduces risks such as void formation, warpage, or interfacial delamination—especially in thermally sensitive packaging environments. To address this challenge, we investigated the oxidation behavior of copper thin films under low-temperature thermal conditions (120°C). Constant-current coulometric reduction was employed to detect and quantify surface oxide layers. These results were cross-validated using X-ray photoelectron spectroscopy (XPS), Kelvin probe force microscopy (KPFM), water contact angle analysis, and atomic force microscopy (AFM). The integrated dataset enabled us to construct a detailed profile of oxide evolution and growth mechanisms under thermal oxidation. Shear tests of Cu t0 Cu direct bonded joints reveal that even relatively thin oxide layers (<10 nm) could cause a steep drop in bonding strength—from above 30 MPa to below 10 MPa—highlighting the extreme sensitivity of Cu-Cu interfaces to early-stage oxidation. Interestingly, the formation of a small amount of hydrophilic CuO was found to temporarily suppress strength degradation by improving wettability and interfacial contact.
Keywords: Cu-to-Cu bonding, Surface oxide, Thermal oxidation, Coulometric reduction, Bonding strength

 

Bio:
Academy of Circular Economy, National Chung Hsing University, Taichung 402, Taiwan

Abstract:
In 3D integrated circuits (3D ICs), vertical chip stacking relies on through-silicon vias (TSVs) filled with electroplated copper to achieve interconnection. As the bonding interface is composed of Cu–Cu, the bonding quality plays a decisive role in determining the overall reliability of the package. However, native oxide layers readily form on copper surfaces, which can hinder atomic diffusion and bonding integrity, making precise characterization of these oxides essential for process optimization. This study proposes a rapid and quantitative electrochemical method for analyzing both the thickness and phase composition of copper oxide layers. By applying constant current cathodic reduction and utilizing Faraday’s law, the oxide layer thickness can be accurately calculated. Moreover, by defining the redox potential ranges of CuO and Cu₂O, the thickness of each oxide phase can be separately estimated, thus improving the precision and efficiency of the evaluation. To validate the results, X-ray photoelectron spectroscopy (XPS) was systematically employed. The proportions of CuO and Cu₂O were determined by comparing the Cu 2p₃/₂ and Cu LMM signals, and the oxide thickness was estimated using the Beer–Lambert law. Depth profiling with XPS was also performed to observe variations in elemental signals along the thickness direction, confirming phase distribution across the oxide stack. Atomic force microscopy (AFM) and α-step profilometry were used to assess the changes in surface morphology and roughness before and after oxidation and electrochemical reduction, providing surface feature information related to the formation and removal processes of the oxide layers. This integrated analysis framework enables multidimensional and complementary validation of copper surface oxidation and reduction behaviors, contributing to the reliability of future microelectronic interconnect technologies.
Keywords: Cu–Cu bonding, copper oxide, oxide thickness, electrochemical reduction, XPS analysis

 

Bio:
SPIL substrate eng DEPT. technical manager

Abstract:
In recent years, with the popularization of cloud services, the application of generative AI and data analysis has become increasingly widespread. The trend of mobile offices or micro-desktop workstations has increased. The market demand of high-performance SoC is not limited to desktop computers. It Has gradually expanded to portable personal computers, such as a tablet or laptop. How to pursue high performance while consideration of thin and light design requirements is not just a subject in IC design, it also broke the previous technological development trend for IC carrier product platforms. While Flip-chip ball grid array (FCBGA) product design pursues large size and multiple layers, it also needs to consider how to reduce the overall thickness.
IC substrate is comprised of multi materials, of which the core layer accounts for 50~80% of the overall thickness (depending on the number of layers designed). If the core layer can be reduced or even removed it to create a coreless structure. Not only can the thickness of the base be significantly reduced, but also increase design flexibility, to remove the useless layers such as the bottom layer on a cored substrate, and achieve better electrical characteristics, due to reduce the loop inductance.
Although the thin core and coreless structures have been widely used in existing Flip-chip chip scale package (FCCSP) product technology; but FCCSP product designs are mostly small-sized and low-layer designs, and the dielectric material used is Prepreg which containing fiberglass cloth inside and able to provide rigidity. In contrast, FCBGA product designs are mostly large-sized and high layer count, thus the dielectric material used chose build-up film, hereinafter referred to as ABF, which does not contain fiberglass cloth. Whether it is reducing the thickness of the core or removing the core to create a coreless structure, the warpage performance of the FCBGA substrate is a big challenge.
Based on the above considerations, we expect to find a feasible substrate structure and suitable dielectric materials through this study. Considering the compatibility with FCBGA production line equipment, we selected two structures, 5/2/5L 0.15mm core and 12L coreless, for ultra-thin FCBGA structure verification. In addition, in the selection of dielectric materials, we also considered another ABF materials which containing glass fiber, also known as ABF-GCP (Glass Cloth with Primer), to enhance the rigidity of the dielectric materials. Due to the glass fiber will increase dielectric layer thickness, we only replaced two layers of ABF with ABF-GCP to keep the thin design requirements as posable and compare the warpage performance between pure ABF and hybrid dielectric (ABF/ABF-GCP).

 

Bio:
My name is Hao-Wei Kuo, a second-year master's student in the Department of Mechanical Engineering at National Cheng Kung University. My research focuses on low-temperature solders, particularly Sn-In alloys, which show great potential for use on flexible substrates. With a strong interest in this field, I am eager to further explore the development of these materials, which has motivated me to pursue a Ph.D. I sincerely hope to continue this journey successfully.

Abstract:
With the rapid development of flexible electronics, the demand for low-temperature solders has grown, especially for polymer substrates that are easily damaged above 150 °C. Traditional Sn–Bi alloys, despite their low melting point, suffer from brittleness, limiting their application. In contrast, Sn–In alloys offer better ductility but lack sufficient mechanical strength. For instance, the Vickers hardness of eutectic Sn–52wt.%In alloys is less than 10 HV, indicating their softness. To improve performance, previous studies introduced third elements such as Cu, Ag, and Zn. While some properties improvement was observed, the effects of multiple additions remain unclear due to system complexity. Therefore, this study adopts a machine learning model to efficiently explore and optimize multicomponent Sn–In–X alloys. Recently, machine learning methods have been proposed as a promising approach for new material design. A Vickers hardness database was established for alloys containing Cu, Ag, Zn, Bi, Sb, Al, and Ni. A Gaussian Kernel Ridge Regression (GKRR) model was trained using this dataset, and a genetic algorithm (GA) was integrated for inverse design. This framework enables efficient screening of alloy compositions targeting desired hardness levels. Candidate alloys were synthesized and experimentally confirmed, demonstrating the model’s predictive capability. The designed SIX5 (Sn–In–X) alloy exhibited approximately three times the hardness and more than double the tensile strength of conventional Sn–52wt.%In, confirming its significantly enhanced mechanical performance. This research demonstrates an effective framework combining machine learning and thermodynamic modeling to accelerate the development of advanced low-temperature solders for packaging and flexible electronics.
Keywords: low-temperature solder, Sn-In alloys, machine learning, hardness, tensile properties.

 

Bio:
I am a graduate student in the Department of Electronic Engineering at National Pingtung University of Science and Technology, Taiwan. My research focuses on low-temperature co-fired ceramics (LTCC) for high-frequency applications. I am dedicated to advancing the development of LTCC technologies in the field of electronic integration.

Abstract:
With the rapid development of 5G wireless communication and Internet of Things (IoT) technologies, there is a growing demand for communication modules featuring high frequency, low latency, miniaturization, and massive connectivity. Low-temperature co-fired ceramics (LTCC) have emerged as key materials in 5G and millimeter-wave systems due to their excellent high-frequency characteristics, high integration capability, and co-firing compatibility with internal electrodes. Compared to commercial substrates such as Rogers 4003C (organic composite) and DuPont LTCC (which require high sintering temperatures and costly gold electrodes), the oxide-based LTCC developed in this study demonstrates both low-temperature sintering and stable microwave dielectric properties, making it suitable for high-frequency PCB and multilayer module applications with improved cost and environmental benefits.
In the first stage, ZnMoO4-based ceramics were synthesized via solid-state reaction, and partial substitution of Zn2+ with Mg2+ formed the Zn1-xMgxMoO4 system. Dielectric properties and sintering behavior were systematically evaluated. The x = 0.06 sample sintered at 770 °C for 2 hours showed εᵣ = 8.65, Qf = 59,000 GHz, and τf = −62.18 ppm/°C, indicating high-Q performance with low-temperature sinterability. To further improve thermal stability and achieve temperature compensation, TiO2 known for its high permittivity and positive τf was incorporated to form the (1−y) Zn0.94Mg0.06MoO4–yTiO2 composite system. At y = 0.13 and sintered at 780 °C, the optimized composition exhibited εᵣ = 9.8, Qf = 42,800 GHz, and τf = −3.41 ppm/°C, achieving both near-zero temperature coefficient and low dielectric loss.
For application verification, a filter was designed based on a 2020 IEEE reference circuit featuring one low-pass and two band-pass responses. The second band-pass center frequency was modified to 3.5 GHz (Sub-6 band), and a band-pass filter was fabricated using the developed LTCC substrate. Its performance was benchmarked against three commercial substrates: Rogers 4003C, FR4, and Al2O3. Results demonstrated that the (1−y)Zn0.94Mg0.06MoO4–yTiO2 substrate enables circuit miniaturization, reduced insertion loss, and improved frequency stability with near-zero τf behavior.
Moreover, this material can be co-fired with low-cost Ag electrodes at low temperatures without the need for expensive gold electrodes or nitrogen atmosphere, significantly reducing process costs and carbon emissions. It shows excellent compatibility with green manufacturing and is well-suited for large-scale PCB production. Finally, a Sub-6 GHz band-pass filter was successfully fabricated using the developed LTCC material, and the experimental results matched well with simulations, confirming its effectiveness in high-frequency applications and demonstrating its potential as a next-generation LTCC substrate for high-frequency modules.
Keywords: Low Temperature Co-Fired Ceramics; Dielectric Ceramics; 5G Filter; Low-Carbon Processing; Cofiring Compatibility; High-Frequency PCB Applications

 

Bio:
I'm Po-hsiang Juan from Tainan, Taiwan. I'm the master student from NCKU MSE. Our lab, NEXT-G, focus on electronic packaging, battery and so on. And my research is about thermal interface materials.

Abstract:
As electronic products continue to evolve toward lighter and more compact designs, chip dimensions have also been continuously shrinking. This results in a significant increase in the number of transistors per unit area. This trend aligns with Moore’s Law, which states that the number of transistors on a chip doubles approximately every two years. To meet the demands of such high-density components, traditional two-dimensional (2D) packaging based primarily on wire bonding has gradually become inadequate in terms of performance and spatial requirements. As a result, packaging technology has been steadily advancing toward three-dimensional integrated circuits (3D ICs). At the same time, as chip functionalities grow more powerful, power consumption has also continued to increase. The power consumption of Central Processing Unit (CPU) has risen with each new generation. This means higher power density in the same or even smaller volume, which not only leads to increased temperatures inside the package but also causes chips to operate under high thermal stress, potentially resulting in reduced performance or even lower reliability.
Efficient dissipation of the heat generated within a chip has become a critical challenge in the field of electronic packaging. Among various thermal management strategies, thermal interface materials (TIMs) play an essential role in the thermal conduction path. Their performance directly influences the overall thermal management efficiency and long-term reliability of electronic systems. When two solid surfaces come into contact, the actual physical contact area is limited due to microscopic surface roughness even if the surfaces appear smooth on a macroscopic scale. The gaps formed by this roughness are typically filled with air, which has extremely low thermal conductivity. This creates a significant thermal barrier at the interface, reducing heat transfer efficiency. TIMs are designed to fill these micro-gaps, replacing the air and increasing the real contact area. This facilitates smoother heat flow from the heat source (e.g., the chip) to the heat-dissipating component (e.g., the lid or heatsink), effectively reducing interfacial thermal resistance and improving overall heat dissipation performance.
In this study, we use Indium as TIM. First, a die/In/die sandwich structure was fabricated using thermal compression bonding (TCB) method. Use SAT to scan the interface to make sure indium and substrate are well-bonded. Subsequently, cross-sectional analysis will be performed to examine the interface. Scanning Electron Microscope (SEM), Energy-Dispersive X-ray Spectroscopy (EDS), and Electron Probe Microanalyzer (EPMA) were used to analyze the microstructure and identify the phases. The thermal resistance was measured by ASTM D5470 method. We investigate the interfacial reaction of die/In/die sandwich structure and examine how different bonding parameters affect the interfacial reactions. By comparing the relationship between interfacial reaction and thermal resistance, we can determine which bonding condition yields the best overall performance.

 

Bio:
Huan-Ping Chao is a professor in Department of Environmental Engineering, Chung Yuan Christian University, in Taiwan. He received his Ph.D. degree from Graduate Institute of Environmental Engineering, National Taiwan University, in 2003. His research interests include adsorption, volatilization, environmental contaminant analysis, and remediation of soil and groundwater, and solid waste management. At present, his research focuses on (1) developing new adsorbents for removal of various contaminants, (2) establishing a theory of volatilization and discussing the volatilization mechanisms of organic compounds from water, (3) developing new techniques for the remediation of soil and groundwater. Up to now Prof. Chao has published more than 60 papers in reputable-journal and two book chapters. Also, he is a regular reviewer for many prestigious environment-focused journals in different publishers.

Abstract:
The contaminants eliminated in wastewater could reduce the impacts of contaminants on the environment. If these contaminants can be recycled, the enterprise can provide sustainable development for the environment. The wastewater from printed circuit board industries often contains contaminants such as copper ions and color. Thus, a new adsorbent removing both copper ions and dyes was developed in this study. The calcium aluminum layered double hydroxides (Ca-Al LDHs) was applied in the adsorption of copper ions and organic dyes. Ca-Al LDHs has attracted widespread attention in recent years due to its unique layered structure, high adsorption amounts of contaminants, and relatively low synthesis cost. In addition, the Ca-Al LDHs can adsorb cationic and anionic contaminants through different adsorption mechanisms to simplify wastewater treatment process.
In this study, Ca-Al LDHs was synthesized using coprecipitation process. Tow kind ratios of calcium to aluminum (3:1 and 4:1) were selected to produce the Ca-Al LDHs. The Ca-Al LDHs before and after adsorption were characterized by were characterized by Scanning electron microscopy (SEM), BET surface area, Fourier transform infrared spectroscopy (FTIR), XRD, and X-ray photoelectron spectroscopy (XPS). Then, the Ca-Al LDHs were used to adsorb copper ion, cationic dyes (methylene blue and methyl green) and anionic dye (methyl orange) in the various pH (3, 4, 5, 7 and 9) solutions. The adsorption amounts of test contaminants on the Ca-Al LDHs were estimated by Langmuir equation. In addition, in-situ synthesis processes for the LDHs were also applied to remove the test contaminants. 1000 mg/L of contaminants were used to test the removal rates in the process for the LDHs synthesis. Three concentrations of chemicals for the in-situ synthesis were added the solutions to measure the removal rates in the given periods.
The results showed the two Ca- Al LDHs before adsorption have the similar SEM images, XRD spectra and FTIR spectra. The result demonstrated the Ca- Al LDHs have been synthesized successfully. The difference in XPS and BET surface area represented the diversity of adsorption efficiencies on the selected contaminants.
The equilibrium adsorption experiments presented the data can fit Langmuir model well. Moreover, the maximum adsorption capacities of selected contaminants on the LDHs can be estimated by the Langmuir equation. The adsorption amounts of methyl orange and copper ion increase with the decreasing pH values. The adsorption amounts of methyl blue and methyl green are less-important with the pH values of solutions. The maximum adsorption capacities of copper ions, methylene blue, methyl green and methyl orange in various pH solutions are 480, 1293, 1408 and 2451 mg/g. The primary adsorption mechanism of copper ion is surface precipitation. The primary adsorption mechanisms of methylene blue and methyl green are hydrogen bonding, van der Waals force and surface precipitation. The primary adsorption mechanism of methyl orange is electrostatic force or ion exchange. The result in the in-situ synthesis demonstrated the Ca-Al LDHs can be used in the realistic wastewater. The removal rates of test contaminants can reach 80% within 4hr.

 

Bio:
Bryant Tsai is a Senior System Power Design Engineer at Intel Corporation, based in Taiwan. His work focuses on supporting customers in designing stable, reliable, and optimized power delivery systems for Intel’s data center platforms. With a strong background in power integrity, system-level design, and cross-functional collaboration, he plays a key role in enabling scalable and efficient power architectures for next generation server solutions. Bryant has extensive experience in system validation, power delivery network (PDN) optimization, and customer enablement across global markets. He is passionate about bridging the gap between silicon design and real-world deployment, ensuring robust performance under diverse workloads and operating conditions.

Abstract:
As Artificial Intelligence (AI) workloads drive unprecedented power demands in modern data centers, efficient power delivery has become a critical design priority. Traditional approaches such as increasing PCB copper thickness or adding layers are reaching physical and economic limits. This paper introduces an advanced copper foil (ADCF) solution that significantly reduces DC resistance compared to conventional Reverse Treated Foil (RTF) foils, thereby enhancing power efficiency. Through theoretical modeling, test vehicle validation, and system-level simulations, the study demonstrates up to 7.4% power loss reduction using ADCF. This translates into substantial electricity cost savings and carbon emission reductions in large-scale AI server deployments. By improving conductivity and minimizing energy loss, this innovation supports the broader goal of sustainable power efficiency in next generation data center infrastructure.

 

Bio:
24 years of work experience at USI QMD/QA Engineer → QA Section Manager (2000~2006)-> Staff Administrator(2009)→Prof. Manager (2015)->Associate Director (2019)→ Director (2021~) Main Job function: 1. Own Global IE&PC for WW Capacity Plan and Drive WW Mfg. Utilization and Efficiency, and Cross-Site Capacity Allocation 2. Survey New sites, New Building Facility Layout. Join M&A, Due Diligence, Synergy post M&A 3. Review Capex, Save Capex by Cross-Site Alloca-tion; Cross-Site Product/Equipment Transfer

Abstract:
In previous studies, SFIS and SAP data have been used to present SMT OEE, achieving global standardization of factory data standards. Excel data is pushed monthly through automated reporting systems, but only the previous month's data can be sent at a fixed time each month, which is not conducive to on-site management and timely improvement. This upgrade utilizes Azure Analysis Services (AAS) for big data modeling and preprocessing and uses Power BI to connect AAS models to generate interactive OEE dashboards. Users can set their own conditions to view reports at any time, as well as analyze the root cause of OEE anomalies independently. They can quickly seek improvement and provide accurate historical data for quotation.

 

Bio:
Education： 1995.9-2000.10 Ph.D in Electronic Engineering, National Chiao Tung University 1992.9-1994.6 Master of Applied Chemistry, National Chiao Tung University Experience： A. 2017/8~Now National Ying Ming Chiao Tung University Post Doc. Research B. 2010/11~2016/02 UMC New Business Company, Manager I. Compound Semiconductor manufacture Foundry (III-V MMIC RF device manufacture) II. 3D IC package C. 2000/11~2006/10 & 2007/03~2010/08 (UMC), Technical Manager

Abstract:
In this study, the feasibility and the QRcode ecosystem are demonstrated with semiconductor processing and advanced packaging supply-chains. The QRcode Mcells are auto-generated via decent CAD flow automation, as this illustration. We can create different QRcode per wafer, per photo-shot and split-patterns, especially for good potential in maskless, sub-millimeter, sip-process usage (in wafer or panel form), it is “traceability” in SiP supply-chain management. We included design splits: same QRcode/pitch with 3 square sizes for 2 µm x 2 µm ; 3 µm x 3 µm and 4 µm x 4 µm, to emulate various process variations. The design for the QR-code combined with two layer. The process DOEs include single exposure (1P, separate layers) and double exposure (2P, single layer), and verified by both SEM and OM (optical microscope), on different film stack/substrates: One was the oxide-on-PR-on-silicon; Others were Ta-on-glass substrates.
The core idea is to use a single controller on the photomask machine to directly generate the QR code onto a programmable mask-reticle, enabling an in-process, closed-loop automation flow. While we can't fully replicate this process in a small SBIR project without the equipment vendor's endorsement, this proof-of-concept (POC) project is an excellent starting point for promoting "SiP traceability" in future SiP and related industry practices. Our CAD flow can auto-generate the QR code Mcell variance, but it can't link with the tool itself.
The QRcode read-out is “JBeGeLlqZTF” correctly, via some software improvements (e.g. machine learning for noise refinement, fuzzy matching, transparent algorithm, etc)

 

Bio:
I am currently a master’s student in the Department of Materials Science and Engineering at National Cheng Kung University. My research focuses on electromigration phenomena and microstructural evolution in Au thin films used in electronic devices. My work involves investigating lattice instability, grain growth, and dislocation density changes, aiming to develop methods for early detection of electromigration-induced damage. In this conference, I will present my work titled “Early Detection of Electromigration-Related Lattice Instability in Au Strip.”

Abstract:
Understanding current-induced degradation in metallic interconnects is essential for improving the reliability of advanced PCBs. In this work, we investigated irreversible lattice deformation in FCC Au strips under electric current stress (ECS) using in-situ synchrotron X-ray diffraction (SR-XRD). A clear threshold was observed at ~1.04 × 10^6 A/cm^2, beyond which the (111) reflection showed irreversible d-spacing expansion, absent under thermal-only conditions. This confirms a non-thermal origin, attributed to electron wind force. The expansion was crystallographically anisotropic and unrecoverable after post-heating, indicating field-induced lattice distortion rather than elastic strain. No phase transformation or hillocking was observed, highlighting Au’s distinct response compared to Cu and Al. This study establishes SR-XRD as a powerful diagnostic tool to detect early-stage lattice instability prior to failure.

 

Bio:
Jeff Chen, graduated from Mechanical Engineering Dep., NYUST in 2002 and started to work in USI as a manufacturing engineer from 2004. He has the experience on board and system assembly. Currently, he focuses on SiP new process and technology in COD

Abstract:
Jumper is a kind of compact metal or plastic cap connector, which is mainly used for short circuit or jumper operation on the circuit board of electronic devices to achieve specific circuit configuration or function selection. The automatic jumper machine arranges the irregular incoming materials orderly through the vibrating plate.The pressure self feedback sensing technology is applied to accurately control the distance and pressure with the electric cylinder, so as to realize the full-automatic jumper insertion instead of manual operation, and improve the production efficiency and quality. Currently, it has been widely used in mass production.

 

Bio:
I'm master student from NCKU

Abstract:
Silver is excellent electrical conductivity; this property makes it to be an ideal material for various electronic and optoelectronic applications. However, its high-cost limits large-scale usage, especially in applications requiring extensive coverage. To solve this challenge, fabricating silver in the form of thin films offers a cost-effective strategy that retains its superior conductivity while significantly reducing material consumption. In this study, a galvanic reaction-based method is employed to efficiently deposit silver thin films, providing a simple, low-cost approach for scalable silver utilization. Galvanic reaction is a type of electroless redox reaction that occurs at the interface between a solid substrate and a solution containing metal ions. This process is driven by the difference in standard reduction potentials, where the substrate undergoes spontaneous oxidation while metal ions in the solution are reduced and deposited onto the surface. To further control the morphology of the deposited layer, polyvinylpyrrolidone (PVP) is introduced as a structure-directing additive. The addition of PVP significantly influences the nucleation and growth behavior of the metal crystals, effectively suppressing dendritic structures and promoting the formation of dense, uniform films composed of near-nanoplate morphologies. Given that the Ag⁺/Ag redox pair has a higher standard electrode potential (+ 0.799 V) than the Cu²⁺/Cu pair (+ 0.337 V), galvanic replacement readily occurs when copper substrate is immersed in AgNO3 solution. A series of experiments were conducted using Ag⁺ solutions of varying concentrations, and the results are presented in Fig. 1. In the absence of polyvinylpyrrolidone (PVP), the deposited silver exhibits poor surface coverage and predominantly cluster-like morphologies rather than plate-like structures. In contrast, when PVP is introduced into the galvanic reaction system, the crystallization of silver dendrites is effectively suppressed. This morphological control is attributed to the steric hindrance imparted by PVP and the reduced mobility of Ag⁺ ions in the more viscous medium, which together promote the formation of discrete Ag nanoplates and polyhedral particles. As the Ag⁺ concentration increases from 1 mM to 50 mM, a notable improvement in surface coverage by silver is observed. However, extended reaction times at higher concentrations lead to the co-growth of Ag dendrites alongside nanoplates, with dendrites often emerging from the preformed Ag plates. This indicates that at 50 mM, the amount of PVP present is insufficient to fully suppress dendritic growth. Increasing the PVP concentration in such high-Ag⁺ systems may further inhibit the formation of undesired dendritic structures. The experimental parameters—including reaction time, silver nitrite concentration, and the content of PVP—play critical roles in determining the thermodynamic and kinetic pathways of the reaction, as well as the resulting morphology and microstructure of the deposited silver.

 

Bio:
My name is An-Yu Huang. I am a graduate student in the Department of Materials Science and Engineering at National Cheng Kung University (NCKU), Taiwan. My research focuses on electronic packaging technologies, particularly the electroplating of liquid metals and low-temperature bonding techniques. I am currently leading a collaborative industry-academic project between NCKU and ASE Group, aiming to advance next-generation 3D IC packaging solutions.

Abstract:
During the high-temperature bonding process in heterogeneous integration, undesirable warpage often occurs due to the mismatch in the coefficient of thermal expansion (CTE) between different materials. Therefore, reducing the bonding temperature is an attractive strategy to mitigate thermal stress and improve structural reliability. Transient Liquid Phase Bonding (TLPB) is a key technology that utilizes low-melting-point metals (such as indium (In) and gallium (Ga)) as bonding fillers to interconnect high-melting-point materials (such as copper (Cu) and nickel (Ni)). In the TLP bonding process, the low-melting-point interlayer melts and reacts with the substrates, forming high-melting-point intermetallic compounds (IMCs). These IMCs offer excellent thermal and mechanical stability, ensuring strong metallurgical bonding. TLPB combines the low-temperature wetting characteristics of liquid metals with the long-term reliability of solid-state joints, effectively addressing the CTE mismatch issue in 3D IC packaging. It also overcomes critical challenges under extreme operating conditions, such as high current density, thermal cycling, and power dissipation, making it a promising solution for next-generation heterogeneous integration.
Electroplating is a well-established thin film deposition method, and gallium (Ga) is a highly promising material for TLPB. However, Ga electroplating has not been widely adopted in the industry due to its inherently low current efficiency. This inefficiency is mainly attributed to the lower reduction potential of Ga³⁺ compared to H⁺, which leads to competitive hydrogen evolution reactions (HER). These reactions significantly suppress the reduction of gallium ions and result in a low gallium metal deposition rate. In this study, we demonstrate how to suppress HER by adjusting the parameters of the electroplating solution. By modifying the ratio of Ga to complexing agents and adding pH buffer additives, we achieved a nearly 40% improvement in current efficiency. The morphology and composition of the Ga layer were characterized using SEM, EDS, and EPMA; functional groups were analyzed by FTIR; and the mechanical properties of the Ga layer were evaluated using nanoindentation. Additionally, we investigated the violent bubble formation observed during the electroplating process, aiming to fully suppress the hydrogen evolution reaction (HER). As a result, this study achieved a current efficiency of 82% for Ga electroplating, successfully suppressing the bubble formation during electrodeposition and overcoming the long-standing challenge of low current efficiency in Ga electroplating. We propose a high-current-efficiency Ga electroplating method and confirm that Ga electroplating is a promising TLPB technology capable of effectively addressing the CTE mismatch issue in advanced electronic packaging.

 

Bio:
I work at the Industrial Technology Research Institute in Hsinchu, and my department is the High Frequency - Wide Band Substrate Materials Laboratory. I have a master's degree and graduated from National Chung Cheng University.

Abstract:
With the accelerating development of application technologies such as artificial intelligence servers (AI Server), high-performance computing (HPC), network communication equipment, and the Internet of Things (IoT), the IC substrate materials market is poised for rapid expansion. In response to the growing demand for next-generation computational power, advanced substrates must offer high-speed data transmission, low signal latency, and low power consumption to meet future performance and system requirements. To meet the demands of high-performance computing, advanced wafer fabrication processes are integrating chips of varying nodes and functionalities into a single device, offering IC designers greater flexibility in system architecture. In addition to continuous node scaling down, advanced packaging technologies such as 2.5D, 3D integration, and chiplets are being employed to heterogeneously integrate these smaller dies. This approach allows for more compact circuit layouts and increased interconnect layer counts to support higher I/O density requirements.
In the realm of high-frequency, high-speed signal transmission, performance degradation arises not only from dielectric losses but also from the pronounced skin effect in copper conductor layers. Moreover, as the number of stacked layers in substrate designs increases, the build-up dielectric materials also require high glass transition temperatures (Tg) and low coefficients of thermal expansion (CTE) to mitigate interlayer warpage, signal instability, and performance loss under high-frequency, high-speed operation. Thus, build-up materials for advanced applications must exhibit a low dielectric constant, low dissipation factor, and high thermal stability to ensure the signal integrity and reliability of the final IC substrate.
In this study, a novel build-up material was investigated using a hybrid resin system composed of a rigid thermosetting resin and a low-polarity resin. By systematically designing the resin components and fine-tuning the formulation, a series of film materials was obtained. These materials exhibit a low dielectric constant (Dk 2.98–3.08 @10 GHz), low dissipation factor (Df 0.0018–0.0029 @10 GHz), low coefficient of thermal expansion (CTE = 16–29 ppm/°C), and high glass transition temperature (Tg = 170–180°C). Furthermore, using a semi-additive process (SAP)—including electroless copper plating, photolithography, and electrolytic copper plating—the material was fabricated into a multilayer substrate. The insertion loss of the complete build-up substrate was then measured under various frequency conditions to evaluate the signal transmission performance of the multilayer configuration.

 

Bio:
Chiew Yee is working in Intel Platform System Engineering team as Systems and Hardware Enabling Engineer responsible for HSIO electrical and functional validation and customer issue debug

Abstract:
As the datacenter industry grows rapidly and high-speed signal data rate increases to support the demands from Artificial Intelligent (AI) server, the channel design of multiple connectors topologies of high-speed interconnect (HSIO) is utilizing the cable assemblies with riser or high-speed backplanes to provide the flexibility to connect and manage multiple PCIe switches end devices such as storage, network and graphic components. The optimization of cables used in the high-speed channel design in high dense AI server design is crucial to ensure the quality of the high-speed signals with low bit error rate (BER).

Flat cable consists strands of high-speed differential wires bundled in parallel ribbon to form a flat surface while the conventional round cable has strands of wires twisted around each other to create a round cylindrical shape. Two types of HSIO cables with round shape with length 360mm and 720mm and flat shape with length 380mm were used in a HSIO channel 3 connectors topology on a datacenter platform for Signal Integrity (SI), Electrical Validation (EV) and Functional Validation (FV) characterization.

The cable is a Y-type cable with one end consist of a Mini Cool Edge (MCIO) connector with x8 lane width connected to the main board (MB) and splitting into two ends of MCIO x4 lane width connected to the high-speed backplane (HSBP) with the PCIe Gen5 x4 Enterprise and Datacenter Standard Form Factor (EDSFF) Solid State Drive (SSD) connected for EV and FV testing. In the SI measurements, the EDSFF SSD and CPU are not included in the impedance and loss analysis with the assumption that delta of CPU and end device loss across various lanes are negligible.

In the EV characterization, the timing and voltage margin of the CPU Receiver (Rx) were collected using flat and round cables, whereby the voltage margin result shown on Figure2 that the round cable with longer length has better voltage margin than the flat cable. The performance throughput of the HSIO channel is measured using Flexible IO (FIO) Tester application. Per Table1, all types of cables are showing similar IOPS test result.

In the SI characterization, flat cable is showing higher insertion loss compared with the round cable with the similar length. Flat cable is showing lower via impedance and greater impedance mismatch with MB (~8ohm) while round cable has better impedance mismatch (~3ohm).

In summary, flat cables provide better flexibility of the cable management in a dense datacenter AI server fleet with the expenses of higher loss, greater impedance mismatch with MB and lower electrical margin. As the channel design are within the specification guideline and receiver is well equalized, the performance throughput of the flat and round cables is comparable.

 

Bio:
Currently a first-year graduate student in the Department of Electrical Engineering at National Formosa University, focusing on the fault diagnosis of Interior Permanent Magnet Synchronous Motors (IPMSM), with an emphasis on spectral analysis methods. The research aims to explore the relationship between electromagnetic signal characteristics and motor fault patterns, in order to improve diagnostic accuracy and system reliability. Current work involves frequency-domain feature extraction, anomaly detection techniques, and validation through hardware implementation. Future research will focus on integrating these diagnostic approaches into intelligent drive systems to enable real-time monitoring and fault prevention.

Abstract:
This study addresses the challenges of performance monitoring and fault prediction in Interior Permanent Magnet Synchronous Motors (IPMSMs) for smart industrial and precision drive control applications. A highly integrated control system with driving, monitoring, and diagnostic capabilities is developed, featuring both hardware and software components. The hardware comprises a custom-designed control core PCB, power stage board, and multifunctional interface board. At the heart of the system is the TMS320F28335 digital signal processor, which, in combination with analog and digital signal conversion components, enables motor drive signal generation, sensor data acquisition, data transmission, and real-time processing. On the software side, a human-machine interface (HMI) is integrated to provide real-time visualization of d-axis and q-axis current waveforms, allowing operators to monitor current fluctuations and identify potential anomalies during motor operation.
To further enhance the system’s capability in evaluating operational conditions, a Fast Fourier Transform (FFT) algorithm is implemented within the TI Code Composer Studio development environment. The algorithm performs frequency-domain transformation and feature extraction on the d-axis and q-axis currents generated during motor operation, establishing spectral indicators for fault detection. Signal spectral characteristics are then compared and analyzed for anomaly trends. This method is effective in early identification of abnormal conditions caused by bearing wear, magnetic circuit asymmetry, or load variations, thus improving the feasibility and accuracy of predictive maintenance strategies.
Moreover, the system incorporates a spectrum analyzer and near-field probes to perform field measurements of electromagnetic signals under actual operating conditions. By observing the near-field radiation and electromagnetic response of critical regions on the PCB, the system's stability and electromagnetic compatibility (EMC) characteristics can be further assessed. Comparing the measured spectra with simulated frequency responses facilitates the identification of potential sources of interference and high-frequency noise, providing guidance for optimizing PCB layout and filtering design.
Experimental results confirm that the developed system can reliably execute motor control and real-time current monitoring. The integrated frequency-domain diagnostic algorithm effectively captures critical abnormal signals during operation and demonstrates strong diagnostic robustness and system responsiveness across various load and speed conditions. The overall system offers a high degree of integration, modular architecture, and good scalability, making it suitable not only for IPMSM motor control but also for broader applications in high-performance electric motor monitoring systems.
This research provides a valuable reference for the development of motor health monitoring and intelligent control systems in Industry 4.0 environments. Future enhancements may involve integrating machine learning and artificial intelligence techniques to strengthen automated fault diagnosis and decision-making capabilities, paving the way for advanced smart predictive maintenance platforms.

 

Bio:
Yu Ching Tseng received the bachelor’s degree from National Taiwan Normal University, Taipei, Taiwan, in 2016. She is currently pursuing the master’s degree in electronics engineering at National United University, Miaoli, Taiwan. Her research interests include microwave measurement techniques and the extraction of electromagnetic parameters of materials.

Abstract:
Please refer to the attached file of abstract.

 

Bio:
Tz-Cheng Chiu received the Ph.D. degree in mechanical engineering from Lehigh University in 2000. He is currently a Professor of the Department of Mechanical Engineering at National Cheng Kung University in Taiwan. His research interests are on material characterization and reliability simulation for advanced packages, in particularly in the areas of fracture mechanics, nonlinear mechanical behaviors, and finite element simulation.

Abstract:
2.5-D integration of logic and high-bandwidth memory (HBM) using fan-out (FO) redistribution layer (RDL) is one of primary choices for high-performance computing applications. The multilayered RDL typically consists fine-pitch Cu lines and polyimide (PI) dielectrics, which allows higher number of electrical input/output and faster signal transmission and. However, the risks of cracking or debonding failure in the RDL are higher under thermal stresses experienced during packaging processes or in-use conditions due to the increased overall package size and the higher density of dissimilar materials arrangements. For the purpose of evaluating the risk of debonding failure under temperature cycling reliability test, it is important to evaluate the debond driving force and the interactions of the defact and RDL Cu pattern.
In this study, a fracture mechanics based 3-D global-local finite element model is developed to investigate the debonding growth driving force of the RDL Cu-trace and PI-dielectric layers in a 2.5-D package. In this model, the growth of cracking defect occurs both at Cu-PI interface and through PI. The driving forces for crack growth under temperature cycling thermal stresses are estimated. Results of the global analysis of the 2.5D package showed that the stress concentration region in the RDL are at the corners of the logic and HBM chiplets. From the perspective of the overall package configuration, the high-risk area of cracking failure is mainly around the periphery of each individual chiplet, as opposed to simply being judged only by the distance to neutral point at package center. From the subsequent crack growth driving force evaluation, it was shown that the RDL stress around the corner defect is mainly in shear, and the crack growth driving force is Mode-II and -III dominant. The shear stress induced rotations of the RDL Cu lines lead to variation in the crack driving force across each Cu line. Comparing the debond driving forces of each RDL layer interfaces, it was shown that the thermal stress induced defect growth in RDL is more likely to occur in layers close to the Si die than in layers close to the laminate substrate. This trend can be attributed to the high deformation mismatch between the Si die and the RDL. For RDL defect underneath the logic die, as the location of the defect moves closer to the corner of the die, the strain energy release rate increases, the Mode-I stress intensity factor decreases, and the Mode-II and -III stress intensity factors increase. The simulation procedure and results described in this paper can be applied to in the package design phase to the enhance the thermomechanical integrity and reliability of RDL.

 

Bio:
ZongYuan Wu has been with USI since 2019. He has experience working in China, Indonesia, and specializes in project management and Industrial Engineering. Since 2024, he joined the Digital Transformation Center to enhance internal processes with modern applications. Digital Transformation Center. Universal Global Scientific Industrial.

Abstract:
Develop a Mendix-based platform to manage and collaborate on changing customer requirements. The main data source is the Excel file updated regularly by the customers. There is no CRM system in the current system to integrate customer demand management, and this needs to be achieved through the internal development of auxiliary systems.
The data on the platform is highly sensitive and has a wide range of influences, so complete permission management is required for information dissemination: including price- related permissions, factory management permissions, work process review permission settings, etc., which are ultimately allocated and reviewed by platform administrators and factory administrators.
This platform will maximize the retention of basic fields as basic data and will also provide users with the option to choose file formats that meet the needs of different customers on the interface. And use the LSTM model to infer the profit-maximizing configuration.

 

Bio:
Jong-hyoung Kim is an Assistant Professor working in the Department of Materials Science and Engineering at Pukyong National University (PKNU), Republic of Korea, since 2024. Kim obtained his BS and PhD degrees in materials science and engineering from Seoul National University in 2012 and 2019, respectively. He was a postdoctoral researcher at Harvard University from 2019 to 2024. Kim can be reached by email at jhkim@pknu.ac.kr.

Abstract:
As semiconductor devices continue to scale down in size, advanced architectures such as 3D ICs and High Bandwidth Memory (HBM) increasingly incorporate complex geometries and multiple heterogeneous interfaces. These structures inevitably develop residual stresses due to factors such as thermal expansion mismatch, and lattice mismatch. Such stresses can lead to mechanical failures including cracks and delamination, ultimately compromising device reliability. In particular, the interplay between the thermal expansion mismatch of insulating and conducting layers and the heat generated during device operation can exacerbate residual stress levels. Therefore, a precise understanding and evaluation of stress distribution within advanced semiconductor devices is essential for ensuring their structural integrity and operational stability.

Conventional residual stress measurement techniques—such as wafer curvature, X-ray diffraction (XRD), and Raman spectroscopy—face significant limitations when applied to patterned 3D structures composed of ultra-thin films. These methods are often material-specific and lack the spatial resolution required for localized stress assessment. To address this challenge, a novel technique capable of measuring local residual stress in patterned thin-film structures is needed.

In this study, we propose an advanced version of slitting method that combines high-resolution Digital Image Correlation (DIC) with Focused Ion Beam (FIB) milling to precisely measure local stresses in thin films. Custom-designed DIC patterns are printed on the specimen surface using lithographic techniques. To protect these patterns during the FIB milling process, a sacrificial polymer layer is temporarily deposited. The deformation induced by stress relaxation around the FIB-milled slit is then captured via DIC analysis. Based on the measured deformation, specimen geometry, and material properties, a neural network-based model is developed to predict the residual stress fields. This approach enables accurate and efficient stress evaluation at the microscale.

In addition, finite element analysis (FEA) simulations were conducted to examine whether the deformation induced by stress relaxation follows a plane-strain condition when the aspect ratio of the slit exceeds a certain threshold. The simulation results were used to optimize the slit geometry for effective stress measurement. Furthermore, the influence of non-equibiaxial stress states was analyzed by investigating how stresses applied parallel to the slit axis affecting the resulting deformation. These insights provide a foundation for accurately interpreting complex residual stress states in semiconductor devices.

This presentation will introduce the theoretical background and experimental & computational results of the proposed method and discuss its potential to improve the mechanical reliability of advanced semiconductor devices.

 

Bio:
Currently serving as a project lead at NXP Semiconductors, with primary responsibilities in package-related evaluation, qualification, and design. Accumulated 6 years and 7 months of experience at NXP, complemented by 10 years of prior experience in assembly process engineering at ASE Group.

Abstract:
Handling small Ball Grid Array (BGA) packages during reliability testing presents significant challenges. To mitigate the risk of device loss and facilitate handling, the packages are mounted on a translation board. This approach is widely adopted, especially during temperature cycling qualification, a critical step in the product qualification process. To further secure the device and prevent mechanical damage, a cap-ring is incorporated into the translation board design. However, this modification significantly influences the test results, producing outcomes contrary to those observed in conventional board-level temperature cycling tests. Specifically, failures are concentrated in the central balls rather than the corners—a shift attributed to the mechanical stress introduced by the cap-ring. To investigate the root cause of this stress redistribution, a simulation is conducted. The results confirm that the altered stress distribution leads to increased stress concentration in the central solder joints, ultimately causing failure in those areas instead of the corners. This study also includes a comparative analysis of SAC105 and SAC405 solder balls under these test conditions, observed the SAC405 is extended the lifetime of temperature cycling test

 

Bio:
Tina Yang is currently a Platform Application Engineer in Data Center Group at Intel, responsible for high-speed interfaces design for server and workstation products. She received the M.S. in National Taiwan University of Science and Technology in 2012. She worked for Jabil from 2017 to 2019 and for Himax from 2019 to 2021. And she joined Intel Corporation as a signal integrity engineer for SI/PI customer enablement and support and technology development from 2021.

Abstract:
As high-speed Input/Output (HSIO) devices, such as servers and AI systems, designing channels on printed circuit board (PCB) has become increasingly complex and challenging. Ensuring data rate requirements is essential to meet the high bandwidth demands of Large Language Model (LLM) training Therefore, the Peripheral Component Interconnect Special Interest Group (PCI-SIG) defined the PCI Express Gen6 specification with a data rate of 64 GT/s in 2022, and the PCI Express Gen7 specification, with a data rate of 128 GT/s, is currently under development. From a board designers’ perspective, designing a system to fulfill the data rate requirements while reducing potential risks is becoming increasingly critical.

A methodology for testing the RX eye diagram, proposed in 2024, is based on PCB routing length and material. This approach enables board designers to efficiently evaluate design quality prior to finalizing the PCB. However, this methodology necessitates preparing various riser cards, potentially leading to extra cost. Alternatively, employing simulation over real measurements can more readily produce results and lower cost. In this paper, we aim to illustrate the simulation process and demonstrate its alignment with real measurements.

The purpose is to identify the differences in various PCB lengths and materials by simulation. The simulation needs to obtain real data from other areas within the end-to-end channel. For example, if the end-to-end channel includes cables, sockets, etc., we need to acquire loss data either from vendors or through measurement. In this study, we used measurements to obtain the loss data, aiming to closely approximate real system results.

After measuring the loss data from PCB, we can obtain different parameters and import them into simulation. By adjusting the EQ settings to generate diverse eye diagrams. In this study, we measured the end-to-end loss and applied 11 dB and 12 dB (matching the riser card loss in previous studies) to the PCB loss to observe changes in the eye diagram. The simulation results show that when an additional 11 dB is applied, the eye height/eye width is 18.5 mV/13.5 ps, which is within the PCI-SIG specification (18 mV/9.37 ps). However, after increasing the additional loss to 12 dB, the eye height decreases to 12.5 mV, which is below the guideline. These simulation results also corroborate the previous study. In real measurements, the results similarly show that using a 12 dB riser card causes the eye diagram to fall below the specification (16.43 mV, with the specification criterion being 17.5 mV). Utilizing this methodology provides a more cost-effective solution for designers, especially when compared to relying on conventional industry baseline criteria.

According to the above simulation and real measurement results, designers can comprehensively understand how to leverage simulation to optimize PCB design for high-speed I/O in AI systems. This simulation methodology offers PCB designers a clear approach to obtaining results across various PCB parameters, thereby enhancing confidence in meeting specification guidelines.

 

Bio:
Chiew Yee is working in Intel Platform System Engineering team as Systems and Hardware Enabling Engineer responsible for HSIO electrical and functional validation and customer issue debug

Abstract:
As the datacenter industry grows rapidly and high-speed interconnect signal data rate increases to PCIe Gen7 with Pulse Amplitude Modulation (PAM4) encoding, the board design is crucial to ensure the quality of the high-speed signal data transmission. Conventionally, in platform design and qualification stage, board design verification (DV), Signal Integrity (SI) and Electrical Validation (EV) tests are conducted to ensure the quality of the high-speed signal data transmission on the specific platform design. However, due to the cost and time constraints, board manufacturers may decide to omit some of the testing which may result in late found issues after platform post-production launch, such as PCIe link stability or data integrity issues that could potentially cause an outage in the datacenter fleet services. In this paper, a closed loop design and validation methodology for datacenter platform design which includes feedback loop and correlation of test results and issues found in DV, SI and EV tests is proposed and detailed case studies with including design, SI and EV analysis and correlation will be provided.
First, the layout of the board design revision1 will be checked against the predefined manufacturing and design constraints by automation tool to avoid the common PCB layout mistakes. Simulation of the board design should be performed to understand the electrical characteristics of the high-speed channel design before the platform in production. Any issues found from the checkers and simulation should be root caused and fixed in the design board before production.
Next, SI measurements should be performed on the productized board design revision1 by conducting end-to-end (E2E) loss and impedance characterization or through the Intel® Automatic In-board Characterization (AIBC) and Automatic Channel Characterization (ACC) testing to identify any outlier in the impedance. The SI measurements could be used to correlate to the board design layout and the previous simulation result conducted.
Lastly, EV tests should be performed across all high-speed channels with various end devices by obtaining the voltage margin and timing margin of receiver. Margin that is below the design guideline is considered low margin. Margin data analysis is required to understand the factors such as settings of component receiver equalization, high speed channel topologies and board designs that could contribute to lower margin performance and correlation with the previous board design verification and signal integrity testing could be done to understand cause poor signal integrity and provide fix proposal for future board design revision2.
With this closed loop design and validation framework applied on the datacenter board design, the components that could cause deterioration in the quality high-speed signal transmission are identified with risk assessment performed and enhancement to the high-speed channel design are developed and deployed to the board design revision2 as needed or fixes in the others component such CPU and end PCIe devices to ensure the health of the high-speed signal and datacenter fleet.

 

Bio:
Ben-Je Lwo is currently a Professor at Department of Mechanical and Aerospace Engineering, National Defense Univ., Taiwan

Abstract:
A newly developed glass-embedded fan-out, antenna-in-packaging (FO_AiP) structure, as shown in Figure 1, was previously proposed. Through ANSYS-HFSS simulation, the electromagnetic (EM) performance of the antenna designs has been demonstrated to be suitable for 5th generation (5G) millimeter-wave (mmWave) applications at 60 GHz [1]. In this study, a backpropagation (BP) artificial neural network algorithm, implemented in MATLAB, is used to improved electromagnetic behaviors of the antenna design. To this end, seven geometric dimensions of the antenna were first selected as design parameters, and a dataset of 300 records of electromagnetic performance from random combinations of these parameters was generated through HFSS simulations. Accordingly, the inputs to the BP algorithm are the seven geometric parameters, and the outputs are the antenna’s gain, bandwidth, and central frequency. As shown in figure 2, the BP model with five hidden layers was next selected as the neural network model of this study, and Adam optimizer was chosen as the optimizing algorithm. The PB model was then trained and validated using 280 records from the dataset, and accuracy of the BP model was subsequently verified using the remaining 20 records from test. After model verification, 78125 designs (i.e., 57, since there are five design levels for each of the seven parameters) were generated through combinations of geometric parameters. The 78125 designs were then input into the established BP model to predict the EM performance of each design. We next scanned and filtered the output of the 78125 records and selected the five best combinations of design parameters from BP model’s output. Finally, the antennas’ geometric dimensions from the best five records in the dataset were re-simulated using HFSS to verify the optimal FO_AiP designs.

 

Bio:
Thermal engineer

Abstract:
Nowadays, technology is growing rapidly in the semiconductor industry, driven by next-generation applications such as cloud computing networking servers, telecommunication devices, communication satellites, and automotive systems. Consequently, these applications demand high power performance in packages. As power levels continue to increase, heat dissipation techniques become increasingly critical. Thermal interface material (TIM) is a thermal pathway between the metal lid and die. To reduce thermal resistance of junction-to-case, bond line thickness (BLT) and thermal conductivity are key factors. In addition to maintaining high thermal performance, good reliability is an important characteristic of TIMs. In this study, we evaluated different types of TIM through reliability test, including Temperature Humidity Test(THT), Temperature Cycle(TC) and High-Temperature Storage (HTS). To compare these TIMs, a thermal test vehicle (TTV) was developed, providing detailed thermal characteristic of Heat Spread Flip Chip Ball Grid Array (HSFCBGA). TTV heaters were integrated into the die, and corresponding thermal sensors were distributed across the die to monitor changes in thermal resistance, which reflect temperature variations throughout the cycling process. The thermal measurement results from TTV were captured by Standard JEDEC thermal resistance equipment for junction-to-case thermal resistance. This study presents the thermal performance evaluation of TIM, summarized in Table1. TIMB showed significant advantages, including high thermal conductivity and good gap-fill capability. Compared with TIMA and TIMC, TIMC has twice the thermal conductivity of TIMA; however, the results show that their thermal performances are still similar. TIMD showed the best thermal performance among grease TIMs. The results also show that after Temperature Humidity Test(THT), Temperature Cycle(TC) and High-Temperature Storage (HTS) evaluation, the sample can maintain the original thermal characteristics. Also, TIM coverage has been verified via scanning acoustic tomography (SAT) after reliability testing. A series of thermal simulations was conducted based on a package thermal model constructed for the thermal test vehicle, which includes multiple heat sources. Verifying with thermal measurement, it’s shown that the thermal model can achieve highly accuracy. Comparing simulation and measurement results, thermal conductivity is not directly proportional to thermal resistance. Once thermal conductivity reaches a particular value, thermal resistance of trend is slowdown. In conclusion, verification and fundamental characteristic of thermal test vehicle was completed. It would be beneficial to achieve methodology in design part to reduce high thermal risk in high-power semiconductor system applications.

 

Bio:
Soo Hin is a Senior Thermal Mechanical Engineer for AMD Server Engineering Team and has 25 years of experiences in mechanical design in semiconductor industry. He started to involve in system thermal for server platform since he joined AMD in 2021. He has passionate and love to work with AMD server engineering team and collaboration across functional team to solve critical issue. Soo Hin has been married to Jenny for over 17 years and has one kid. As family they like to travel and enjoy food.

Abstract:
In recent years, rapid technological advances and the emergence of various solid-state drives (SSD) connectors in backplanes, such as EDSFF E1.S and E3.S, have necessitated unique designs for each SSD tray. This has contributed to increased non-recurring engineering (NRE) costs and longer lead times. The added challenge of validating different SSD types for SP7 Venice CPU performance compliance further complicates the process. This technical paper seeks to address these issues by introducing a versatile, small-scale common backplane chassis through design standardization and modularization, which ultimately reduces costs and development time while increasing flexibility.
This innovative design employs a shared SSD tray that accommodates 6 different thickness and types of EDSFF SSD, making it compatible with various backplane types. The backplane chassis consists of 8 SSD trays as modular and offering small scale to match 8 connectors on each backplane. Offering versatility, this design caters to both rackmount and benchtop platform systems, ensuring it can meet a range of application requirements. The SSD tray can be positioned vertically in backplane chassis for direct cooling from axial fan. Thermal simulation results indicate that the cooling solution provided in this design is sufficient to meet SNIA SSD Tcase specifications. Moreover, the consistent pitch of SSD connectors across different backplane types allows for the accommodation of up to 8 SSDs in a backplane chassis.
In summary, this paper presents a comprehensive solution for designing and validating a wide range of SSD types through the implementation of a common backplane chassis and common EDSFF SSD tray. This groundbreaking approach not only curtails NRE costs and lead times but also enhances adaptability and applicability across an array of system requirements.

 

Bio:
Seongkyu Choi is currently a master's student in the Department of Intelligent Robotics at Sungkyunkwan University, Suwon, South Korea. He received his B.S. degree in Mechanical Engineering from the Tech University of Korea, Siheung, South Korea. He is pursuing his M.S. degree through an academic–research collaboration between the Advanced Packaging and Reliability Innovation Laboratory at the Korea Institute of Industrial Technology (KITECH) and the Multiphysics System & Computation Laboratory at Sungkyunkwan University. His current research interests include the thermo-mechanical reliability of semiconductor packaging, particularly using Digital Image Correlation (DIC) and Finite Element Method (FEM) to analyze strain and warpage in advanced package structures.

Abstract:
With the rapid advancement of semiconductor packaging technologies, there is a growing shift toward heterogeneous integration, chiplet-based architectures, and large-area system-in-package (SiP) designs. These emerging trends, while enabling higher performance and functionality, also introduce significant thermomechanical challenges. In particular, the mismatch in the coefficient of thermal expansion (CTE) between dissimilar materials leads to warpage during thermal processing, which can generate localized strain at solder ball interconnections. This strain accumulation is increasingly recognized as a critical factor influencing the long-term reliability and service life of advanced electronic products.
Traditional methods for evaluating solder joint reliability often rely on destructive cross-sectional imaging or time-consuming thermal cycling tests. To address these limitations, this study proposes a non-destructive framework that quantitatively assesses the thermomechanical behavior of ball grid array (BGA) packages using digital image correlation (DIC) and finite element analysis (FEA).
Our research will focus on BGA packages with 400 µm solder ball pitch, which remain widely used in industry and serve as a suitable platform for analyzing package-level deformation mechanisms. Full-field 3D DIC will be employed to capture the global out-of-plane warpage of the package under controlled thermal loading, while 2D DIC will be used to extract in-plane strain distribution near critical solder joints. These experimental measurements will be compared against FEA simulations constructed with measured material properties, including Young’s modulus (via nanoindentation) and CTE (via DIC-based thermal expansion tracking). In this configuration, the warpage of the package acts as a displacement boundary condition on the solder ball interconnections, inducing significant strain particularly at the outermost joints, where the deformation is most concentrated.
A key objective of this study is to establish a clear correlation between experimentally measured warpage and strain fields and the corresponding simulation results. Through iterative tuning, we aim to validate the FEA model against DIC data to ensure consistency in both global warpage patterns and local strain behavior, thereby confirming the model's predictive capability.
Once validated, the FEA model will be utilized to investigate the relationship between warpage and strain across different geometric configurations and material settings. This is expected to reveal a robust and reproducible correlation between package-level warpage and solder joint strain, suggesting that warpage can serve as an effective proxy for interconnection reliability evaluation. This approach will potentially enable engineers to predict strain-induced reliability risks based solely on non-destructive warpage measurements
Furthermore, the FEA model to be validated in this study is expected to lay the groundwork for its practical application in optimizing package structures to reduce thermally induced warpage in next-generation electronic systems. By providing a reliable and accurate simulation framework, this methodology will allow engineers to virtually explore various design parameters and material combinations before physical fabrication. Such a predictive approach is anticipated to support more informed decision-making in the early design phase, ultimately contributing to improved reliability, reduced development costs, and a lower risk of solder interconnect failures during actual operation.

 

Bio:
Member of Technical Staff as Customer Solutions Engineer at AMD, where Fabian plays a key role in enabling and validating cutting-edge silicon solutions for global customers. With hands-on experience collaborating across cross-functional teams, he ensures the successful delivery of high-quality silicon and critical platform ingredients, tailored to customer requirements. Fabian has worked closely with numerous industry partners to bring complex products from early engagement through validation and deployment till product launch. His work bridges the gap between engineering and customer success, helping partners accelerate time-to-market and achieve robust platform readiness.

Abstract:
In the realm of the Server product development program, Server platform developers have expressed concerns on memory interface electrical healthiness. Server system design has grown more complex, leading to the need for stricter board design rules, more advanced circuit knobs tuning and increasing rigorous validation coverage. Consequently, post-silicon electrical validation of DDR5 is crucial in product release qualification for aggressive launch with an upright board design that supports sufficient list of approved DIMM vendor modules. In this work, we designed a data-driven automation system to collect and postprocess DDR margin metadata. By integrating design-on-simulation technologies and utilizing advanced testing and measurement techniques, we have enhanced the data management framework for HSIO margin data, facilitating efficient and actionable insights.

This paper presents a comprehensive analysis of memory configuration and design influencers. The study focuses on the impact of various design parameters on memory performances, specifically examining Vref and Delay margin influencers. Key influencers identified in the study include DRAM configuration, DIMM Channel, DIMM pitch, Via-In-Pad routing on SMT connector, PCB material, PCB layer routing and routing lengths which are crucial in understanding the variations in memory performance. These elements are analyzed to determine their influence on the VREF values for top margin and bottom margin, as well as Delay values for left margin and right margin, providing insights into how design choices can optimize memory configurations.

The metadata framework involves a detailed examination of memory routing layers, topology, and subchannel configurations, offering a granular view of how these components interact to affect overall system performance. The findings suggest that specific design parameters, such as PCB material and SMT VSS via count, play significant roles in influencing VREF values, thereby impacting the efficiency and reliability of memory systems.

The findings suggest that specific design parameters, such as channel routed on bottom microstrip on 14-layer PCB has reported poorer margin at the lower side which is close to the margin limit line. Besides, in order to get better margin, the key influencers suggested the use of 1Rx8 DIMM modules instead of 2Rx4 DIMM modules to gain ~10mv VREF bottom margin uplift.

Our comprehensive study serves as a pivotal study in the realm of memory configuration, offering a detailed exploration of design influencers and their impact on VREF values. The findings underscore the importance of strategic design choices in achieving optimal memory performance, paving the way for future innovations in memory technology

 

Bio:
Honglin Li is a junior student at the School of Eilte Engineer College, Dongguan University of Technology. His research interests focus on machine vision and pattern recognition.

Abstract:
For applications in autonomous driving, robotic navigation, and other intelligent system scenarios, traditional SLAM (Simultaneous Localization and Mapping) algorithms face critical challenges in dynamically separating camera motion from object motion within complex scenes, thereby leading to significant degradation in 3D model construction accuracy. This paper introduces an innovative 4D Gaussian splashing approach enhanced by time-scene flow technology, realizing precise dynamic scene modeling through multi-faceted technical innovations. It integrates advanced scene flow algorithm optimization with epipolar geometric constraint mechanisms to establish a robust spatiotemporal correlation model, enabling efficient estimation of complex camera motion parameters. Through novel optical flow field decomposition strategies, the method achieves effective decoupling of object dynamics from the scene flow framework. Furthermore, a four-dimensional Gaussian splashing model fusing 3D spatial dimensions with temporal dynamics is employed to dynamically characterize scene structures, complemented by a multi-layer motion compensation algorithm system to mitigate the interference of moving objects on 3D modeling.
This proposed methodology breaks through the modeling bottlenecks of conventional SLAM in dynamic environments, demonstrating remarkable improvements in real-time environmental perception and adaptive motion handling capabilities. It provides a more robust technical solution for intelligent systems to achieve precise environmental understanding in dynamic scenarios, showcasing significant application potential in fields such as autonomous vehicle navigation, robotic environmental mapping, and intelligent scene perception

 

Bio:
Jeong Yeonwook is a graduate student in the Department of Semiconductor Convergence Engineering at Sungkyunkwan University. His research focuses on thermal interface materials for advanced semiconductor packaging, with a particular emphasis on underfill and non-conductive film (NCF) materials.

Abstract:
With rapid advancements in cutting-edge technologies such as artificial intelligence (AI), fifth-generation (5G) wireless networks, and autonomous driving, semiconductor chips increasingly demand higher performance, faster processing speeds, and greater integration levels. Consequently, effective thermal management has emerged as a critical challenge to ensure device reliability and efficiency. Epoxy-based underfills, extensively utilized in flip-chip packaging due to their excellent mechanical stability, process compatibility, and ease of handling, traditionally employ silica (SiO₂) fillers. However, silica fillers possess inherently low thermal conductivity, which is insufficient for meeting the heightened thermal dissipation requirements associated with next-generation high-power semiconductor devices. Thus, alternative ceramic fillers with intrinsically high thermal conductivity, such as hexagonal boron nitride (hBN), alumina (Al₂O₃), and aluminum nitride (AlN), are being actively explored.
Among these ceramic fillers, hBN stands out for its exceptional thermal conductivity exceeding 300 W/m·K, excellent electrical insulation characteristics, low dielectric constant, and outstanding chemical and mechanical stability. Nonetheless, hBN’s intrinsic platelet-shaped morphology results in weak interparticle bonding, facilitating the formation of internal porosity when nano-sized particles aggregate into larger micro-sized spherical or fibrous structures. This porosity significantly diminishes both thermal conductivity and mechanical integrity. Conventional sintering methods alone typically struggle to achieve adequate densification and strong interparticle bonding, leaving residual pores and suboptimal thermal conduction paths.
To overcome these structural limitations, this study introduces Al₂O₃ precursors as effective sintering aids during the fabrication of hybrid hBN-Al₂O₃ composite fillers, dramatically enhancing particle neck formation and significantly reducing internal porosity. Micro-sized spherical fillers were fabricated via spray drying of slurries containing nano-hBN and Al₂O₃ precursors. Additionally, micro-sized fibrous fillers were prepared by electrospinning polymer-based solutions incorporating the same mixture. Quantitative evaluations through finite element method (FEM) analyses confirmed that the addition of Al₂O₃ substantially enhanced microstructural stability and thermal conductivity by promoting effective interparticle necking and minimizing internal voids.
Moreover, the blending of spherical and fibrous fillers in optimized ratios enabled the formation of extensive three-dimensional thermal percolation networks, markedly improving thermal conduction pathways compared to single-form fillers. FEM simulations further optimized these filler ratios, demonstrating that hybrid filler structures significantly outperform singular spherical filler systems in thermal conductivity. Furthermore, amino silane (APTES) surface treatment effectively introduced reactive amine groups (-NH₂) onto filler surfaces, substantially improving interfacial bonding with epoxy resins and reducing thermal interfacial resistance. Experimental measurements, corroborated by molecular dynamics (MD) simulations, quantified the effectiveness of these interfacial enhancements.
The developed hybrid spherical and fibrous hBN-Al₂O₃ fillers demonstrate significantly enhanced thermal conductivity, markedly reduced internal porosity, and improved interfacial compatibility with the epoxy matrix. These characteristics collectively highlight their strong potential as next-generation thermal interface materials for advanced underfill materials in high-performance flip-chip packaging.

 

Bio:
Wen-Chieh Tsao is currently a second-year master's student in the Department of Electronic Engineering at National Taipei University of Technology (NTUT). He brings several years of industry experience in process engineering and production management within the electronics sector. His current research centers on process optimization and low-frequency noise analysis of IGZO thin-film transistors (TFTs), with a focus on applications in back-end-of-line (BEOL) integration and 3D integrated circuits (3D-ICs).

Abstract:
In this work, we present a low-frequency noise (LFN)-based evaluation methodology for assessing the reliability of bottom-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under different post-deposition treatments. As monolithic 3D integration demand low-temperature and BEOL-compatible devices, oxide semiconductors such as a-IGZO have emerged as promising candidates due to their excellent mobility and low thermal budget process compatibility. However, hydrogen incorporation during deposition and fluorine doping can significantly affect the device’s electrical performance [1], [2]. Improving electrical stability remains a key technical challenge. Therefore, this study investigates the low-frequency noise and interface trap characteristics of a-IGZO TFTs subjected to oxygen annealing at the back-gate insulator (BGI) and fluorine doping in the active layer.

 

Bio:
Sheng-Wei Tsai received the B. Sc. degree in electronic engineering from National Formosa University, Yunlin, Taiwan, R.O.C., in 2023. He is currently working toward the M.S. degree in the Institute of Precision Electronic Components, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
Advanced heterogeneous integration packaging (AHIP) often requires the creation of high aspect ratio TSVs in silicon substrates. Deep reactive ion etching (DRIE) is the main method currently used, especially under the requirements of precise diameters and fine pitches. Although it can achieve high aspect ratio vias, the processing of DRIE takes a long time and special masks need to be made for different designs, which is costly and limits the flexibility of design and production. In addition, DRIE uses fluoride gas, which produces waste gas and liquid treatment problems and is inconsistent with requirements of ESG environmental sustainability. Modern laser technology has made rapid progress and laser drilling method is regarded as a potential alternative due to its advantages of fast speed, high flexibility, low cost and no need for fluoride gases. It is in line with the trend of miniaturization and high performance of packaging. The industry is in urgent need of fast, flexible and environmentally friendly TSV manufacturing technology, but the existing laser technology applied in TSV production still needs to be optimized to meet the requirements of advanced packaging.
In the paper, we use two process approaches. In the first approach, a slightly larger via diameter is drilled on the surface of the silicon substrate with low energy laser. The purpose is to create a track with a larger via to guide the second high-energy laser to drill via more concentratedly. The second process is to drill a small-diameter through vias, and we use a 20-um laser beam to drill through the silicon substrate. Figures 2 and 3 show the results of making low taper ratio TSVs on silicon substrates using Ultrashort Pulse IR laser. The entrance via diameter (Din) on the top surface of the substrate is 19.7 µm, the middle via diameter and the exit via diameter (Dout) are 16.5 µm and 17.7 µm respectively. The entrance via taper is calculated as 0.229° on the top surface of the 250 µm (h) thick silicon substrate. This study uses Design of Experiments (DOE) to evaluate the effects of five key process parameters, including peak power, drilling time, pulse frequency, number of pulses, and focal plane position, on quality factors such as via roundness, taper, sidewall roughness, and heat-affected zone (HAZ). Analysis of Variance (ANOVA) is used to find out the significant factors affecting the experimental results, and Response Surface Methodology (RSM) is used to establish the optimal process parameters.

 

Bio:
Jhan Jhih-Syuan received the B.Sc. degree in Electrical Engineering from Tunghai University, Taichung, Taiwan, R.O.C., in 2023, She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
Applications of AI, automotive electronics, and 5G/6G wireless communications are driving the rapid development of heterogeneous integrated packaging that integrating various small chips (chiplets) and placing them on the same substrate have faced many challenges, among which power overheating and heat dissipation considerations have become the primary difficulties. Advanced heterogeneous integrated packages such as CoWoS use silicon substrate as a platform of interconnection of electricity for various chiplets. Silicon substrate faces problems with heat dissipation and warpage in packaging processes due to CTE mismatch of different package materials. Therefore, the development of glass substrates provides a viable option other than silicon substrates for high-frequency and high-density packaging. However, the thermal conductivity of glass substrate in advanced packaging has also become the next dilemma. Whether there is a material with a suitable CTE to avoid warpage issue and quickly dissipate heat has become the primary research goal.
Aluminum nitride (AlN) ceramic substrate has the potential to be a candidate besides silicon and glass substrates used in advanced heterogeneous integrated packaging. From the comparison of data in the table, silicon, glass, and AlN all have a coefficient of thermal expansion (CTE) suitable for packaging, where AlN has more excellent high thermal conductivity.
In this paper, a picosecond infrared (IR) laser with a wavelength of 1064 nm was employed to drill blind and through vias with a diameter of 50 um to 30 um on a 600 m thick AlN substrate. By combining different optical lenses and focal lengths, high aspect ratios of through vias with the values of 1:12 to 1:20 can be formed on a 600 um thick AlN substrate. Laser drilling quality factors such as via roundness, taper, sidewall roughness, and heat-affected zone (HAZ) will be examined and reported. Design of Experiments (DOEs) and ANOVA analysis are performed to evaluate the effects of process parameters, including peak power, drilling time, pulse frequency, number of pulses, and focal plane position, on these quality factors.

 

Bio:
Mr. Hao-Tse Lo is currently a master's student in the laboratory of Professor Masahiro Kozako in the Department of Electrical and Electronic Engineering at Kyushu Institute of Technology, Japan. His research focuses on polymer-based composite materials for applications in thermal conductivity and electrical insulation, particularly epoxy–alumina systems. He specializes in enhancing thermal conductivity through electric field-induced filler alignment and has presented his work at multiple academic conferences in Japan. Mr. Lo received his bachelor's degree from National Taipei University of Technology and is currently pursuing his master's degree at Kyushu Institute of Technology.

Abstract:
This study focuses on enhancing the thermal and electrical properties of epoxy-based insulating substrates through electric field-induced filler alignment. The orientation of alumina fillers in the thickness direction promotes thermal conductivity while minimizing filler content—thus mitigating issues such as increased viscosity, reduced moldability, and compromised electrical insulation that typically accompany high filler concentrations. To satisfy the key requirements of insulating substrates—thermal conductivity, electrical insulation, and heat resistance—a filler chain structure was formed prior to resin curing. Thermal conductivity was evaluated via the laser flash method, with calculations based on thermal diffusivity, specific heat capacity, and density. Dielectric constant measurements were conducted using an impedance analyzer. The thermal conductivity and dielectric properties of epoxy-alumina　composites with aligned fillers are presented and discussed, demonstrating the effectiveness of electric field-assisted alignment in enhancing overall substrate performance.

 

Bio:
I'm Andy Chang, is currently the R&D Engineer for Tong Hsing Electronic Industries, a manufacturer of ceramic substrate with metallization, and custom semiconductor packages. My current work is on DPC on ceramic design or other advanced electronic sensor devices. The products I contacted are Optical transmitters (Laser Diodes), RF/Microwave Devices, High power LED devices and Medical.

Abstract:
As the size of electronic devices continues to shrink and the demand for higher efficiency increases, the requirements for product reliability also rise, presenting greater challenges to material properties. While ceramic substrates offer excellent thermal conductivity, their brittleness makes thin substrates prone to cracking. Therefore, silicon nitride substrates, with superior thermal conductivity compared to glass and higher toughness than other ceramic substrates, have emerged as one of the optimal solutions to address this challenge.
Silicon nitride (Si₃N₄) has become a promising alternative to aluminum nitride (AlN) and glass substrates in advanced electronic applications due to their exceptional bending strength and fracture toughness. Compared to AlN, Si₃N₄ exhibits superior fracture toughness resistance and mechanical shock resistance, significantly reducing the risk of substrate cracking during fabrication and assembly processes. This leads to improved yield and enhanced product reliability. In contrast to glass substrates, Si₃N₄ offers higher thermal conductivity and structural robustness, and can withstand elevated temperatures and harsh thermal cycling conditions, making it particularly suitable for high-power or thermally demanding environments.

In thin-film circuit processes, Si₃N₄ substrates provide a low coefficient of thermal expansion (CTE), enabling precise and stable thin-film deposition and photolithography. These characteristics support the fabrication of high-density, high-accuracy resistors and conductor patterns. Si₃N₄ also delivers excellent electrical insulation, effectively isolating conductor layers to maintain signal integrity and improve product safety.

When applied in electronic systems, Si₃N₄ substrates significantly enhance heat dissipation and mechanical reliability, making them ideal for applications such as electric vehicle power modules, high-frequency communication devices, and laser modules that demand long-term operational stability. Overall, the combination of mechanical durability, thermal performance, and electrical insulation makes silicon nitride a critical material for next-generation high-performance electronic designs.

 

Bio:
Dr. Ching-Yu Liu is a Senior Engineer at the Industrial Technology Research Institute (ITRI) in Taiwan, specializing in MEMS sensors, semiconductor processes, and FEM simulation in solid and thermal mechanics. She earned her Ph.D. from National Tsing Hua University, focusing on spherical silicon chip technology for retinal prosthesis. Dr. Liu previously worked at Blickfeld GmbH in Germany on LiDAR sensor assembly, and served as Project Manager at Iridium Medical Technology Co. (IMTC), contributing to the development of a bionic artificial retina. With strong international and interdisciplinary experience, she is passionate about advanced MEMS devices and next-generation packaging technologies.

Abstract:
Haptic feedback has become one of the most important sensory interfaces, playing a critical role in enhancing user interaction across applications such as virtual reality (VR), augmented reality (AR), wearable devices, and advanced human-machine interfaces. A key challenge in this field is the development of thin, flexible, and integrable surfaces that can deliver rich and controllable tactile sensations. When a human finger slides over a textured surface, the resulting interaction force is composed of horizontal friction and vertical vibrations. Accurately reproducing this interactive force pattern enables the rendering of virtual textures that simulate real materials. Among the various haptic technologies, electroadhesion stands out due to its simplicity in structure and driving mechanism, making it a promising candidate for next-generation haptic feedback systems.
Traditional electroadhesive devices that incorporate dielectric layers often require high driving voltages—typically in the range of several hundred volts—and are susceptible to dielectric breakdown, limiting their long-term reliability and safety in interactive applications. To address these limitations, we propose a thin-film electroadhesive component that operates at low voltage while maintaining effective and tunable haptic performance. Our device is fabricated using a low-temperature process with polyvinylidene fluoride (PVDF), a high-permittivity dielectric polymer, and features thin-film electrodes to reduce thickness and improve mechanical flexibility. The system is designed to be controlled via a custom-built interface, enabling real-time adjustment of waveform type, pulse width, frequency, and voltage amplitude.
This flexibility allows the device to dynamically modulate the stiffness and adhesive forces experienced by the user’s fingertip, thereby rendering various surface textures and simulating different material sensations. To experimentally validate the performance of our device, we developed a customized friction force measurement setup, consisting of a robotic arm to apply controlled lateral motion and a precision force gauge to measure the resulting friction forces. The measurements indicate that the electroadhesive feedback force ranges from tens to hundreds of millinewtons, depending on the applied voltage and control parameters.
Additionally, we conducted finite element simulations using the same structural parameters and loading conditions to predict electroadhesive behavior. The simulation results showed excellent agreement with experimental data, with deviations less than 10%, confirming the reliability and accuracy of our design and modeling approach.
One of the key advantages of this electroadhesive component is its versatile integrability. Through pattern-based design and fabrication, the thin-film structure can be configured into various form factors. For instance, we developed a ring-shaped electroadhesive device capable of wrapping around or rotating beneath the finger. This flexible design enables seamless integration with other haptic feedback technologies, such as vibrational actuators or deformation devices, facilitating multi-modal tactile feedback in compact and adaptive formats.
Overall, this work demonstrates a scalable, low-voltage, and customizable electroadhesive component that can serve as a fundamental building block for future haptic interfaces in both wearable and immersive systems.

 

Bio:
Naoko Araki received the M.S. and Ph.D. degrees in science from Nara-Women’s University in 2003 and 2006, respectively. She joined Daicel Corporation in 2006, where she conducted research and development of resins for optical waveguides and fibers having flexibility and thermal stability. In 2014 she also joined WOW alliance in Institute of Science Tokyo where she engaged in the development of adhesives. Her research interests include cationic polymerizable resins having high heat-resistance.

Abstract:
We have developed a novel permanent adhesive suitable for both wafer-on-wafer (WOW) and chip-on-wafer (COW) processes, enabling room-temperature bonding without the need for adhesion promoters. This adhesive also shows promise for hybrid bonding applications. Its unique molecular structure provides excellent thermal stability, low outgassing, and minimal weight loss at elevated temperatures, making it ideal for 3D integration using ultra-thin wafers and bumpless through-silicon via (TSV) interconnects.
In previous WOW applications, permanent adhesive demonstrated low contact resistance and high uniformity in TSV interconnects with lengths as short as 12 μm on 300 mm wafers [1–6]. However, COW processes face challenges in using adhesion promoters due to the small surface areas of individual chips [7]. To overcome this limitation, a new adhesive has been developed that does not require adhesion promoters while retaining the thermal and mechanical advantages demonstrated in WOW applications. This adhesive can be coated on only one side, significantly simplifying the bonding process and broadening its applicability to a wider range of integration processes.
The new adhesive can be applied via spin-on, spray, or roll-to-roll techniques, forming uniform layers under 10 μm thick. It cures at 135–170°C and thermally stable up to 300°C. After curing, it exhibits strong adhesion to both Si and SiO₂ surfaces and maintains excellent stability during thermal cycling [8]. Chips and wafers bonded at room temperature showed high mechanical strength and stability and reliability after curing, confirming its suitability for high-throughput and multilevel stacking. We also evaluated its performance in hybrid bonding using Cu-patterned wafers [9]. The adhesive was spin-coated, cured, polished, and diced, followed by hot compression bonding. The resulting copper–polymer hybrid interface was robust and electrically stable, indicating high compatibility with hybrid bonding processes. Notably, the resin’s tolerance to surface contamination offers a key advantage over conventional SiO₂-based bonding, which is sensitive to sub-nanometer particles. The softer properties of the resin may allow bonding even in the presence of sub-micron contaminants, potentially improving yield and process robustness. In addition to its mechanical and thermal properties, the adhesive’s compatibility with both WOW and COW processes—without requiring surface modification—makes it a versatile solution for next-generation 3D integration. Its ability to form reliable interconnects at room temperature contributes to reduced thermal stress and improved process efficiency.
In summary, the newly developed adhesive supports permanent bonding in both WOW and COW processes, and has been specifically demonstrated for hybrid bonding as an alternative to dielectrics. The capability of room-temperature bonding and elastic material characteristics provide the benefits of a low thermal budget in the bonding process, such as reducing warpage and increasing the margin of Cu-Cu connectability. This adhesive makes it a promising solution for advanced semiconductor packaging and 3D integration technologies.

 

Bio:
Shin Jungbin is currently a Master's student in the Department of Intelligent Fab. Tech Convergence at Sungkyunkwan University, with a research interest in high thermal conductivity ceramic material synthesis and composite fabrication. Their recent work involves the development of ceramic-based thermal interface materials, particularly in the area of thermal filler engineering and simulation-based analysis for advanced heat dissipation applications.

Abstract:
Flexible thermoelectric generators (FTEGs) are gaining increasing attention as self-powered energy harvesting solutions, particularly for next-generation wearable electronics, biomedical monitoring systems, and untethered Internet-of-Things (IoT) devices. The core performance of an FTEG depends heavily on its ability to maintain a substantial temperature gradient (ΔT) across the thermoelectric (TE) legs. However, commonly used flexible substrates such as polydimethylsiloxane (PDMS), polyimide (PI), or silicone elastomers exhibit intrinsically low thermal conductivity, which leads to poor lateral heat spreading and localized heat accumulation. This thermal bottleneck critically limits the achievable ΔT and, consequently, reduces the device’s power output.
To overcome this limitation, this study proposes a new class of anisotropic high-thermal-conductivity insulation films based on aligned aluminum nitride (AlN) nanofibers. AlN was selected due to its unique combination of high intrinsic thermal conductivity, electrical insulation, and chemical stability. Electrospinning was employed to fabricate precursor Al-containing nanofibers with high aspect ratios. These fibers were subsequently converted into pure wurtzite-phase ceramic AlN fibers through a high-temperature carbothermal nitridation process under an ammonia atmosphere.
The AlN nanofibers were then directionally aligned and laminated in multiple layers with orthogonal stacking configurations (0° and 90°). The layered composite structure was thermally pressed to promote intimate interfacial contact and directional heat pathways. This configuration enabled the film to exhibit high in-plane thermal conductivity while maintaining electrical insulation—an essential requirement for TE device integration.
To enhance both solar radiation absorption and mechanical flexibility, the top layer of the film was impregnated with a polymer binder mixed with small amounts of carbon black. Silver nanowire (AgNW) networks were employed as flexible electrodes by spin-coating onto the film surface. The fabricated composite film demonstrated excellent mechanical durability, withstanding more than 10,000 cycles in bending fatigue tests without significant performance degradation.
When integrated as a heat-spreading and insulating layer in a Bi₂Te₃-based p/n-type FTEG module, the film showed a significant improvement in the system’s overall performance. Continuous power output data collected over 72 hours under real-world ambient solar conditions revealed that the use of the anisotropic thermal film increased ΔT and boosted power generation compared to control samples with non-engineered substrates.
In addition, finite element method (FEM) simulations were conducted to analyze heat diffusion behavior and to predict the resulting thermoelectric voltage and output power. The simulation results closely matched the experimental data and confirmed that the system followed the theoretical power relationship P=(n⋅S⋅ΔT)2/4RLP = (n·S·ΔT)^2 / 4R_LP=(n⋅S⋅ΔT)2/4RL, where S is the Seebeck coefficient and R_L is the load resistance. The simulations also illustrated the role of fiber orientation, stacking geometry, and material anisotropy in establishing a uniform and efficient temperature gradient across the TE legs.
This work demonstrates a scalable and effective strategy to fabricate anisotropic thermal interface films that are electrically insulating, thermally conductive, and mechanically flexible. The developed AlN nanofiber-based composite is not only a powerful platform for improving FTEG performance but also provides a practical foundation for heat management in wearable electronics, self-powered sensors, and energy-harvesting devices operating with low-grade thermal sources.

 

Bio:
Jeff Chen, graduated from Mechanical Engineering Dep., NYUST in 2002 and started to work in USI as a manufacturing engineer from 2004. He has the experience on board and system assembly. Currently, he focuses on SiP new process and technology in COD. Yoyo Chen, received her bachelor’s degree in Chemical Engineering from Anhui Normal Universi-ty. She started working in 2007 as a manufacture engineer. She has more than 17 years’ experiences in SMT field. Currently, she is responsible for new product introduction and advanced technology development for SiP products.

Abstract:
As businesses continue to struggle with resource allocation and climate change, ASE group is seeking to improve its value contribution through innovations that will promote social and environmental benefits. ASE group’s low carbon strategy is an integral part of the company’s move towards Net Zero, the company continues to improve energy efficiency and adopt renewable energy alternatives across its operations.
The Formic Acid Vacuum Reflow Oven had been used in power module products for years, it uses solder preform to be the interconnection material and no need the clean process after reflow due to no “Flux” in the solder preform, but solder preform process is not easy to be used in SiP module, so if we can have Formic Acid Vacuum Reflow and keep the original solder printing process, then the deflux clean process of SiP module also can be removed as power module, not only saving clean equipment and cleaning addition agent spending but also electric power consumption and wastewater discharge.
The conventional reflow process needs cleaning process to remove flux, not only water-soluble solder paste but also non-clean one due to the post processes requirement, such as underfill or molding, so the deflux clean is always the must process in current SMT. Deflux clean machine consumes a lot of electric power to drive and discharge the considerable wastewater during the cleaning process after SMT reflow, it costs money to purchase flux cleaning equipment and consumes our precious water resources in TW. If there is an alternative process to produce the same products without flux cleaning, we will not need to buy clean machines to save money and electric power, then the saving water can be made good use in others, both economic and environmental benefits can be achieved in one time if this alternative process can work.
As Figure 1, the new/alternative process is expected to use “Formic Acid Vacuum Reflow Oven” with “Flux-free solder paste” instead of the conventional reflow oven, then the clean station can be pulled out from SMT process.

Figure 1. Conventional VS Formic Acid Reflow

The purpose of this paper is to evaluate the engineering workability of the Formic Acid vacuum reflow oven and flux-free solder paste for SiP (System in Package) module to apply the Formic Acid reflow without “Flux”, intend to provide the initial evaluation results for further study reference soon in ASE group.

 

Bio:
Li-Wei Yao has worked at the Industrial Technology Research Institute Electronic and Optoelectronic System Research Laboratories in Taiwan for more than 17 years. He specializes in in-mold electronics technology, 3D conformal sensor module integration, thin-film photolithography etching process, and integration technology for the foldable touch AMOLED panels.

Abstract:
This study presents the integrated design and simulation of a thermoformed center console, highlighting the application of advanced materials and manufacturing technologies to achieve a low-carbon, lightweight, and energy-efficient center console for the automotive industry. The thermoforming process was modeled using simulation software, and the metal screen-printed ink mesh pattern was incorporated to facilitate mesh generation and setting of boundary conditions. A comprehensive analysis of mesh deformation before and after thermoforming facilitates the prediction of surface decorative pattern displacement, ensuring that the pattern after thermoforming aligns with the intended design position. The offset compensation method demonstrates an accuracy of over 90%, underscoring the approach's efficacy. The experimental results indicate that the circuit displacement remains below 0.5%, substantiating the design's stability and reliability. Notably, at a distance of 41 millimeters from the knob, the strain value ranged between 0.46% and 0.5%.

 

Bio:
Nahye Kim received the B.S. degrees in the department of materials science and engineering from the Korea University, Seoul, South Korea, in 2025. She is currently researching in Korea Institute of Industrial Technology and her research interests include the advanced packaging technology.

Abstract:
The advent of the artificial intelligence era and the ongoing miniaturization of semiconductor devices have driven unprecedented demand for high-density, high performance computing technologies, particularly High Bandwidth Memory (HBM). This trend necessitates a significant increase in interconnection density to meet evolving computational requirements. To address these technological challenges, advanced packaging technologies have emerged as promising solutions. Especially, Cu hybrid bonding is one of the most potential methods for vertical stacking with high density due to copper's superior electrical conductivity, cost-effectiveness, and absence of intermetallic compound (IMC) formation. However, copper's inherent susceptibility to oxidation at elevated temperatures poses substantial challenges, leading to both electrical and mechanical degradation that compromises bonding integrity and overall device performance.
This study proposes a glucose vapor-assisted Cu direct bonding to suppress copper oxidation. Glucose was selected as a reducing agent as its hydroxyl and aldehyde groups readily donate H atoms or electrons, serving as a reducing agent for Cu. Furthermore, glucose is eco-friendly, non-toxic and stable at room temperature. Unlike other approaches that require additional plasma treatment or passivation layers for copper oxidation prevention, the proposed glucose vapor method eliminates these supplementary steps, thereby reducing both manufacturing costs and processing time.
The experiment was conducted with 1 micrometer-thick copper films plated on 1 cm × 1 cm and 0.5 cm × 0.5 cm silicon substrates. At first, heating process on hot plate was conducted with and without glucose vapor to confirm the feasibility of oxidation inhibition on Cu. Specimens heated with glucose vapor had much less copper oxide on the surface compared to the other.
This oxidation suppression operates throughout the thermal compression bonding (TCB) process. Comparative analysis was conducted between specimens exposed to glucose vapor and specimens bonded without glucose vapor to evaluate the oxidation prevention efficacy and bonding quality enhancement of glucose. An X-ray photoelectron spectroscopy (XPS) was performed to detect copper oxide’s peak on the surface. Additionally, sheet resistance measurement was performed to assess electrical property changes induced by copper oxide layer formation. The results of both measurements demonstrated oxidation suppression in glucose vapor-assisted samples, confirming the protective mechanism's effectiveness in preventing surface oxidation.
The glucose vapor-assisted approach facilitated Cu direct bonding processes at temperatures below 250℃, undercutting standard bonding temperature of 300-400℃. The bonding quality was evaluated through shear strength measurements and scanning electron microscopy (SEM) cross-sectional analysis to assess mechanical integrity. The specimens benefiting from glucose vapor assistance achieved higher bonding integrity compared to untreated specimens.
The glucose vapor-assisted approach prevented copper surface oxidation during TCB process, resulting in enhanced mechanical strength and improved electrical conductivity. These comprehensive findings demonstrate the substantial potential of glucose vapor protection as a viable, environmentally sustainable, and cost-effective approach for copper oxidation prevention in advanced semiconductor packaging applications, particularly for Cu hybrid bonding.

 

Bio:
Mr. Shaoyou Lu is an engineer at Tong Hsing Electronics, specializing in the development of AMB (Active Metal Brazing) substrates for high-power modules. His expertise includes conductor design, ceramic integration, and electrical reliability. In this presentation, he will share insights on substrate design for high-power applications.

Abstract:
With the global emphasis on electrification, energy efficiency, and carbon neutrality, the demand for high-performance power electronics has grown rapidly in key industries such as electric vehicles (EVs), renewable energy systems, industrial automation, and railway traction. These applications require power modules capable of operating reliably under harsh conditions — high voltage, high current density, elevated temperatures, and frequent switching. To meet these stringent requirements, wide band gap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), have emerged as superior alternatives to conventional silicon due to their exceptional thermal stability, higher breakdown voltage, and switching efficiency.
As the power density of WBG-based systems continues to increase, the substrate materials used for packaging play an increasingly critical role. Substrates must not only provide mechanical support and electrical insulation but also serve as efficient thermal pathways to manage heat dissipation. Among the available substrate options, silicon nitride (Si₃N₄) ceramics have attracted significant attention due to their unique combination of high thermal conductivity, low dielectric constant, excellent mechanical strength, and superior thermal shock resistance.
To address these requirements, Active Metal Brazing (AMB) technology has been widely adopted in the production of ceramic/metal composite substrates. In AMB substrates, copper (Cu) is bonded directly to the ceramic through a brazing layer containing active elements such as titanium (Ti), forming a reliable structure with integrated electrical and thermal conductivity. Tong Hsing Electronics, a leading manufacturer of advanced ceramic substrates in Taiwan, has been actively developing Si₃N₄-based AMB substrates to support the next generation of high-reliability power modules, particularly those utilizing WBG semiconductors. Module makers are looking for higher power density, however, higher power density always comes with the challenge in circuit design. To push the limit of the substrate, a series of electrical studies were performed in this paper.
In practical module design, trench structures are often incorporated on AMB substrates for electrical routing. However, the trench geometry (including opening width, depth, and spacing) has a significant influence on the local electric field distribution and overall dielectric performance. Improper trench design can lead to field crowding, partial discharge, and premature insulation breakdown, which severely impact system reliability.
This study presents a systematic investigation into the electrical reliability of Si₃N₄ AMB substrates with varying trench opening configurations. Multiple test samples with different trench geometries were fabricated using standard AMB processes and subjected to insulation resistance and dielectric withstand voltage testing under simulated operating conditions. The experimental analysis aims to clarify the correlation between geometric design and electrical insulation behavior, providing valuable insights for future optimization of substrates used in high-density, high-efficiency power module applications.

 

Bio:
I am the leader of the Research Group at RIMTEC Corporation, a member of the Zeon Group. My research focuses on hydrocarbon-based thermosetting resins for electrical insulation, aiming to improve their performance and reliability in industrial and electronic applications. I received my Bachelor of Engineering degree from Kobe University in 2002, and since then, I have been dedicated to exploring innovative solutions in resin technology.

Abstract:
Dicyclopentadiene (DCP) resin can control elasticity and is a thermosetting resin with low viscosity, low moisture absorption, and excellent electrical properties. In power cycle tests using power modules equipped with SiC-MOSFETs, outstanding results have been reported compared to silicone gel sealing materials. In recent years, power modules are expected to be used in various harsh environments, with durability in high-temperature and high-humidity conditions being a significant challenge. This report focuses on the low moisture absorption of dicyclopentadiene resin and presents the results of power cycle tests conducted after exposure to high-temperature and high-humidity environments, comparing it with other sealing resins.
As encapsulation resins, a developed DCPD resin, silicone gel, and epoxy were used. Power modules sealed with these resins were exposed to an environment of 85 °C and 85% relative humidity. After a specified exposure period, power cycling tests were conducted.
The developed DCP resin exhibited approximately twice the power cycle lifetime after exposure, whereas the silicone gel and epoxy encapsulated samples showed significantly reduced lifetimes compared to their pre-exposure performance. This difference is considered to be due to moisture absorption by the silicone gel and epoxy resins, while the DCPD resin remained unaffected by moisture.

 

Bio:

Joon Sang Kang is an assistant professor in the Department of Mechanical Engineering at KAIST. He received his B.S. in Mechanical Engineering from Inha University, followed by an M.S. from KAIST and a Ph.D. from the University of California, Los Angeles (UCLA). His research focuses on the development of high thermal conductivity materials, thermal management in electronic devices, and thermal characterization for advanced electronic packaging technologies. He has published papers in prestigious journals, including Science, Nature Electronics, Advanced Materials, and Nano Letters.

Abstract:

  Thermal management in electronics is increasingly critical for enhancing computing power and reducing device power density. Recently discovered cubic boron arsenide (BAs) exhibits ultrahigh thermal conductivity (1500 W/mK), holding promise for heat spreading and packaging applications. However, integrating BAs as a heat spreading layer for transistors necessitates device integration and heterostructure fabrication.
  In this talk, heterostructure devices combining various materials with BAs were fabricated using an e-beam evaporator and plasma bonding technique. The cooling performance and hot spot temperature of each device were evaluated using ultrafast pump-probe methods and Raman spectroscopy. Our findings indicate efficient interfacial energy transport between different materials and BAs, resulting in a significant reduction in transistor temperature.
  Comparative analysis with conventional heat spreading materials like SiC and diamond reveals that BAs heterostructures exhibit minimal temperature rise during transistor operation. These results position BAs as the most promising material for thermal management in semiconductor devices.

 

Bio:

  Tae-Ik Lee is a principal researcher in the Advanced Packaging Integration Center (APIC) of Korea Institute of Industrial Technology (KITECH). He received his B.S., M.S., and PhD, in Mechanical Engineering from KAIST. His research focuses on understanding thermo-mechanical properties of micro/nano systems seeking for bonding & reliability solutions for advanced electronic devices. Major applications include semiconductor packages and displays. He has published 44 journal papers with (>1700 citations, 19 h-index).

Abstract:

As semiconductor packaging advances toward miniaturization and high integration, thermo-mechanical reliability has become increasingly critical due to heat generation from high-performance devices. The complex physical properties and limited knowledge of mechanical stability at heterogeneous interfaces necessitate precise analysis of thermal stresses and deformations. To improve reliability, understanding the actual mechanical behavior under thermal conditions during packaging and operation is essential. Utilizing micro-scale digital image correlation (DIC) enables detailed visualization and quantification of surface deformations. This presentation showcases micro-2D-DIC techniques for local deformation analysis of packaging interconnects, including solder joints and epoxy-bonded interfaces. The findings demonstrate that early detection of thermo-mechanical failures is possible through these measurements. Additionally, thermomechanical properties such as the coefficient of thermal expansion and glass transition temperature are measured using 3D-DIC. Combining these insights enhances understanding of material behaviors and stress-related deformations in real operating environments, offering strategies to mitigate warpage issues in next-generation semiconductor packages.

 

Bio:

  Hanwool Yeon is an assistant professor in the Department of Materials Science and Engineering (MSE) at GIST. He received his B.S. (2009) and Ph.D. (2016) degrees in MSE from Seoul National University. He then conducted postdoctoral research for 4.5 years under Prof. Jeehwan Kim at the Massachusetts Institute of Technology. In 2022, he joined GIST as a faculty member. His research aims to realize energy-efficient and reliable edge Ai hardware through innovative back-end-of-line (BEOL) metallization technologies. Specifically, his group focuses on (1) BEOL-embedded devices, (2) BEOL conductors, and (3) advanced packages beyond the BEOL.

Abstract:

  Advanced packaging (AVP)‒the compact integration of disaggregated chips without long wires and with bondable interconnects-has become an indispensable technology in the artificial intelligence (Ai) era. AVP forms short and dense interconnections between memory and processors, facilitating fast and energy-efficient edge Ai computing. However, AVP-based compact Ai hardware faces crucial reliability challenges, including (1) poor heat dissipation, (2) copper (Cu) contamination, and (3) electromagnetic interference (EMI) in integrated chips. Addressing these challenges requires innovative advancements in AVP materials. In this talk, I will present my group’s efforts to develop highly reliable Ai hardware by establishing novel metallization strategies, enabling the discovery of synergistic material combinations with metals. First, for organic interposers, we have developed Cu metallization technologies with self-assembled monolayers (SAMs) to enhance reliability under thermal and electrical stress. Second, for EMI shielding, we have demonstrated ultrathin metal-MXene hybrid shields that achieve unprecedented high performance and provide compact chip passivation. I will elaborate on the underlying mechanisms of our metallization technologies, referred to as SMART metallization.

 

Bio:

  Seung-Kyun Kang is an associate professor in the Department of Materials Science and Engineering at Seoul National University (SNU) and Head of the Materials Analysis Center at the Research Institute of Advanced Materials. He earned his BS (2006) and PhD degrees (2012) from SNU, specializing in mechanical properties of multiscale materials. He conducted postdoctoral research on bioelectronics under Prof. John A. Rogers at the University of Illinois at Urbana-Champaign (UIUC) and Northwestern University. Before joining SNU in 2019, he was an assistant professor at the Korea Advanced Institute of Science and Technology (KAIST). Kang has published over 80 peer-reviewed papers in Nature, Science Advances, and Advanced Materials. His research spans materials science, electronics, mechanics and bioengineering, focusing on wearable, implantable and bioresorbable medical devices, neuromorphic devices and soft robotics. Beyond applications, he investigates mechanical failure analysis, corrosion, degradation and mechanical testing of advanced materials.

Abstract:

     The era of flexible and stretchable electronics has drawn significantly closer with the commercialization of foldable and flexible devices such as flip and foldable phones, intensifying global technological competition. The ultimate vision for next-generation systems is to achieve ultra-thin, lightweight formats that approximate epidermal-level electronics, and further, to advance toward miniaturized devices capable of implantation within the human body. Such progress requires moving beyond single-element devices or simple wiring toward the integration of heterogeneous soft and hard components, accompanied by new packaging strategies tailored to novel form factors to ensure long-term mechanical reliability. This presentation will provide an overview of packaging technologies for ultra-soft and flexible electronics, addressing critical aspects across design, testing, and system integration. In particular, I will discuss interconnection and wiring technologies that simultaneously sustain flexibility and electrical conductivity, as well as three-dimensional structural design strategies that mitigate stress concentration during deformation. As the overall thickness of devices continues to decrease, encapsulation approaches become increasingly critical—not only to ensure environmental stability and biocompatibility but also to preserve functionality over long-term operation. Recent advances in barrier layer technologies and thin-film encapsulation will also be highlighted as essential enablers for robust, skin-like and implantable electronic systems. By examining these advances from the perspective of packaging and encapsulation, this talk will explore both the challenges and the emerging opportunities in realizing the next generation of flexible, stretchable, and implantable electronics.

 

Bio:

  Eun-Ho Lee is currently an Associate Professor with the School of Mechanical Engineering at Sungkyunkwan University, Korea. He worked at the Manufacturing Lab of General Motors R&D (Warren, MI) and the Package Team at Samsung Electronics before joining Sungkyunkwan University. His research interests include intelligent manufacturing, semiconductor/packaging manufacturing, and reliability.

Abstract:

  This presentation explores how grain orientation and grain size affect Cu-Cu bonding interface behavior. Using crystal plasticity theory and ABAQUS simulations, we modeled copper's microstructure, including its FCC structure, slip systems, and diffusional creep driven by pressure gradients. Simulations showed that grain orientation significantly impacts bonding interface deformation and shape change, with different orientations dominating during bonding formation versus grain growth. This complexity suggests advantages for random grain structures. We also found that fine grains store more free energy and can reduce the grain orientation effect. All simulation results were experimentally validated.

 

Bio:

Hirokazu Ito received the M.S. degrees in applied chemistry from Hokkaido University, and joined JSR Corporation in 2008. He also worked in 3D Systems Packaging Research Center in Georgia Tech as a Visiting Researcher from 2017 for two years. He has engaged in development of photo imageable dielectrics and photoresist.

Abstract:

In this session, we mainly discuss photosensitive polyimide material required for re-distribution layers (RDLs) in next generation interposer. As increase the demand of high-density interconnect on interposer, stable process of fine pitch Cu traces less than 2µm-L/S is a key technology. However large topology which comes from large polyimide shrinkage through curing causes some technical issues on photoresist lithography for plating. In addition, CTE mismatch between polyimide and Cu is a potential reliability concern especially in larger packaging. Therefore, retaining low CTE at high temperature, namely high Tg, becomes important. From these prospective, JSR newly developed photosensitive polyimide enabling high resolution with an aspect ratio of 2.0 or more, low shrinkage around 10%, low CTE and high Tg simultaneously. We also demonstrated reliability performance including the biased-HAST by multi-layer stacking structure with 2 µm-L/S Cu traces. These unique properties and reliability data indicate that the newly developed photosensitive polyimide is a promising material for RDLs in next generation interposer. We also touch on the topics of fine pitch patterning photoresist for plating.

 

Bio:

Shaw Fong currently serves as the Principal Engineer at one of the Kulim Campuses of Intel Malaysia. With ~24 years of extensive experience in the semiconductor industry, he has held various positions that encompass a wide range of technical domains including packaging processes, assembly, testing, and material technology development. Throughout his career, Shaw Fong has played a pivotal role in advancing multiple packaging and product development initiatives, with a particular focus on warpage development and mechanical testing. His technical acumen and leadership have significantly contributed to innovative solutions and improved efficiencies within these critical areas.

In 2023, Shaw Fong was honored with the prestigious IEEE/EPS William Chen Distinguished Award, recognizing his significant contributions to the IEEE in driving advancement in semiconductor assembly and testing field. He has been nominated to the IEEE/EPS Board of Governance and serves as Region-10 Program Director. He is also engaging in IEEE Malaysia Section as the Executive Committee (Industrial Relations). Additionally, he is an active Committee Member of both the Electronic Engineering Technical Division (eETD) and the Material Engineering Technical Division (MaTD) of the Institution of Engineers Malaysia (IEM). His recent designation as a Professional Engineer by the Malaysia Board of Engineers (BEM), along with his advisory roles with various local universities, underscores his unwavering commitment to engineering excellence and education. Shaw Fong holds a total of 12 combined patents and trade secrets, and he is a key driver of technical innovation at Intel Malaysia, having achieved over 90 technical publications. Outside of his professional endeavors, Shaw Fong is a devoted family man with two sons and a passionate sports enthusiast, particularly in football, where he proudly supports Liverpool FC.

Abstract:

The IEEE Electronics Packaging Society (EPS) plays a pivotal role in advancing microelectronics and packaging technologies globally. This session aims to introduce the IMPACT community to the mission, structure, and strategic initiatives of IEEE EPS, with a focus on Region-10 (Asia-Pacific). As the semiconductor industry shifts toward heterogeneous integration and system-level innovation, EPS offers a robust platform for collaboration, knowledge dissemination, and professional development.
At the heart of EPS’s technical leadership is the Heterogeneous Integration Roadmap (HIR), a 15-year vision co-developed with global stakeholders to guide the integration of logic, memory, photonics, and sensors into high-performance systems [1]. This roadmap is not only a technical compass but also a catalyst for regional innovation and policy alignment. Region-10 chapters—including Taiwan, Japan, India, and others—are actively contributing to this vision through conferences, workshops, and chapter-led initiatives. The Malaysia EPS Chapter, for example, has expanded its membership base and hosted key events aligned with the EPS and national strategies [2]. EPS-sponsored conferences provide platforms for cross-border engagement and technical exchange [3].
This presentation will also highlight membership trends, 2025-2026 chapters’ activities, and opportunities for Region-10 collaboration. By leveraging EPS’s global resources and regional networks, we can accelerate innovation, strengthen talent pipelines, and shape the future of electronic packaging in Asia.

 

Bio:

Jenn-Ming Song is the Dean of the office of R&D, and a professor in the Department of Materials Science and Engineering, at National Chung Hsing University in Taiwan. He is also a visiting professor of Osaka University in Japan as well. His research interests encompass semiconductor packaging, advanced interconnect materials, synthesis and applications of nanomaterials, phase transformation and mechanical behavior of advanced materials at bulk and small length scales. He is an Editor for the journal Materials Chemistry and Physics, and serves as the member of editorial advisory board of Microelectronics Reliability. Prof. Song has received several excellence research awards, including the Ta-You Wu Memorial Award from National Science Council of Taiwan and the outstanding research professor award from the Lee Chang Yung (LCY) education foundation.

Abstract:

By minimizing interconnect resistance and improving signal transmission efficiency between stacked dies, metal to metal direct bonding addresses key challenges in next-generation semiconductor systems, such as power delivery, data bandwidth, and form factor reduction. In addition to thermal compression, ultrasonic technique has been suggested to achieve bonding between Au, Al, Cu and In, due to the advantages of short processing time, and the elimination of the need for vacuum and additional intermediate materials, such as solders or adhesives. An innovative and efficient surface modification pre-treatment that enhances direct metal bonding through electromagnetic irradiation, including pulsed Xenon flash, near infrared rays and short wavelength UV lights, has been proposed by our research group. Without vacuum, short period but critical electromagnetic radiation exposure on faying faces prior to bonding can significantly improve the joint strength up to 50% or even more. In addition to hydrophilic surface ligands, atom diffusion acceleration by increased compressive residual surface stresses resulting from sudden heating/ cooling accounts for the joint reinforcement. A close relationship between the increase in joint strength and the change in surface physics and chemical properties due to electromagnetic irradiations will be reported.

Keywords: Light irradiation, Direct metal bonding, Thermal compression, Ultrasonic bonding, Surface properties

 

Bio:

Chuan Seng Tan is a Professor of Electronic Engineering at the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore. He received his PhD from MIT in 2006. Currently, he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology. He is a Fellow of IEEE (Class of 2022) and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. He was a Distinguished Lecturer with IEEE-EPS from 2019-2023. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019 and a recipient of the William D. Ashman - John A. Wagnon Technical Achievement Award in 2020.

Abstract:

Increasingly, enhancements in system-level performance are being complemented by functional diversification. In this talk, we present our recent work on engineered substrates (X-OI) and advanced packaging techniques—including through-silicon vias (TSVs) and wafer bonding—to advance this dual objective. We will highlight several key demonstrators, such as GaN-LED integration on silicon CMOS, ion-trap architectures on silicon interposers, and our latest proposal involving triple integration of optics, III-V optoelectronics, and silicon technologies.

 

Bio:

Dr. Sam Dharmarathna earned his Ph.D. from the University of Connecticut and is currently a Line of Business Partner for IC Substrate R&D at MacDermid Alpha Electronics Solutions. With a strong background in materials chemistry and electrochemistry, Dr. Dharmarathna specializes in developing innovative metallization solutions for IC substrates, driving advancements in advanced packaging, redistribution layers (RDL), and glass substrate technologies.
As a published author with over 30 technical publications.

Abstract:

Saminda Dharmarathna, Leslie Kim, Peter Chang, Steven Tam, Brian Gokey, Ernie long

The global IC substrate market is experiencing robust growth, projected to expand from USD 15.1 billion in 2024 to USD 37.1 billion by 2033, fueled by the rising demand for advanced semiconductor packaging solutions in artificial intelligence (AI), 5G, and high-performance computing (HPC) applications. As chip dimensions shrink and interconnect densities increase, IC substrates are evolving to incorporate wafer-level precision manufacturing techniques traditionally associated with front-end semiconductor processing. This evolution necessitates plating solutions capable of delivering ultra-fine line and space (L/S) structures, defect-free via filling, and highly planar surfaces — all critical for ensuring multilayer stack integrity and superior electrical performance.

In this study, we present an innovative copper electroplating process specifically tailored for advanced IC substrates, utilizing wafer-level technology principles adapted for substrate manufacturing. The process is optimized for embedded trench fill, simultaneous via fill, and through-hole plating with enhanced pattern plate capability. A bottom-up copper filling mechanism, driven by a finely tuned additive package—including suppressors, accelerators, and levelers—ensures uniform, defect-free filling of microvias and trenches. This approach eliminates common defects such as V-pitting, seam voids, and uneven copper deposits, while removing the need for costly and energy-intensive post-bake treatments.

To enable high-volume production with superior quality, the process is specifically designed for integration into High-Speed Plating (HSP) systems. HSP tools offer rapid throughput, precise current control, and uniform fluid dynamics, making them ideal platforms for advanced substrate electroplating. Leveraging HSP capabilities, the process ensures excellent via fill quality, superior co-planarity across the entire panel, and high mechanical and electrical reliability—critical attributes for AI and HPC applications.

Comparative studies show that the new plating process achieves significantly flatter pattern profiles and improved microvia filling compared to traditional dome-shaped plating outcomes. The resulting copper deposits demonstrate enhanced mechanical strength and elongation, meeting the rigorous demands of next-generation semiconductor packages.

By translating wafer-level precision into high-speed, panel-level manufacturing, this solution sets a new benchmark for IC substrate technology. It provides a scalable, efficient, and reliable pathway to meet the evolving performance and miniaturization requirements driven by the explosive growth of AI and HPC markets.

 

Key words

Artificial Intelligence (AI), Advanced packaging, Modified semi-additive processing (mSAP), IC Substrates, Electroplating, Uniformity.

 

 

Bio:
Michael Lo is PSC’s APAC Applications and Business Development Manager with rich professional experiences ranging from IR/Raman, AFM, material characterization to sample preparation, material synthesis, polymer-drug formulations and business development. Since 2018, he leads the technical market development of the novel submicron IR super-resolution microscope, also known as mIRage and mIRage-LS. In his past roles, he has led the discovery of new applications using tip-based sub-diffraction limited microscopes and resulted in numerous peer-reviewed publications. He has completed and received his doctoral degree in Chemical and Biomolecular Engineering from UCLA.

Abstract:
Improving yields in the manufacturing of microelectronic packages has become a progressively important task but also growing increasingly difficult due to smaller and finer feature sizes. Modern advanced packages consist of multiple functionalities toward system-on-chip (SOC) by incorporating multiple known-good dies, high bandwidth memories, and chiplets in an increasingly small complex 3D or even 3.5D packages. To accommodate small packages, feature sizes of interconnects are pushing toward sub-10 µm regime [1], leading to the smallest contamination could potentially jeopardize the operability of the entire device. Since multiple steps and processes are required to prepare each individual chip component, it becomes financially important to ensure integration through interposers and interconnects to be free of defects.

When defects do occur, these small foreign matters are challenging to identify for root cause analysis. After identifying the specific faults through physical failure analysis (PFA), Fourier-transfer infrared spectroscopy (FT-IR) is typically utilized to molecular fingerprint the unknown. This conventional FT-IR technique detects electromagnetic waves that are typically between 2.5 to 20 µm. The infrared wavelengths employed in the FT-IR microscopes are much too long to effectively resolve those sub-10 µm foreign contamination and particles [2,3]. Certainly, Raman microspectroscopy has been the go-to alternative that can offer spatial resolution for resolving those sub-10 µm organic defects, but the inherently strong fluorescence nature of many resins and chemicals used in the manufacturing of microelectronics shunts the benefits of Raman microspectroscopy.

To overcome the abovementioned challenges, a novel type of infrared-based microscope taking advantage of detecting localized infrared-absorption induced photothermal effects using a visible laser source, namely optical photothermal infrared or O-PTIR [4,5] has been developed to provide high spatial resolution and sensitivity to remedy aforementioned challenges in conventional analytical techniques. This instrumentation simultaneously illuminates a constant wave visible laser and a pulsed wide-tuning laser in the mid-IR. This visible laser is typically equipped at 532 nm, the theoretical spatial resolution of O-PTIR would also be in the submicron regime (<1 µm). The IR laser’s pulse width is a few hundred nanoseconds and repetition rate is about 100 kHz. When the material absorbs the IR wave, the material would heat up, leading to photothermal expansion and an instantaneous change in the refractive index. These phenomena are referred to collectively as photothermal effect, which would bend the constant wave visible laser, leading to the deflection of it relative to when the IR laser is in the off state [Fig. 1]. Since the photothermal effect is due to the IR absorption of the unknown, the resulting infrared spectra reflects its native IR absorption profile, such that we can directly searched and compared with commercially identified infrared databases.

Using this new method, identification of unknown of sub-5 µm contamination can be accomplished. In this contribution, we will briefly explain the fundamentals of submicron IR (O-PTIR) and conclude with an example illustrating the capabilities of O-PTIR toward analyzing contamination in between a sub-5 µm gap between metal leads (Fig. 2) with high signal to noise (Fig. 3), thus leading to confident identification of the unknown material.

 

Bio:
Mr. Ting-Wei Chen is an engineer who works in the NMC department at TSMC, specializing in advanced packaging within the semiconductor industry. Throughout his career, Mr. Chen has demonstrated a strong understanding of the carrier wafer process and has helped develop new processes and technologies that improve carrier wafer process stability and reliability.

Abstract:
ABSTRACT
The rapid progression of advanced packaging technologies is being driven by the growing demands of high-performance computing (HPC) applications. To meet the increasing complexity of HPC workloads, innovative packaging solutions such as 2.5D and 3D integration, chiplet architectures, and heterogeneous integration are being actively explored. However, these advancements introduce significant manufacturing challenges. In 2.5D and 3D packaging, carrier wafers play a critical role in supporting wafers throughout complicated processes including etching, thermal curing, lithography, and grinding. A key function of the carrier wafer is to minimize wafer warpage, ensuring precision in steps such as lithography and grinding.
The material selection of carrier wafer is crucial, requiring properties such as transparency, low surface roughness, and bulk defects-free (like voids or cracks) and chemical resistance. These carrier wafer qualities are essential for reliable performance at temporary bonding and subsequent processing stages. To ensure the quality of carrier wafer, this paper proposes an Advanced Optical Metrology (AOM) to monitor physical properties of carrier wafer, including transmittance, surface roughness, and bulk defects.
The AOM has been successfully validated on 12-inch transparent carrier wafer, providing comprehensive data on transparency, surface morphology, and bulk defects within one minute of measuring time. The validation was further confirmed by cross-checking results with other inspection instruments. The demonstration cases show that AOM offers a fast, reliable, and efficient solution for quality monitoring of carrier wafer, addressing the critical needs of advanced packaging processes in HPC applications.

 

Bio:
Education: 2011 Master of mechanical engineering department, National Chung Hsing University (NCHU), Taiwan. Experience: Over 14 years of job experience on semiconductor industry, especially focus on flip chip, Package on package (PoP), SiP (System in Package), CoWoS and Fan-out solutions of advanced assembly technology for mobile computing, IoT and networking market application. Mike is focus on new assembly package & new technology development. He has been exploring the product application strategy, package technology promotion, new project engagement.

Abstract:
Major semiconductor market applications require HPC, Cloud, Autonomous Car and Generative AI to get better daily life. When large scale expansion requirement from each application, we will receive a large amount of data which will be generated in the computing process by efficiently transmitted, calculated and stored. In recent years, the demand for data transmission in large data centers and cloud servers. Industrial networking countries have been driving into the optical communication field, by using "optical light" instead of "electrical" as the carrier during data transmission. The major benefits for optical communications can improve the transmission capacity, bandwidth, power efficiency to increase data bandwidth and reduce electricity energy consumption. However, the current networking server are using the traditional pluggable transceiver method, but power consumption is a major concern. Therefore, in order to overcome these challenges and achieve higher bandwidth and faster data processing needs, a "Co-packaged Optical" (CPO) packaging solution was developed to improve power and better bandwidth. The CPO product combined EIC (Electronic Integrated Circuit) and PIC (Photonic Integrated Circuit) with optical waveguides design into OE (Optical Engine) module and integrated switch chips and multiple OE modules into single package integration. In this paper, we see different OE structures (EIC/PIC) by horizontal and vertical integration methodologies, and use fan-out embedded with RDL, 3D TSV die stacking and hybrid bonding technologies to integrate EIC/PIC function into OE module. The FAU (fiber array unit) will use optical passive/active alignment method to put on waveguide area of PIC with grating coupling (GC) and edge coupling (EC) solutions. Both of electrical performance and thermal performance are major challenges for OE solutions. Compared with electrical performance by insertion loss and verify die thickness of thermal performance simulation. We also demonstrated the Fan-out CPO (FO-CPO) structure warpage challenge and assembly solutions during wafer level bonding and package level bonding to get better warpage control result. Finally, this paper will provide the advanced CPO and OE technology solutions for the next generation networking and HPC markets.

 

Bio:
Darko Grujicic, Ph.D. is a Principal Engineer at Intel's Advanced Packaging Technology Manufacturing organization. He received his bachelors degree from the University of Belgrade and his Ph.D. in Materials Science and Engineering from the University of Idaho. For the last twelve years at Intel, he has been working on development and manufacturing of advanced packaging solutions, including EMIB, EMIB-T and glass core and carrier packaging solutions, responsible for seed deposition and etch. He holds 10 awarded patents, and numerous peer-reviewed journal publications.

Abstract:
This paper presents the study of chemical copper seed etching in panel-level substrate packaging application for redistribution layers, utilizing equipment with the novel fluid reactor design. The main challenge in removing the copper seed for fine-line spacing redistribution layer interconnects is preserving the dimensions of the interconnects, while ensuring complete removal of the seed copper to prevent shorting between the interconnects. This prompted the need for a novel reactor design that can meet these requirements for fine-line interconnects with the width of 2um and below. Components of the reactor were designed by applying Computational Fluid Dynamics (CFD) modeling. These concepts comprise modelling of two-phase flow combined with the Discrete Phase Model (DPM) method and fluid film development on the panel surface to simulate solution flow on the panel surface. Additional control of the etch process is enabled by implementing the end-point detection system, so that the etch process can account for the incoming seed thickness variation and adjust the etch duration appropriately. The platform has flexibility to incorporate different chemical modules, incorporating titanium etch module for sputtered seed application. The platform, with some modifications, can be extended to other wet processes in the semiconductor packaging (e.g. photoresist develop and strip, bulk Cu etch, photoresist stripping using solvents, etc…) making it a universal platform with many potential uses.
The results in this paper demonstrate the capability of the reactor to remove copper seed between the copper electrical traces, without affecting the trace profile by over-etching the traces, using commercially available copper etch chemistry. The traces, defined by optical lithography in photoresist are biased to 2.4 um, and electrolytically plated on a 250 nm copper seed to a 3um thickness. Profilometry measurements and cross-sectional SEM images post etch indicate that the top and sides of the trace are etched at the same rate as the seed, resulting in a 2 um wide trace with a uniform rectangular profile.

 

Bio:
will be updated later

Abstract:
Heterogeneous integration enhances functional density by incorporating multiple chips or components into a single package. This integration increases the overall package size, posing challenges for dimensional stability. A promising solution is the use of new materials like glass, which offers exceptional flatness and dimensional stability. Achieving inclusion-free filling of high aspect ratio (HAR) through glass vias (TGVs) is crucial for improving the performance and reliability of advanced electronic packaging.
This study investigates the application of pulse reverse electroplating (PRE) to achieve defect-free copper electroplating in HAR TGVs. Defect-free filling of HAR TGVs is essential for the performance and longevity of advanced electronic devices. The PRE technique, which employs alternating current pulses combined with advanced DC electroplating processes, theoretically prevents the formation of inclusions and voids, ensuring excellent bridging and superconformal filling even in challenging structures.
Our findings suggest that the PRE method can provide inclusion-free filling for specific through-hole dimensions, as supported by theoretical ideas and plating examples. Additionally, our recent investigations support the theory of an influence of cuprous ions on the TGV filling mechanism, which could further optimize the electroplating process. Cuprous ions play a significant role in the electrochemical reactions occurring during the PRE process, impacting the deposition quality and uniformity. Understanding this influence allows for better control over the electroplating parameters, leading to improved filling results.
Another filling mechanism, previously published by our group [1], is also considered. This mechanism is based on the differential de- and re-adsorption of various additives at specific phases of the pulse scheme. These additives interact with the copper surface during the electroplating process, affecting the behavior and distribution within the TGVs. By carefully managing the adsorption and desorption cycles, it is possible to achieve more uniform and defect-free filling, enhancing the overall performance and reliability of the electronic packaging.
The theoretical data highlights PRE's potential to enhance structural integrity and improve thermal and electrical conductivity. The inclusion-free filling achieved through PRE not only improves the mechanical stability of the package but also enhances its thermal management capabilities, which are critical for high-performance electronic devices. The improved electrical conductivity ensures efficient signal transmission, reducing losses and enhancing the overall functionality of the device.
Future research will focus on refining these processes to accommodate diverse structure dimensions, further enhancing their reliability and versatility. By refining the techniques and exploring new combinations of electroplating methods, including testing new in-house synthesized molecules with tailored electrochemical performance, we aim to further enhance the versatility and reliability of HAR TGV filling processes to meet the evolving demands of advanced electronic packaging. These efforts will contribute to the development of more robust and efficient packaging solutions, capable of supporting the next generation of electronic devices.

 

Bio:
Ling-Hua Wang Worked at Advanced Semiconductor Engineering, Inc., Kaohsiung, Taiwan six years as Supervisor Participated PLCSP, FO/ FX, FOMCM, FOCoS-B device research and development Responsible Molding process including EQP and materials research and development Concurrently Recon team integrated

Abstract:
The packaging purpose of semiconductor is in order to protect chip and transfer electronic single. In packaging fan-out process, the size are 8 inch, 12 inch wafer and 600x600mm panel, more to achieve the 700x700mm panel which is as the large-Size. They are produced with the more hardly and challenge in the process. Large panel FO development is advance assembly technology. It’s a High-end Technical and also a Aggressive Cost Model in the OSAT (Outsourced Semiconductor Assembly and Test). Mold EMC filling methodology different between Wafer level and Panel level. The Incomplete molding filling improved is requirement on large panel molding. Molding filling is on large panel molding size. EMC background (1) : for hollow filler issue improved Filler size is changed. Filler size: 55um to 20um. EMC background (2) : for hollow filler issue improved. Spiral flow property difference. Spiral flow: 102cm to 88cm. Incomplete fill exist due to lower spiral flow

 

Bio:
Weiming Cheng is a Senior Manager of Business Development at MKS|ESI, leveraging over 23 years of expertise in the FPC, PCB/HDI,and IC Substrate markets to integrate New Product Introduction (NPI) with strategic market expansion. During his 15-year tenure at Unimicron, he demonstrated comprehensive R&D, strategic marketing, process and production capabilities, notably scaling facilities for volume readiness across advanced packaging substrate platforms (CSP, FCCSP, FCBGA). In PCB segment, he led new market penetration into high-growth applications like SiP, Automotive, and mSAP-HDI. Mr. Cheng holds 45 granted PCB/HDI and IC substrate patents and possesses dual Master's degrees in Engineering and Management.

Abstract:
Technological advancements in the integrated circuit (IC) package market, driven by the proliferation of mobile devices and artificial intelligence (AI) servers, have led to several key trends. These include increasing design complexities and package dimensions, heightened routing densities, miniaturized lines and spaces, and a corresponding reduction in the size of laser-drilled microvias. Consequently, the dry film solder resist (SR) materials employed in the outermost layer of these advanced IC package substrates must exhibit exceptional performance reliability. This is crucial for enduring the amplified mechanical stresses arising from coefficient of thermal expansion (CTE) mismatches between various IC package substrate constituents, such as capillary underfill materials, solder, copper (Cu), and interlayer insulation materials, as well as overall substrate warpage in upcoming larger and larger package formats. Furthermore, the continuous increase in routing densities necessitates superior insulation integrity in fine-line and -space configurations and an enhanced capability to stably produce smaller microvias with finer pitches, a demand that has grown significantly year over year.

 

Bio:
Hsin-Lin is a master’s student in the Department of Materials Science and Engineering at National Yang Ming Chiao Tung University. Her research focuses on Ni-doped nanocrystalline copper for low-temperature Cu-Cu bonding in advanced semiconductor packaging.

Abstract:
The semiconductor industry is rapidly advancing toward fine-pitch interconnects and integration of chips through 3D stacking technologies, such as through silicon vias (TSVs) and hybrid bonding. These approaches enable higher performance, reduced latency, and compact form factors critical for AI accelerators, high-bandwidth memory (HBM), and other high-growth applications. Achieving bonding at low temperature has become a critical requirement, particularly for copper-to-copper (Cu–Cu) bonding. Conventional Cu–Cu bonding processes typically demand high temperatures (≥300 °C) to enable sufficient atomic diffusion and grain growth across interfaces. However, such elevated temperatures can damage low-k dielectrics and induce warpage, and limit compatibility with backend-of-line (BEOL) processes. To overcome these limitations, this study explores the use of nanocrystalline copper doped with trace amount of nickel as a promising solution for achieving strong interfacial bonding at reduced temperatures.
Nanocrystalline copper, defined by its ultra-fine grain structure (grain size <100 nm), exhibits a high density of grain boundaries, which serve as fast diffusion paths. These features enhance atomic mobility and bonding efficacy even under reduced thermal conditions. To further improve bonding performance, trace element doping, specifically with Ni was employed. Ni doping was found to influence grain boundary energy, suppress abnormal grain growth, and enhance the thermal stability of the Cu films.
In this study, Ni-doped nanocrystalline copper films were fabricated by co-electroplating under controlled conditions to ensure favorable grain structures and uniform distribution of dopants. By varying the dopant concentration, we achieved tunable grain size and diffusivity, enabling tailored bonding behavior. Additionally, we annealed the films at 150°C for 2 hours and compared the microstructure before and after to evaluate the thermal stability, which is essential for integration into industrial manufacturing flows. Thermal compression bonding was performed at 200 °C for 1 hour in a vacuum environment. The microstructural characterization before and after bonding was carried out using electron backscattered diffraction (EBSD), focused ion beam (FIB), and EDAX OIM analysis to examine grain size, orientation and cross-section analysis. Electron probe microanalysis (EPMA) was used to assess Ni dopant distribution and concentration. In addition, shear tests were conducted to determine the mechanical strength and quality of the bonding interfaces.
The results show that Ni addition effectively refines grain size and enhances bonding performance. With increasing Ni content, grain size consistently decreased within the studied range, leading to improved interfacial contact and mechanical strength. Compared to conventional Cu bonding, Ni-doped nanocrystalline copper significantly improved bonding strength and interface integrity, even under low thermal budgets. These findings suggest that Ni-doped nanocrystalline copper is a promising material for next-generation fine-pitch and low-temperature bonding applications in advanced semiconductor packaging.

 

Bio:

Andreas Ostmann, born 1966 in Berlin, studied Physics and received his Ph. D. in Micro System Technologies at the Technical University of Berlin. Since he joined Fraunhofer IZM in 1992, his research focus is on advanced packaging technologies. He is head of the department System Integration and Interconnect Technologies. His research group is involved in the developed of large-area processes for chip embedding, System-in-Package and advanced substrates. Andreas is author of a large number of publications and holds several patents on advanced packaging technologies.

Abstract:

In order to meet the bandwidth, form factor and power management requirements of computing systems for AI applications based on chiplet architectures, high-end packaging is required. Substrates for chiplet systems must overcome a number of challenges. Their connection density must allow the chiplet wiring to continue seamlessly. This necessitates structure widths of just a few µm and minimal electrical losses. Although substrates based on organic cores are a proven technology, they reach their limits with very high connection densities. Glass core substrates can address these geometric challenges and facilitate multiple sub-µm wiring layers in the future.
This presentation will outline some aspects of the process flow for glass core substrates. A study will demonstrate where a transition from organic to glass cores is necessary to achieve the geometric stability required for high densities. Reliability studies on copper-filled through glass vias (TGVs) will also be presented.

 

Bio:
Masaya Ukita was born in Kyoto, Japan, in 1990. He received the ph.D. degree in Engeneering from Nagoya University, Aichi, Japan in 2019. He is curently the Assistant Research Engineer of the Reliability Group, ROHM Company Ltd, Kyoto. His current research interest is the reliability of semiconductor packages.

Abstract:
Please refer to the attached PDF file. The PDF file totally follows IMPACT's guideline for submission.

 

Bio:
Hsueh-Chih Liu received his bachelor's degree in Mechanical Engineering from Yuan Ze University and went on to complete master's degree in Mechatronics and Mechanical Engineering at National Sun Yat-sen University. He has professional experience as a research and development engineer at TECO Electric & Machinery Co., Ltd. and China Motor Corporation. Currently, he is pursuing Ph.D. at the Advanced Institute of Manufacturing with High-tech innovation (AIM-HI) in National Chung Cheng University, with a research focus on probe testing in advanced electronic packaging.

Abstract:
Currently, the development of semiconductor chip packaging continuously shrinks to light weight and high integration density structure. Meanwhile, the structural dimensions of interconnect system in advanced electronic packaging also being smaller and smaller; therefore, the mechanical response induced by probing test and its influence on interconnect system must be studied. In this study, the numerical and experimental approach are performed to analyze the probing mark formation of aluminum (Al) pad on silicon (Si) wafer. The test vehicle of 6-inch Si wafer with PVD Al coating is shown in Fig. 1(a), the thicknesses of PVD Al coating and Si wafer are estimated as 1.4 μm and 675 μm, respectively. The 10 × 10 mm2 micro chips were diced from Si wafer for subsequent single probing test with Cobra-type needle.

To explore and understand the contact phenomenon and mechanical response of Cobra-type probe needle and Al pad, a finite element method (FEM) modeling was demonstrated with the Cobra probe needle and representative domain of Si wafer with PVD Al coating, the domain area and thickness of Al pad/Si wafer bi-layer system were defined as 0.04 × 0.04 mm2 and 10 μm, respectively. The Cobra probe needle and Si wafer are assumed as linear elastic material with Young’s modulus of 123 GPa and 130 GPa, respectively; and the Al pad is considered as elasto-plastic material to study the probing mark formation behavior, the Young’s modulus and yielding stress are separately considered as 69 GPa and 39 MPa.

The single probing test is accomplished by a customized fixture and MTS Acumen eletrodynamic test system, the test speed is set as 0.5 μm /sec to applied the external overdrive (OD) displacement similar to the actual wafer probing test approach. As shown in Fig. 3, a simulated probing mark with side pile-up along scratch direction is formed on Al pad under applied OD displacement, which is highly comparable to the experimental measured surface profile by AFM (Referred to Fig. 4). The relationship of contact force and external applied OD are illustrated in Fig. 5, which the contact force gradually increased from ~0.02 N to ~0.047 N and revealed the stable contact during single probing test. The demonstrated approach combined numerical and experimental methods are benefit to systemically investigate the probing mark formation phenomenon during wafer probing test with different probe needle geometries.

Fig. 1(a) 6-inch Si wafer with PVD Al coating; (b) Detailed dimensions of Si wafer and Al pad.

Fig. 2 FEM modeling of Cobra probe needle and Al pad/Si wafer structure.

Fig. 3 Simulated displacement contour on surface of Al pad.

Fig. 4 Topography of probing mark on Al pad.

Fig. 5 Contact force estimation during probing test with different OD consideration.

 

Bio:
Shang Yi Lim is currently pursuing an Engineering Doctorate (EngD) in Electrical Engineering at the National University of Singapore, where he works closely with both academic and industry partners to advance semiconductor failure analysis methodologies. His research focuses on the integration of artificial intelligence and machine learning in failure analysis, with an emphasis on physics-guided approaches for defect localization. With seven years of experience in silicon die failure analysis at AMD, Shang Yi has played a key role in developing advanced sample preparation workflows and interconnect defect detection strategies for cutting-edge packaging technologies and advanced technology nodes.

Abstract:
3D integrated circuits (3D ICs), realized through chip stacking (3D packaging) or device-layer stacking (3D monolithic integration), represent a significant leap beyond conventional planar architectures by enabling dense and heterogeneous integration. When combined with other heterogeneous system designs, these advanced packaging technologies offer substantial benefits in terms of modularity, signal integrity, mixed-signal co-integration, cost reduction, and footprint minimization. However, as integration density increases, the complexity of failure modes escalates, introducing critical challenges in yield, diagnostic turnaround time, and long-term reliability. While machine learning (ML) techniques, particularly neural networks (NNs), have been proposed to automate defect detection and prediction, their utility in high-reliability domains remains limited by their “black-box” nature, poor generalizability across evolving failure modes, and a lack of physical interpretability. To address these limitations, we propose a physics-informed modular stochastic framework based on Markov Chain Monte Carlo (MCMC) methods to learn and guide failure analysis with relevant physics progressively. Due to the inherent rarity of defective samples and the data requirement of machine learning models, we first construct a well-calibrated TCAD digital twin based on transistor and interconnect physics. The physics-guided digital twin model generates data on command and provides a holistic understanding of the 12 extracted data features from the electrical characterisation of defects across the interconnect and chip layers. Some key data features include the maximum and minimum node currents, as well as signal delay metrics, which are closely correlated with defect-induced parasitic resistance and capacitance. Finally, the MCMC models are trained to estimate the probabilistic distributions of physical features, enabling traceable and interpretable predictions that connect the most indicative feature sets to their underlying defect mechanisms. This not only facilitates informed physical diagnostics but also provides greater transparency into model decisions critical for failure analysis. The final trained model achieves 96.0% accuracy in predicting faulty signal paths and 75.7% accuracy in localizing specific faults within interconnect structures when applied to advanced CMOS inverter stack test structures. Furthermore, the modular architecture supports continual learning, allowing the seamless integration of new defect data without full model retraining. With the sequential introduction of defect class, defect localization accuracy and signal fault prediction increase steadily from 9% to 75.7% and 32% to 96% respectively. This adaptability suits the evolving nature of semiconductor manufacturing, where new failure signatures continually emerge. By combining physics-based modeling with probabilistic machine learning, our approach offers a scalable, explainable solution for next-generation failure diagnostics and reliability engineering in advanced heterogeneous packaging enhancing both the efficiency and confidence of fault localization for future system-in-package designs.

 

Bio:
Ming-Yi Tsai received the B.S. degree in civil engineering from the National Cheng Kung University, Taiwan, in 1982, and the M.S. and Ph. D. degrees in engineering science and mechanics from the Virginia Polytechnic Institute and State University (Virginia Tech), USA, in 1988 and 1990, respectively. Currently, he is a professor at the Department of Mechanical Engineering, Chang Gung University, Taiwan. He has published more than 150 technical papers in journals and conferences. He serves as an associate editor of J. Electronic Packaging, ASME, and J. of Mechanics for international journal paper publications. His research of interest is in electronic/optoelectronic packaging, photomechanics, adhesive bonding, and mechanics of composite materials. He was the president of IMAPS-Taiwan from 2018-2021 and is also a member of IEEE, ASME, and IMAPS

Abstract:
The three-dimensional integrated circuits (3DIC), stacked-die, or wearable electronics packages gain increasing popularity in subsystem or system packaging applications for satisfying the requirements of small size, low-profile features, high-pin count, high performance, low power consumption, or flexibility. In such applications, the silicon wafers of integrated circuits (IC) need to be thinned to their target thicknesses, typically in the range of 10 μm to 150 μm. The strengths of the silicon die cut from the wafers must be characterized after wafer thinning and sawing processes to fulfill the package design requirements in order to ensure short-term manufacturing yield and long-term reliability. The ring-on-ring test (RoR) is one of the standard tests for biaxial bending, suggested in ASTM C1499-19 and ISO 17167. This test has been widely applied to determine the biaxial bending strength of silicon dies to avoid the die edge effect of the four-point bending tests. However, from the literature, when the relatively thin silicon dies are tested, this test suffers from a geometric nonlinearity effect and thus results in overestimated maximum stress calculated simply by the theoretical solution. This study aims to investigate the mechanics issue in the RoR test experimentally, theoretically, and numerically by considering the geometric nonlinearity. A 2D-isotropy model of a nonlinear finite element method (NFEM) simulation is utilized and verified by experiments, and a 3D-anisotropy model in terms of deformation (or displacement) and stresses. Based on the 2D-isotropy NFEM solutions, the fitting equations of correction factors to modify the theoretical linear solution are proposed and implemented to determine the bending strength of 10 mm × 10 mm silicon dies with thicknesses ranging from 57 μm to 297μm. It has also been proved that the RoR test using the theory associated with the correction factor fitting equations can be easy to use to successfully determine the biaxial bending strength of the thin silicon dies that frequently failed in the nonlinear range.

 

Bio:
Masaaki Koganemaru was born in Fukuoka, Japan, in 1968. He received a Bachelor of Engineering degree in Nuclear Engineering and a Master of Engineering degree in Science and Engineering from Kyushu University in 1992 and 1994, respectively. He earned a Ph.D. in Mechanical Engineering from Kyoto University in 2008. From 1994, he worked as a researcher at Fukuoka Industrial Technology Center in Kitakyushu, Japan. In 2016, he became an Associate Professor at Kagoshima University. Since 2025, he has been serving as a Professor at Kagoshima University. His research interests include device simulation of strained-silicon MOSFETs and stress or strain measurement in electronic packages.

Abstract:
The demand for miniaturization in electronic packaging continues to grow, driving the development of flip-chip bonding technology capable of high-density implementation. In this flip-chip bonding, direct Cu-Cu bonding technology using Cu pillar bumps without solder has gained attention. This bonding method prevents short circuits caused by bridging between bumps during heating, as the bumps do not melt, making it suitable for fine-pitch applications. Additionally, the low electrical resistance of Cu is another advantage. However, the increased rigidity of the bonded parts raises concerns about increased stress on semiconductor chips and joints, potentially affecting mechanical reliability.
Currently, the behavior and reliability of microstructures such as Cu pillar bumps are mainly evaluated through simulations like the finite element method. It has been pointed out that the mechanical behavior of microstructures can differ significantly from bulk materials due to differences in crystal structure. Therefore, it is essential to ensure the validity of material properties and simulation results by comparing them with experimental results. In other words, to ensure the validity of simulations, it is necessary to measure and evaluate the behavior of Cu pillar bumps (deformation, strain, and stress under load).
In this study, a system and method were developed to measure the deformation and strain of Cu pillar bumps under compressive load, simulating the conditions during mounting (bonding). This test system consists of a CMOS camera for capturing specimen images, a micro-load testing machine with a piezo actuator for applying displacement (load) to the specimen, and a load cell for detecting the load. Digital Image Correlation Method (DICM) was applied to the images of Cu pillar bump specimens obtained by the CMOS camera to measure the displacement distribution (discrete point displacement) within the Cu pillar bumps. The Moving Least Squares Method was then applied to the discrete point displacement distribution to determine the displacement field, which was differentiated to obtain the strain distribution.
In this study, compression tests and strain measurements were conducted on Cu pillar bumps formed on Si chips at a scale of tens of micrometers. The Cu pillar bump specimens were prepared by ion milling to expose the height-direction cross-section of circular bumps as the DICM observation surface. As a result, DICM was applied to the images of Cu pillar bumps during compression tests, and the strain distribution within the Cu pillar bumps was successfully obtained. Finite element method simulations mimicking the compression tests were also conducted and compared with the strain measurement results. The order of strain values was approximately consistent between the two, but differences in strain distribution were observed. One possible reason for this is that the finite element method simulations did not consider the anisotropy of material constants in Cu pillar bumps. Specifically, it is suggested that there is anisotropy in the material constants in the width and height directions of Cu pillar bumps. In the future, experimental data will be increased to verify the validity and reproducibility of the test system and method.

 

Bio:
Chao-Ching (Burt) Ho received his B.S. and M.S. degrees from National Taiwan University, Taipei, Taiwan, R.O.C., in 1995 and 1997, respectively. He earned his Ph.D. in electrical engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 2008. He served as a naval engineer officer from 1997 to 1999. From 1999 to 2003, he worked as an R&D manager at 3DFamily Inc. From 2009 to 2016, Dr. Ho was an Associate Professor in the Department of Mechanical Engineering, National Yunlin University of Science and Technology. He joined National Taipei University of Technology in 2016 as a Professor at the Graduate Institute of Manufacturing Technology and Department of Mechanical Engineering, and he has held the title of Distinguished Professor since 2024. His research interests include industrial AI, in-situ monitoring and inspection, laser drilling and ablation, electrical chemical discharge machining, machine vision, as well as stereo vision. He has served as an academic editor for the Journal of Technology (JOT), Smart Science, British Journal of Applied Science & Technology, Journal Technologies, Journal of Science and Innovation , and as an Associate Editor for the International Journal of Innovative Technology and Education. Additionally, he has been a topic editor for Chemosensors and a board member of the World Journal of Textile Engineering and Technology. He is a member of SME (Society of Manufacturing Engineers, Taipei), SPIE and the International Measurement Confederation (IMEKO) TC10 (Measurement for Diagnostics, Optimization & Control).

Abstract:
With the rapid adoption of Industry 4.0 and smart manufacturing paradigms, production is shifting toward small-batch, highly customized runs, where new products cycle through the line at an ever-increasing pace. Traditional supervised defect inspection methods—which rely on thousands of labeled faulty samples and require retraining a dedicated model for every new board design—impose prohibitive annotation costs and lengthy redeployment timelines. Although unsupervised anomaly detection techniques alleviate the need for negative examples by learning exclusively from defect-free data, they still typically require separate models per product family and often suffer from unstable reconstructions and high false positive rates when confronted with the intricate textures and fine geometries of printed circuit boards (PCBs). In contrast, PCB fabrication workflows inherently provide precise CAD design files that encode the ideal board layout, and the universe of possible component arrangements—copper traces, solder pads, vias, silkscreen patterns, and substrate backgrounds—is finite and well defined. Leveraging this rich prior, we present a unified anomaly detection framework that trains only once, yet generalizes across multiple PCB product lines without full model retraining. At its core lies a bidirectional generative adversarial network: a “real-to-CAD” branch learns to map photographed PCB images—including those with latent defects—back to their idealized CAD representations, thereby internalizing canonical board structure; a complementary “CAD-to-real” branch synthesizes high-fidelity, defect-free PCB images from CAD inputs, enabling the network to capture the visual characteristics of normal textures under varying lighting and imaging conditions. During training, we augment the non-defect dataset with a synthetic anomaly generation pipeline that simulates broken traces and microscopic scratches. We further stabilize the dual-domain mappings by enforcing cycle consistency constraints and optimizing a structural similarity loss that emphasizes high-frequency detail retention. These design choices ensure that, in the absence of defects, the reconstructed images closely match real inputs—whereas even subtle deviations caused by manufacturing errors manifest as pronounced reconstruction-error residuals. At inference time, a query PCB image is processed through the real→CAD→real reconstruction cycle, and an anomaly heat map is generated by computing per-pixel reconstruction discrepancies and applying a threshold. Crucially, because the CAD prior comprehensively defines all valid component layouts, extending our framework to a novel PCB design requires only the provision of its CAD file—with no need to retrain the core network. This yields a highly efficient, flexible, and easily deployable solution for industrial anomaly detection. Our approach melds domain-specific prior knowledge with adversarial learning to deliver robust, low-cost quality inspection. It not only dramatically reduces data collection and retraining overhead, but also ensures consistent detection sensitivity across diverse PCB lines—making it ideally suited for any manufacturing setting equipped with CAD resources.

 

Bio:
I studied Chemical Engineering at Ming Chi University of Technology. After graduation, I worked as a Manufacturing Engineer at Unimicron Technology Corporation for about 1.5 years. Seeking to improve my professional knowledge, I left the job and am now studying at National Central University in the Department of Chemical and Materials Engineering. My research focuses on how different solder alloy compositions and solder ball sizes affect the reliability of Ball Grid Array packaging.

Abstract:
As AI chips evolve toward higher I/O density and advanced integration, smaller BGA solder balls are increasingly required to meet the electrical, thermal, and mechanical demands of high-end device applications. This study evaluates the reliability of lead-free solder joints by examining the effects of solder ball size and alloy composition. Each package was assembled with two types of solder pastes: the conventional SAC305 (Sn–3.0Ag–0.5Cu) and a new SABN alloy (Sn–4.0Ag–3.0Bi–0.05Ni). Two BGA package types were used: CTBGA228 with 0.30 mm SAC305 solder balls (SAC305(S)) and CABGA192 with 0.45 mm SAC305 solder balls (SAC305(L)). All solder joint combinations are summarized as SAC305/SAC305(S), SABN/SAC305(S), SAC305/SAC305(L) and SABN/SAC305(L).
All samples were subjected to two reliability tests: drop testing at 1500 G acceleration over a 0.5 ms duration using a half-sine waveform (JESD22-B111A), and thermal cycling from –40 °C to 125 °C with a ramp rate of 15 °C/min and a dwell time of 10 minutes (IPC-9701B). After testing, SEM and EDS were conducted to examine the microstructure and intermetallic compound (IMC) at fracture locations. EBSD investigated the relationship between recrystallization behavior and crack propagation after thermal cycling.
The reliability test results in the table I show that CTBGA228 exhibited earlier failure than CABGA192 during the drop test. In the CTBGA228 package, cracks in the smaller solder balls initiated and remained within the interfacial IMC layer (Fig. 1a). In the CABGA192 package, cracks propagated either along the IMC layer or into the solder bulk (Fig. 1b). The larger solder balls in CABGA192 absorbed more impact energy during the short loading period, which led to cracking at the interface or in the solder bulk.
During the thermal cycling test (TCT), the smaller solder joints in CTBGA228 exhibited a greater number of failure cycles than those in CABGA192. A comparison of crack types observed during TCT revealed different fracture characteristics between the two package types. Recrystallization in the solder balls is associated with stress distribution and relaxation within the joints. In CTBGA228, recrystallization occurred both at the neck region and near the center of the solder joints, whereas in CABGA192, it was observed only at the neck region. These differences in recrystallization behavior influence the lifetime of the solder joints under TCT.
Table I shows that the SABN/SAC305 solder joints exhibit better reliability performance than SAC305/SAC305 solder joints, especially in smaller BGA solder joints. The SABN/SAC305 solder joints tend to form a (Cu,Ni)₆Sn₅ IMC layer with the Cu pad, which enhances the mechanical stability of the interfacial IMC. The higher Ag content in the SABN alloy promoted the formation of larger Ag₃Sn particles in the SABN/SAC305 solder joints. These Ag₃Sn particles enhanced recrystallization, which led to intergranular crack propagation under thermal stress.
This study demonstrates that solder ball size significantly affects reliability. In smaller BGA solder joints, the mechanical properties of the IMC layer, thermal stress distribution, and recrystallization behavior play a more significant role in failure mechanisms. These findings provide valuable insights for optimizing BGA package design and solder alloy selection in high-reliability electronic applications.

 

Bio:
Pin-Jing Su is presently Deputy Manager of material technology department of R&D at Siliconware Precision Industries Co., Ltd. (SPIL) Over 12 years of job experience in semiconductor industry (focus on assembly field) and he is in charge of new advanced material development and management in SPIL currently. He has authored/co-authored 5 papers and 16 patents in the advanced packaging field.

Abstract:
In the booming era of Artificial Intelligence (AI), the high-performance computing (HPC) products focus on the pursuit of processing large amounts of data and fast calculations for efficient training and inference of AI models. Furthermore, the product will be required to enhance the heat dissipation ability to maintain computing efficiency, due to the high-density transistor in chips and the evolution of high-power input design. For the package application, flip chip ball grid array (FCBGA) is the well-known solution that has high IO and fine line width and line space design features. Therefore, the thermal interface material (TIM) selection plays an important role in the performance of high-end products. Currently, there are three major TIM material types including gel type, film type and metal type, which are used in different thermal dissipation requirements. Among them, film and metal types usually used for high heat dissipation products of HPC applications because of high thermal conductivity and low thermal resistance benefits. Thermal resistance is defined as the measurement of heat dissipation capacity of a package. It can involve the thermal characteristics of material bulk and contact interfaces. In the case of solid metal TIM, the lowest thermal resistance is exhibited due to the high isotropic thermal conductivity and high wettability of the contact surface after metal melting and bonding. However, it presents some challenges including high TIM stress and the necessity for additional back side metal (BSM) treatment for the contact surface with TIM material. In the case of liquid metal TIM, it can overcome the high stress and without the necessity for BSM. However, there are existing workability challenges including the design of sealed structures and the necessity for advanced liquid filling technologies. Conversely, the film type of Graphite TIM can be capable of addressing the aforementioned challenges, although its thermal resistance property is still higher than that of metal TIM. Therefore, we are studying a new film type material that is composed of liquid metal and carbon fiber. The melting point of this liquid metal alloy was measured to be approximately 31℃ by DSC. Thus, it is solid phase at room temperature. This composite film type material has the capacity to combine the workability of film type material and the thermal resistance reduction characteristics of metal type material.
The present article focuses on the discussion of material thermal properties and process workability. First, the thermal properties of this novel film material were measured such as thermal conductivity and thermal resistance. All thermal properties are superior to those of conventional Graphite TIM. Secondly, the solutions of high-risk processes were evaluated. These processes included TIM attachment, add the heating stage under the substrate and temperature setting greater than 31℃ that can prevent TIM shift risk in process because of the film material is non-polymer-based and non-adhesive. For HS process, when the TIM size is larger than die size, the liquid metal bleeding risk can be reduced. This is attributable to the extra TIMs around, which serve to enhance the resistance of liquid metal and thereby prevent bleeding out. To conduct a TIM coverage inspection by SAT, it is necessary to utilize a low-frequency probe that can enhance the penetration of ultrasound to get the readable TIM coverage image. In the meantime, the TIM material change of appearance was collected following the reliability conditions. The foaming of liquid metal alloy was found after uHAST condition, which directly influenced the TIM coverage. Therefore, the liquid metal alloy requires adjustment and enhancement in the subsequent stage. In conclusion, although this study did not achieve the expected results, it has provided new inspiration for research in related fields.

 

Bio:

Chi-Chuan Wang is currently a chair professor in the Department of Mechanical Engineering, National Chiao Tung University, Hsinchu, Taiwan. He received his B.S., M.S., and Ph.D. from the Department of Mechanical Engineering of National Chiao Tung University, Hsinchu, Taiwan during 1978-1989. He then joined the Energy and Environment Research Lab., Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan for about twenty years (1989.10-2010.1) conducting researches related to electronic cooling (liquid-cooling, air-cooling, heat pipe technology, immersion cooling, two-phase high-performance cold plate, data center cooling…) enhanced heat transfer, multiphase system, micro-scale heat transfer, membrane separation, and HVAC&R technology. He joined National Yang Ming Chiao Tung University in 2010 as a professor, working on all aspects of thermal energy systems and heat transfer processes. His editorial services include an associate editor Int. J. of heat and mass transfer (3-year term, term starts from Jan. 2025 to Dec. 2027), a regional editor of the Journal of Enhanced Heat Transfer since 1999, an associate editor of Heat Transfer Engineering since 2003, and an editor of Int. J. of Air-conditioning and Refrigeration since 2013. He has been authors or co-authors of more than 450 international journal articles. He is also a co-inventor of 40 Taiwan Invent Patents and 9 US Patents, and authored three books in association with heat exchanger design and heat transfer. He is also an elected Fellow of ASME (American society of mechanical engineers) and ASHRAE (American Society of Heating, Refrigerating and Air-Conditioning Engineers). He was a member of the Assembly of the World Conference (AWC) on Experimental Heat Transfer, Fluid Mechanics, and Thermodynamics (2009-2017) and a member of the scientific council of the International Centre for Heat and Mass Transfer (2017~2024). He is also receipt of the outstanding research award twice (2017, 2020) from Ministry of Science and Technology, Taiwan. Dr. Wang is actively involving the industrialization of novel concepts with more than 20 industrial sponsored projects currently. From miniature heat pipe, thermosiphon, vapor chamber, pulsating heat pipe, air-cooled heat sink, cold plate w/wo phase change, heat sink, smart energy system, chip/package level thermal management, airflow management in datacenter, PCM thermal system, immersion cooling w/wo phase change, heat transfer augmentation technique, HVAC&R, to huge industrial thermal systems. He is now supervising 40 MS/PhD graduate students along with another 8 Post-docs. His group is the most influential research team/think tank of thermal management to bridge the gap between industry and academics in Taiwan. With more than 455 SCI/EI international journal articles, the Google citation exceeds 25500 with h-index 80, and there are 59 papers are cited over a hundred times. He was listed as in the top 2% of scientists in the world rated by Stanford University in 2020~2024 through Scopus’s impact data. According to the World's Top 2% Scientists list, among the approximately ten-million research scholars in the world, according to the data published in October 2024 from Stanford university, he ranked 11,666 and the lifetime scientific impact ranking was ranked 18,219.

Abstract:

This study incorporates a step-gap structure (VCSG) to enhance two-phase heat transfer of vapor chamber (VC). The step-gap is on top of the boss area to facilitate effective pressurization and accelerating of the generated vapor from the heat source, therefore creating better heat spreading performance. Experiments were conducted using water as the working fluid, with heating load spanning from 80 to 560 W, filling ratios from 61% to 155%, and air flow rate between 33 and 110 CFM. Three step-gap configurations, namely VCSG-1, VCSG-2, and VCWSG-1, were evaluated in comparison with a baseline VC without step gap. For VCSG-1 at an air flowrate of 110 CFM, it is found that the thermal resistances are always lower than those of the conventional VC for all filling ratios (FR), and a pronounced drop of thermal resistance is encountered for VCSG-1 when the filling ratio is raised to 110%, and the maximum heating load can be extended to about 410 W.  The VCSG-2 structure incorporates a thicker step gap, and the thermal performance improves progressively as the filling ratio increases, with enhancements up to 50.9%, and the thermal resistance drop to about 0.072 °C/W for a heating load around 350 W. However, a reversed rise of thermal resistance is encountered when the heating load surpasses 400 W due to excessive evaporation of meniscus liquid in the wick and a possible local dry-out. By raising the filling ratio to 86%, the maximum heating load can reach 550 W at the maximum threshold temperature. The heat transfer mechanisms for the step-gap VCs include evaporation and boiling. 

 

Bio:
2011 Ph.D., University of Hamburg, Germany 2011-2017 Postdoctoral Fellow, RIKEN, Japan 2017-2021 Researcher, Nissan Arc, Japan 2021-now CEO and Founder, ANVOS Analytics Co. Ltd., Japan

Abstract:
Galium nitride high-electron-mobility transistors (GaN HEMTs) are critical for high-power and high-frequency applications, but self-heating effects limit their reliability and performance. Traditional thermal characterization techniques struggle to resolve small temperature gradients in-situ. Here, we present the first use of confocal thermoreflectance microscopy coupled with Rayleigh scattering intensity modulation to map self-heating in a GaN HEMT, offering a non-contact, sub-micron spatial resolution alternative to conventional methods.
A custom confocal microscope (adapted from Raman spectroscopy configuration) was employed to monitor thermoreflectance signals. The GaN HEMT was biased under varying source-drain currents (Ids), inducing Joule heating. The Rayleigh scattering intensity (elastic light scattering) was recorded as a proxy for reflectivity changes (ΔR/R), which correlate with temperature-dependent refractive index variations. The system’s spatial resolution (<1 µm) enabled localized thermal monitoring near the device’s active region.

A clear intensity modulation in Rayleigh scattering was observed with increasing Ids, confirming thermoreflectance sensitivity to self-heating. The scattering signal exhibited a reproducible, monotonic dependence on power dissipation, with localized intensity shifts near the gate edge (hotspot formation).
This work establishes confocal Rayleigh scattering as a viable thermoreflectance probe for GaN devices. Together with the calibrated thermoreflectance coefficient, quantitative temperature mapping can be enabled. The technique’s compatibility with standard optical setups simplifies adoption.
Our approach enables in situ, nanoscale thermal profiling of active GaN HEMTs, critical for addressing self-heating bottlenecks in RF and power electronics. Future work will integrate spectral filtering to enhance signal-to-noise and extend the method to other wide-bandgap semiconductors.

 

Bio:
Chun-Kai, Liu received his Ph.D. from the Department of Mechanical Engineering at National Taiwan University. He is currently working as a manager at the Electronics and Optoelectronics Systems Research Institute of the Industrial Technology Research Institute, specializing in electronic cooling, advanced IC packaging, power electronics packaging, and power conversion systems.

Abstract:
The exponential growth of the global data center market, driven by the rapid expansion of cloud computing, artificial intelligence, and high-performance computing, has resulted in significant increases in server thermal design power (TDP). This surge in power density has rendered traditional air-cooling methods insufficient for ensuring thermal reliability and energy efficiency. In response, liquid cooling technologies—particularly cold plate cooling and immersion cooling—have gained prominence. Cold plate cooling offers precise heat extraction at the component level, making it effective for high-TDP CPUs and GPUs, while immersion cooling enables full-system thermal management and significantly reduces cooling-related energy consumption.
In this paper, we investigate a hybrid cooling approach combining single-phase immersion with cold plate systems to optimize thermal performance and system-level efficiency by numerical simulation. Results demonstrate that this integrated solution achieves up to a 30% improvement in cooling efficiency compared to conventional cold plate setups alone, with a notable reduction in hotspot temperatures and thermal resistances. The findings underscore the potential of hybrid liquid cooling systems as a scalable and energy-efficient thermal management solution for next-generation data centers.

 

Bio:
Kenji Ono is currently the Director of Research Institute for Information Technology at Kyushu University, and he also holds an appointment at Kumamoto University. Before that, he worked at RIKEN Advanced Institute for Computational Science, the University of Tokyo and Nissan Motor Company. He received his degrees of Dr. Eng. in mechanical engineering from Kumamoto University, in 2000. His research fields are Computational Fluid Dynamics, parallel computation, visualization and machine learning for large-scale dataset.

Abstract:
This study presents a high-throughput thermal simulation framework to support early-stage IC design, particularly during floor planning when geometry and power profiles are uncertain. The method enables fast, reliable thermal evaluation to guide design decisions in upstream phases. A Julia-based simulator is developed with automated mesh generation and a pseudo-3D modeling strategy that leverages the near-linearity of temperature distribution in the stacking direction. As transistor integration reaches its planar limits, 3D integration is gaining traction. However, vertical stacking increases power density, raising thermal concerns like localized hotspots. Early 3D-IC design requires optimizing thermal TSVs, chiplet placement, and power delivery under incomplete information. While AI and surrogate modeling offer powerful design tools, they demand high-quality training data, which is hard to obtain across vast design spaces. Thus, rapid and accurate thermal simulation is essential for generating representative datasets. The proposed method automates mesh generation using primitive geometric shapes (Fig. 1). Material properties are assigned to voxel cells using predefined priority rules. The steady-state 3D heat conduction equation is discretized and solved via the BiCGstab method, suitable for asymmetric, ill-conditioned matrices from heterogeneous domains. Results on regular voxel grids confirm near-linear temperature profiles in the vertical direction (Fig. 2). It was also observed that automated meshing may alter heat source volume, affecting accuracy.
With a 60×60×30 mesh and a single Intel Core i5 3GHz CPU core, full simulation including meshing completes in 193 seconds. To reduce computation time further, a pseudo-3D approach minimizes vertical cells and relocates heat sources to silicon surface layers. This maintains accuracy while shortening runtime. Such rapid thermal simulations provide a foundation for training AI-based surrogate models and design optimization workflows. Future work includes modeling anisotropic thermal diffusion, TSV-aware cooling strategies, and layout co-optimization in 3D-IC design.

 

Bio:
Po-Hsun He is a Ph.D. student in the Department of Materials Science and Engineering at National Tsing Hua University. His research focuses on electrodeposition and thermal management, particularly in the modification of copper dendritic structures for wick enhancement in vapor chambers. His recent work investigates how electroplated copper wicks influence fluid transport and thermal resistance within vapor chambers.

Abstract:
With the rapid advancement of technology, high-performance computing (HPC), especially in AI training and CPU/GPU processors, has grown increasingly critical. One of the major challenges these components face is the escalating power consumption and heat density, making effective thermal management essential. Inadequate thermal management can lead to component failure, diminished performance, and long-term reliability issues. To address these thermal challenges, vapor chambers integrated into the lid structure offer an effective solution for chip heat dissipation and advanced packaging. These devices operate by circulating a working fluid between the evaporator and condenser: heat input at the evaporator vaporizes the fluid, which then condenses at the condenser to release heat, while capillary-driven wick structures passively return the condensed liquid to the evaporator.
While vapor chambers provide excellent horizontal (in-plane) thermal conductivity due to rapid vapor diffusion, their vertical (through-plane) heat transfer performance is limited by inefficient fluid transport and suboptimal phase-change efficiency. In vapor chambers, vertical thermal resistance is mainly influenced by evaporation and condensation behaviors. Sufficient fluid supply to the evaporator is crucial for efficient heat removal. If the fluid fails to absorb heat, the evaporator may dry out, leading to a loss of heat dissipation capability. Wick structures with high permeability facilitate fluid return to the evaporator, enhancing both fluid vaporization and overall heat dissipation efficiency.
This study investigates a novel hierarchical dendritic copper wick structure fabricated via a two-step electrodeposition process. The electrodeposited wick exhibits a spatial variation in morphology and thickness in radial direction. The gradient-designed structure achieves a high capillary performance (K/Reff) of 0.55 μm using deionized water as a working fluid. It promotes efficient fluid return by mitigating Marangoni resistance arising from temperature-induced surface tension gradients. The enhanced wick design enables superior vertical liquid transport and sustains evaporation at the hot spot, resulting in significantly improved thermal performance. The vapor chamber with the heterogeneous structure demonstrates a very low thermal resistance of 0.065 °C/W under a high heat power of 600 W, and can achieve a maximum heat dissipation capacity up to 750 W.
Our study centers on optimizing the surface morphology and microstructure of the dendritic coatings. By increasing maximum heat flux and minimizing thermal resistance, we position vapor chambers as the ideal thermal solution for next-generation high-power electronic devices. The novel structures and fabrication methods demonstrated in this research represent a significant leap in thermal management technology.

 

Bio:
Yusuf Rahmatullah is a Ph.D. candidate in Mechanical Engineering at the National Taiwan University of Science and Technology (NTUST), specializing in two-phase flow simulation for advanced thermal management systems. His research focuses on developing accurate and efficient numerical models to simulate phase-change heat and mass transfer in vapor chambers and heat pipes. Yusuf’s work emphasizes the implementation of the Lee model, interface tracking, and temperature-dependent Marangoni effects within ANSYS Fluent and custom solvers. He has investigated the impact of interfacial accommodation coefficients, evaporation layer thickness, and gravitational orientation on simulation stability and thermal accuracy. His recent efforts include full-scale modeling of Si-based vapor chambers, incorporating nucleate boiling, dryout behavior, and thin film evaporation to capture detailed thermal-hydraulic dynamics. He holds a diploma in mechanical engineering from Universitas Gadjah Mada and completed his B.S. and M.S. degrees at NTUST, graduating with distinction. His master’s research focused on the design optimization of pillar-reinforced vapor chambers using CFD and ANOVA methods. Yusuf continues to advance the simulation of two-phase systems with the aim of improving the predictive capability and design of next-generation passive cooling technologies.

Abstract:
Vapor chamber is a two-phase-based cooling solution that offers high equivalent thermal conductivity, ideal for high-power electronic devices. However, maximizing vapor chamber thermal-hydraulic performance requires a well-designed sintered powder pillar, including pillar diameter, pitch, and porosity. Because the present of the pillars may hinder the vapor flow, and neglecting these pillar design factors can adversely affect the performance. In design optimization, numerical analysis offers notable advantages over the experimental one in terms of cost and flow/temperature visualization. This paper uses the Lee model-based numerical scheme combined with the analysis of variance (ANOVA) to systematically examine how those pillar design factors affect thermal resistance, temperature uniformity, and total (liquid and vapor) pressure drops. The results revealed that the pillar porosity has the highest contribution to the thermal resistance, followed by the pillar pitch and the pillar diameter. However, the pillar diameter has the highest contribution to the temperature uniformity and total pressure drops. The optimization result suggests that desirability of 0.77 balances all responses for the best overall thermal-hydraulic performance.

 

Bio:
Chris Lin Wistron Corporation / Thermal Engineer 5 years of experience specializing in thermal design and optimization for server products

Abstract:
With the rapid advancement of AI technology, the heat flux and power density of chips continue to rise significantly. In addition to the development of advanced thermal solutions, thermal interface materials (TIMs) play a critical role in effective heat dissipation. Beside the thermal conductivity of TIMs, their ability to maintain stable cooling performance over the device's lifespan is equally crucial. Regardless of how advanced a thermal solution may be, its effectiveness can be greatly compromised without the use of an appropriate TIM. Various factors, including package design, package coplanarity, and warpage behavior, can significantly impact the performance of TIMs in chip cooling. This study aims to identify a TIM that can sustain efficient heat transferability under humidity and temperature cycling conditions while demonstrating strong pump-out resistance under warpage stresses.
This paper compares the performance of various types of TIMs in two different functional package designs: TIM1.5 for ring-type packages and TIM2 for lid-type packages. Time-zero and post-reliability test results are determined using standalone thermal test vehicle (TTV) testing. Junction temperatures of the TTV are measured with a four-wire thermistor, and junction-to-ambient thermal resistance (Rja) is calculated. Additionally, package coplanarity and cold plate flatness are assessed as key influencing factors. By analyzing the collected data, this study seeks to decouple the contributing factors affecting TIM performance and to identify the reasons behind the advantages and limitations of different TIM types.
This study evaluates the thermal performance of phase change materials (PCMs), thermal grease, thermal gel, and thermal pads under time-zero and reliability testing. At time-zero tests, PCMs, thermal grease, and thermal gel exhibit comparable thermal performance, while thermal pad shows approximately 10% lower performance. Under humidity and temperature cycling tests, thermal grease and thermal gel suffer significant degradation in performance, whereas PCMs demonstrate performance stability with variations within 10%, and thermal pads show even lower variation. Considering the current value of chip warpage, PCMs & thermal pads demonstrate strong competitiveness as a TIM due to their reliable performance and durability under stress. These findings provide valuable insights for optimizing thermal interface material selection for advanced chip packaging applications.
A testing platform and process have been established to validate the thermal performance of TIMs under conditions resembling real chip behavior. This platform is expected to serve as a development reference for the thermal design and selection of TIM1.5 and TIM2, providing a basis for evaluating and understanding TIM behavior across varied scenarios.

 

Bio:
Current working as a senior thermal engineer in ASE Group Chung-Li Branch. Responsible for thermal simulation, thermal measurement and package thermal issue solution.

Abstract:
With the continuous advancement of IC technology toward higher performance, slimmer form factors, and greater miniaturization, packaging technologies are facing increasing challenges in thermal management and reliability. Flip chip technology is a critical step in the package process and has a direct impact on bonding quality, reliability and lifetime of package product. The conventional flip chip bonding technique widely adopted in the industry is Mass Reflow (MR). However, due to its heating characteristics, MR can lead to excessive thermal stress and package warpage. Moreover, bonding defects are more likely to occur with fine-pitch and ultra-fine-pitch bumps under the MR process, thereby limiting its applicability for advanced packaging.

Laser Assisted Bonding (LAB) is an emerging flip chip bonding technology. By irradiating the package with a laser, the chip and substrate absorb laser energy and rapidly convert it into heat. The localized heating allows the solder to reach their melting point and bond to the substrate. Since the heat is concentrated in and around the chip region, LAB significantly reduces the overall temperature rise, shortens process time, and minimizes the heat-affected zone—enhancing both the flexibility and reliability of the packaging process. However, the rapid and localized heating may cause uneven temperature distribution. If key parameters such as laser beam size, power, and irradiation time are not properly controlled, issues like cold welding or incomplete bonding may arise. Thus, accurately predicting temperature rise and thermal distribution is essential for successful LAB implementation.

This study employs three-dimensional thermal modeling and transient thermal analysis to simulate the LAB process. The simulation predicts both the overall temperature rise across the package and the temperature rise for specified points. The results are validated against experimental data, confirming that the simulation approach effectively replicates the LAB process. This study not only offers valuable insights into thermal behavior during LAB, but also provides a practical simulation tool for thermal management and process optimization—particularly in high-end packaging applications.

 

Bio:
Professor Chi-Hua Yu is a scholar in artificial intelligence and advanced semiconductor packaging, with expertise in multiscale modeling and computational mechanics. He earned his Ph.D. from National Taiwan University in 2014 and conducted postdoctoral research at the Massachusetts Institute of Technology (MIT) from 2018 to 2020. Since 2020, he has been a faculty member at National Cheng Kung University, where his research focuses on applying AI techniques—such as deep learning, reinforcement learning, and generative modeling—to the design and optimization of electronic packaging systems. His work addresses key challenges in thermal management, mechanical reliability, and structural innovation for 2.5D/3D IC and fan-out packaging technologies. In parallel with his academic role, Prof. Yu is the founder and Chief Technology Officer of NeuroShine Ltd. Co., a university spin-off committed to developing AI-driven EDA tools for intelligent semiconductor design and advanced manufacturing. His combined academic and entrepreneurial efforts seek to bridge artificial intelligence with next-generation electronic system design.

Abstract:
Efficient thermal management remains a formidable challenge in high-power electronic systems, where escalating power densities and progressive miniaturization have rendered conventional cooling strategies inadequate. These limitations not only constrain system performance but also compromise long-term device reliability. While microfluidic cooling systems present a promising alternative, their optimization has traditionally depended on computationally intensive and time-consuming simulations, which often struggle to navigate the complex, multiphysics design landscape. To address these bottlenecks, this study introduces an integrated, AI-driven framework aimed at accelerating and automating the design of high-performance microfluidic cooling channels for electronic microchips. The primary objective is to establish an autonomous and intelligent design methodology that delivers thermally efficient and mechanically robust solutions.
The proposed framework leverages a hybrid computational strategy. Initially, the Representative Volume Element (RVE) approach, combined with the Finite Element Method (FEM), is employed to generate a diverse dataset comprising 2,160 unique microfluidic configurations. These designs systematically vary channel geometries and patterns, capturing twelve critical thermal and mechanical properties—including Young’s modulus, yield strength, and directional thermal conductivity. To circumvent the high computational costs of iterative FEM analyses, a dual-input convolutional neural network (CNN) is constructed to serve as a high-fidelity surrogate model. This network simultaneously ingests geometric images and numerical parameters of microchannel designs, providing real-time predictions of material properties with high accuracy.
Subsequently, a Deep Q-Network (DQN) reinforcement learning algorithm is integrated into the design loop to autonomously explore the vast design space. The DQN agent, informed by real-time feedback from the CNN surrogate, iteratively adjusts key design variables—such as channel width, spacing, and depth—toward optimizing vertical thermal conductivity (k₃₃). This dynamic exploration allows for rapid convergence to non-intuitive yet high-performing configurations.
The AI-driven framework exhibits exceptional predictive and optimization capabilities. The CNN surrogate consistently achieves R² values exceeding 0.99 across all twelve target properties when benchmarked against FEM simulations. The DQN algorithm effectively identifies innovative designs that demonstrate significant improvements in vertical thermal conductivity. Subsequent validation using computational fluid dynamics (CFD) and thermo-mechanical warpage simulations confirms the practical viability of these AI-generated solutions. Optimized configurations successfully maintain ASIC and HBM chip temperatures within safe operating limits while simultaneously reducing package-level warpage.

 

Bio:

Dr. Li-Cheng Shen is currently the AVP of Miniaturization Competence Center of USI, focusing on developing and researching cutting-edge technologies of miniaturization. With more than 20 years of experience in the semiconductor industry, Dr. Shen owned more than 30 patents in the fields of Fault Diagnosis System, 3D Package, Wafer Level Package, Opto-electronic Package, Electro-optical Circuit Board, Embedded Component Substrates, RF Module Testing and RF SiP/System Assembly. He is also the technical committee member of ED&A (Electrical Design and Analysis) of ECTC.
In 1998, Dr. Shen received a PH.D. degree in Electrical and Control Engineering from Nation Chiao-Tung University, Taiwan.

Abstract:

• Energy Eagerness in AI/ML Applications


• Why modulelization and miniaturization


• Roadmap of power solutions for AI/ML
  

 

Bio:
Chaur-Hwan (John) Lin is a veteran hardware engineering leader with over 30 years of experience in high-speed digital design, specializing in PCB technology and system-level signal and power integrity. As Director at Lenovo Corporation Taiwan, he leads initiatives in server platform development, advanced interconnect design, and ultra-low-loss PCB material innovation. John has contributed to cross-industry research efforts, including iNEMI, and holds multiple patents related to PCB design and measurement techniques. He earned his Master’s and Bachelor’s degrees in Electrical and Computer Engineering from the University of Wyoming and remains deeply engaged in next-generation PCB advancements.

Abstract:
The warpage of printed circuit boards (PCBs) significantly impacts high-speed signal integrity (SI) due to mismatches in the coefficient of thermal expansion (CTE) among substrate materials, as well as environmental factors such as temperature and humidity variations, and thermo-mechanical stresses during manufacturing and assembly. Warpage distorts signal traces, vias, and critical regions such as ball grid array (BGA) fanouts and connector pads, potentially leading to impedance discontinuities, increased crosstalk, and signal degradation.

This study presents a systematic analysis of how PCB warpage impacts high-frequency signal transmission by constructing three-dimensional (3D) models of chip BGA fanout regions and Mini Cool Edge IO (MCIO) connector fanout regions under normal and warped conditions using full wave electromagnetic solver. Time-domain simulations are used to evaluate eye height and eye width variations for Non-Return-to-Zero (NRZ) signaling (e.g., PCIe 5.0 at 32 GT/s) and Pulse Amplitude Modulation 4-level (PAM4) signaling (e.g., PCIe 6.0 at 32 GT/s).

Warpage, defined by IPC-2221 as Bow (arc-like bending) or Twist, is quantified using the formula (R1−R2)/L×100%, with a focus on typical 0.74% warpage (1 mil height) in connector regions and 0.53% in BGA areas—parameters aligning with both industrial standards (0.75% max for SMT components) and tightened engineering norms (≤0.5%).

Three-dimensional (3D) modeling reveals that warpage distorts signal paths, increasing insertion loss (IL) and return loss (RL). For example, in BGA regions, IL shifts from -0.15 dB to 0.15 dB, and RL deteriorates from -32.72 dB to -29.91 dB under warpage, while connector fanout areas exhibit RL degradation from -19.75 dB to -19.22 dB, verifying via networks’ sensitivity to geometric deformation. Frequency-domain analysis confirms impedance discontinuities caused by warpage intensify above 16 GHz, severely affecting high-frequency signals.

Time-domain analysis reveals that PCB warpage reduces eye height significantly for both NRZ and PAM4 signaling, while eye width remains relatively stable. For PCIe 5.0 (NRZ), eye height decreases by 3.8% from 163 mV to 157 mV, and for PCIe 6.0 (PAM4), the top eye height drops by 10.2% from 43 mV to 39 mV. This degradation is primarily attributed to amplitude fluctuations induced by warpage, which predominantly affect the vertical signal margin. In contrast, timing characteristics, such as jitter and offset remaining largely unaffected and receiver equalization techniques help maintain eye width stability. Despite the reduction in eye height, the bit error rate (BER) requirements 1E-12 for PCIe 5.0 and, 1E-6 for PCIe 6.0 provide sufficient margin to tolerate limited signal degradation without compromising transmission reliability. The system’s ability to absorb moderate levels of noise and reflection ensures continued compliance with performance standards.

This study innovates by:
① Quantifying the correlation between 0.74% warpage and 1 mil physical deformation, enabling cross-scale analysis from geometric to electrical degradation.
② Comparing NRZ/PAM4 eye diagram parameters to reveal multi-level modulation’s higher warpage sensitivity—PAM4’s smaller eye margin (6 mV vs. NRZ 15 mV) exacerbates SI degradation.
③ Proposing a "warpage-loss-eye diagram" analytical framework for PCB design.

Engineering insights emphasize the importance of the collaborative optimization across multiple domains to mitigate the effects of PCB warpage. This includes low CTE substrate material selection, symmetric stack-up design, and tighter process control with reflow temperature gradients.

Looking ahead, future research may explore multi-dimensional warpage phenomena-(Bow-Twist composites) and their impact on high-frequency bands beyond 32 GHz. Additionally, the integration of machine learning offers the promising potential to predict warpage-induced SI degradation enabling smarter design strategies for advanced packaging and high-speed interconnects.

 

Bio:
Ashton Huang received the B.S. degree in applied mathematics from the National Chung Hsing University, Taichung, Taiwan, in 2006, the M.S. degree in statistics from the National Chiao Tung University, Hsinchu, Taiwan, in 2008, and the Ph.D. degree in statistics from the National Chiao Tung University, Hsinchu, Taiwan, in 2016. He is currently a Technical Manager with ASE Inc., Taiwan. His research interests include AI, machine learning, data modeling, and data analysis.

Abstract:
As industrial manufacturing processes become increasingly complex, a wide variety of product defects can arise and evolve rapidly—some may even be never seen. To ensure product quality, AI image-based defect detection technologies have been widely used in the manufacturing industry. For example, Object Detection (OD) techniques learn defect features through human-annotated data and are effective at classifying defect types. In contrast, Anomaly Detection (AD) models learn the features of normal samples and identify anomalies without requiring manually labeled defective data.
Despite these advancements, rapid deployment of image-based defect detection still faces critical challenges in practical applications: a large amount of manually labeled data, a model that can be trained quickly for inspecting new products, and a single model applicable across various product types. To address these issues, we apply the following methods to accelerate model deployment on the production line:
Synthetic Data (SD) We leverage the Domain Randomization method, a technique of Synthetic Data (SD), to automatically generate defect images. This approach not only enhances the model's classification capability but also reduces the need for defect data collection. In our experiments, we trained the model on approximately 5,000 human-annotated substrate defect images. The results show that with SD, the model's recall increased from 82.1% to 93.1%, and precision improved from 82.2% to 93.4%. Furthermore, SD enables the model to achieve the original accuracy using half the size of the original dataset.
Light Anomaly Detection Model (LADM) The goal of the LADM model is to enable rapid deployment for product inspection. We modified the PatchCore AD model to develop a faster, high-performance, low-resource version. The model can be trained in under three minutes using around 1,000 normal samples with 512x512 image resolution. It achieves a high AUROC, with an overall average of 97.27% on the MVTec AD dataset.
Cross-Product Anomaly Detection Model (CADM) The semiconductor manufacturing industry typically offers a wide variety of products to meet customization demands. Training a separate AI model for each product leads to a large number of models, creating challenges in maintenance. We modified existing AD models into a generalized version applicable across multiple products. In our experiment, we trained a substrate dataset of around 1,000 samples from different products. The escape rate is under 0.05%, the false positive rate below 1%, and about 10% of cases are judged as uncertain, requiring human inspection. This approach enhances model management efficiency while maintaining high detection accuracy.

We integrate three technologies—SD, LADM, and CADM—into a unified detection framework. When a new product requires inspection, LADM is trained for immediate deployment to monitor production. Meanwhile, normal images are used to train CADM, gradually improving its accuracy. Once CADM outperforms LADM, it replaces LADM in the detection workflow. Anomalous data is labeled by humans and combined with SD to train a comprehensive OD model. OD re-inspects images flagged as anomalies by AD for final quality assurance. This approach improves defect detection, accelerates model deployment, and reduces maintenance costs in manufacturing.

 

Bio:
Have three years of rich experience in the field of artificial intelligence, focusing on algorithm research and software development. Currently, He hold a pivotal role as a core member of the AI team within Universal Scientific Industrial Corpora-tion, specializing in algorithm engineering.

Abstract:
Image similarity comparison is vital for manufacturing tasks like defect detection and quality control, yet conventional text-based searches are slow and error-prone. We propose HOAM (Hybrid Orthogonal Attention Model), a dual-branch network that fuses orthogonal attention mechanisms—using Multi-Head Self-Attention for fine-grained feature extraction and Sub-Center ArcFace loss for robustness to noise. By indexing embeddings with Faiss and performing K-Nearest Neighbors retrieval at inference, HOAM returns the top-5 most relevant images, reducing search time by 80%. Trained on 1,569 classes, HOAM achieves 99.86% Precision\@1, demonstrating state-of-the-art performance in complex, noisy industrial environments. We detail HOAM’s architecture, training strategy, and inference workflow as a high-precision, high-efficiency solution for industrial visual search.

 

Bio:
I have over 20 years of experience in software development and digital transformation across several industries including retail, automotive & luxury cars, telco, manufacturing. Currently, I am leading the industrial digital & control software strategy to drive the industrial digital transformation in the PCB Market through the use of Machine Learning, IIoT, Digital Twin, AI and other technologies.

Abstract:
Background
The increasing demand for environmentally responsible and highly adaptive manufacturing processes has driven the electronics industry toward digitalization. While many existing IIoT and MES platforms offer data collection and visualization capabilities, they often lack enabling real-time optimization or active feedback to manufacturing equipment.
In the context of PCB manufacturing, achieving meaningful sustainability and productivity improvements requires not only data monitoring but also deep integration with control systems and domain-specific insight.
This study presents an industrial case of DFS, a purpose-built IIoT platform for PCB production environments, which uniquely combines real-time data acquisition, process domain knowledge (chemistry and equipment), and closed-loop control integration. It contributes to both Track B1 (Sustainable Materials and Technology) and Track B2 (Smart Manufacturing, Inspection and Testing) by demonstrating how integrated control and optimization can lead to measurable improvements in resource efficiency and production quality.
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Methods
DFS is deployed as a multi-layer digital platform interfacing with diverse data sources, including process equipment, utility infrastructure, and environmental controls. Unlike most industrial platforms which passively collect data for reporting, DFS enables bidirectional communication with programmable logic controllers (PLCs). This allows the system to not only observe but also dynamically and safely adjust process parameters in real time, creating a closed-loop feedback control system based on high-level optimization goals.
The system architecture supports:
• Modeling of energy consumption at the device level using virtual sensors derived from correlated process data
• Rule-based and AI-supported optimization logic, enabling fine-grained equipment control (e.g., pump schedules, idle states, heating routines)
• Historical traceability and contextual data aggregation, enhancing root-cause analysis and predictive diagnostics.
Domain-specific models, rooted in the team’s extensive experience with PCB manufacturing chemicals, process stability, and equipment behavior, are used to interpret raw data in terms of process efficiency, material usage, and potential failure mechanisms.
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Results
The platform was implemented across multiple PCB manufacturing lines, with quantitative and qualitative improvements in both sustainability and operational performance.
For Track B1, sustainable outcomes included:
• Up to 15% reduction in electrical energy consumption achieved via process-aware equipment control (e.g., oven idle-state management, compressor load balancing),
• CO₂ footprint analysis and optimization enabled by real-time modeling without the need for additional hardware sensors,
• Better alignment with environmental compliance frameworks through integrated reporting tools.
For Track B2, smart manufacturing benefits included:
• Up to 50% reduction in troubleshooting time due to multi-source data aggregation and PCB-level traceability,
• Increased reliability in inspection and testing feedback through centralized access to high-resolution process data,
• Implementation of predictive alerts and dynamic thresholds that improved first-pass yield and reduced operator intervention.
A key differentiator of DFS is the active, data-informed control loop between the platform and factory floor systems. This makes it possible to close the gap between optimization logic and physical execution — something that conventional MES or IIoT systems typically lack. The study underscores how the synergy between deep process expertise and integrated control systems can transform traditional PCB manufacturing into a more sustainable, intelligent, and responsive process.

 

Bio:
Mr. Wu is a Manager at Mirle Automation Co. He holds an M.S. in Computer Science from National Chung Hsing University. With over 20 years of experience in software development and system architecture, Mr. Wu has led numerous projects focused on factory system development.

Abstract:
With the rapid advancement of smart manufacturing and Industry 4.0, Automated Material Handling Systems (AMHS) have emerged as a critical element for enhancing production efficiency, reducing operational costs, and strengthening market competitiveness. Currently, PCB factories still heavily rely on manual scheduling and monitoring, which is inefficient and highly struggle to respond to rapidly changing production demands. However, in highly complex processes and high-value material scenarios presented in PCB substrates factories, the implementation of automated material handling equipment such as Automated Guided Vehicles (AGVs), Overhead Hoist Transports (OHTs), and Panel Stockers faces significant challenges in handling efficiency, task scheduling, system stability, and data utilization.

This study proposes a MCS Intelligent Assistant digital solution to overcome material handling bottlenecks and maintain a high throughput rate. The proposed system involves automatically gathering real-time operational data from both MES and MCS systems. Then cleans and formats the data to ensure data integrity and availability. After preprocessing, the system calculates KPIs, such as task completion time, equipment utilization, handling failure rate, and system response time. Analytical charts that visualize transportation routes, equipment status, task allocation, and abnormal events will be provided for visual representation. MCS Intelligent Assistant system can then empower engineers to identify latent problems such as task delays, equipment idleness or route conflicts. The system could analyze transportation tasks, equipment operations and route traffic to accurately locate bottlenecks or high-risk equipment and support more informed scheduling decisions.

This research method can overcome the limitations in manual improvement of bottlenecks and maximize AMHS performance. In usual practice, it can achieve more than 25% reduction in problem solving time and regain productivity. In future work, it is possible to integrate advanced technologies such as Large Language Models (LLMs), the Internet of Things (IoT), and Digital Twin to further enhance this MCS Intelligent Assistant for smart manufacturing and ultimately realizing the grand vision of Industry 4.0.

 

Bio:
Chi Chen is currently a master's student in the Department of Mechanical Engineering at National Cheng Kung University, Taiwan. His research focuses on using machine learning to predict electromigration behavior in low-temperature Sn-Bi solder alloys for reliable electronic packaging.

Abstract:
Driven by RoHS regulations and the continued miniaturization of semiconductor devices, the industry is adopting low-temperature lead-free solders, especially focusing on Sn-Bi alloys. However, reliability issues such as electromigration (EM) effect are still tremendous challenges. This study develops a machine learning model to predict the resistance change induced by electromigration of Sn-58Bi low-temperature solder alloys. The training data are extracted from published literature and focus on resistance changes under different processing conditions. A non-destructive planar joint structure was used in their study, enabling resistance measurement without sample sectioning—an advantage for narrow solder channels where traditional techniques may damage samples. The dataset includes five groups of Sn-58Bi solder data extracted from literature, categorized based on combinations of current density of 2.2, 4.4, 6.6 A/cm², and temperature of 60, 80, 100 °C. These features are used to predict the resistance behavior of solder joints. A Gaussian Kernel Ridge Regression (GKRR) model is employed. Results show excellent predictive performance on the Sn-58Bi dataset, with an R² of ~0.99, indicating an excellent fit between predicted and actual resistance values. The root mean square error (RMSE) is 0.020 ± 0.005, meaning that the average difference between the predicted and actual resistance values is only about 0.02 mΩ, demonstrating both high accuracy and consistency. The framework may provide a promising way for evaluating EM-related resistance behavior in low-temperature solders and can be extended in future work to include additional alloy compositions and experimental validation.

Keywords: Electromigration, low-temperature solder, Sn-Bi alloys, Machine learning

 

Bio:
I am currently a fourth-year Ph.D. student in the Department of Chemical and Materials Engineering at National Central University, Taiwan. My research focuses on electromigration-induced failure mechanisms in solder joints. I have a strong background in solid-state diffusion, phase transformations, and interfacial reactions in microelectronic packaging. I am also proficient in EBSD (Electron Backscatter Diffraction) principles and analysis, with applications in crystallographic characterization of solder microstructures.

Abstract:
Lead-free solder is widely applied in electronic packaging as a critical interconnection for electrical signal transmission between chips. As the industry advances toward solder bump miniaturization and fine-pitch designs to enhance electronic performance, concerns related to electromigration (EM) in solder joints have become increasingly significant. The high current density passing through these joints can lead to phase transformation, under-bump metallization (UBM) dissolution and void formation even open circuit at the cathode, resulting in a substantial increase in electrical resistance. The microstructure evolution at the cathodic interface plays a critical role for EM-induced failure. In this study, the flip-chip solder joints were conducted EM test through energizing with 4.0×104 A/cm2. We focus on the microstructure at the cathode side to discuss the effect of Ni barrier on interfacial reaction of the flip-chip solder joints. Based on the cross-sectional SEM images in the EM-failed Cu/solder/Cu bumps, the Sn phase forms in the consumed Cu-pillar region. In addition, some voids are observed above the as-reflowed the Cu pillar/solder interface, suggesting that Sn phase transformation occurs prior to void formation during Cu pillar consumption. From EBSD analysis, the dihedral angle between current-stressing direction and c-axis of β-Sn is calculated by {001} pole figure. Effect of grain orientation on the Sn back-filled area has been discussed in this study. The back-filled Sn phase exhibits the same crystallographic orientation with the as-reflowed Sn grain. Moreover, the Sn back-filled rate is controlled by grain orientation. It is indicated that Sn grains with a small α angle exhibit a larger back-filling area. When the Cu pillar is covered with a Ni barrier, voids form either at the solder/IMC interface or inside the IMC layer beneath the reflowed Cu/solder joint. Furthermore, in the absence of Sn back-filling, IMCs are formed in the region of the consuming Cu pillar instead. According to EPMA analysis on the cathode side, the IMCs are (Cu,Ni)6Sn5, which indicated that diffusion of Ni atoms would be driven to dissolve into Cu6Sn5 layer to retard the formation of new Sn phase. The suppression mechanism of Sn back-filling has been proposed in this study. As Cu concentration of the solder near the interface between IMC/solder interface at the cathode reduce to lower than Cu solubility under current stressing, Cu6Sn5 will occur dissolution from its surface to transform into a new Sn phase. On the other hand, When Ni atoms dissolve into Cu6Sn5 phase to form (Cu,Ni)6Sn5, Cu6Sn5 dissolution will be retarded leading to suppression of Sn phase transformation because the Ni solubility in Sn is much smaller than the Cu solubility in Sn. Once Ni or Cu atoms are driven by electron flow from (Cu,Ni)6Sn5 near the cathode side to anode side, vacancies continue to accumulate in (Cu,Ni)6Sn5 phase when Cu6Sn5 dissolution is retarded, voids may easier to form.