Sessions Index

Abstract:

Advanced packaging is enabling unprecedented levels of integration, enabling dense interconnection of logic, memory and optical chiplets, to create a system in a package. In AI & data centric applications, the amount of silicon content in a single package is increasing dramatically every generation. To meet future scaling, high speed signaling and power delivery needs, the package substrate must also evolve significantly. In this talk, we will cover some of the recent advances in the EMIB package platform including multiple scaling vectors such as die to die interconnection pitch, package form factor and the introduction of a bridge with TSV to enable denser and more efficient integration on package. Further, we will also cover the Intel’s latest breakthrough’s in glass core substrates which have superior mechanical, physical and optical properties and can drive dramatic improvements in chiplet integration on a substrate.

Abstract:

The rapid expansion of AI is accelerating innovation in semiconductor packaging across both high-performance computing (HPC) systems and mobile devices. As power density and package complexity continue to increase, thermal management has become a key enabler for achieving high performance, energy efficiency, and long-term reliability. In other words, as the paradigm shifts toward mobile and on-device AI, thermal management at the package level is evolving from a design challenge to a fundamental physical limit.

This presentation will discuss the critical role of packaging materials in addressing the evolving thermal challenges of advanced AI packaging for both data center and mobile applications. Examples of material solutions, including the implementation of high thermal conductivity (high-k) materials and Heat Path Block (HPB) technologies for mobile AP and HBM packages, will be presented to illustrate how structural and material innovations have addressed increasingly demanding thermal requirements.

Building on these experiences, the presentation will explore the next generation of material solutions required as the industry moves toward package-level cooling for future HPC systems. Key enabling material technologies for these cooling architectures will be discussed, together with the structural and material innovations needed to support kilowatt-level power while maintaining package reliability and improving energy efficiency. Finally, the presentation will provide perspectives on future material innovations that will enable low-power, high-efficiency AI technologies across diverse computing platforms.

Abstract:

As the generative AI boom drives individual data center racks toward megawatt-scale power densities, next-generation high-performance computing (HPC) clusters are confronting insurmountable physical barriers defined by the "bandwidth wall" and the "power wall."
this presentation explores an enabling framework of energy-efficient AI technologies based on a dual-axis system architecture: Co-Packaged Optics (CPO) connection solutions and Vertical Power Delivery (VPD) networks, seamlessly integrated through advanced packaging material innovations.
On the optical axis, CPO mitigates high-frequency signal loss by heterogeneously integrating optical engines with computing silicon, significantly shortening electrical trace lengths.
On the power axis, VPD addresses the physical limitations of legacy delivery systems by utilizing backside power delivery and through-silicon vias (TSVs) to route power vertically from integrated voltage regulators (IVRs) directly beneath the core logic. We systematically analyze the material reliability of high-current density power SiP modules under 800V DC server power architectures.
Ultimately, this work outlines a cohesive, multi-dimensional material optimization blueprint essential for unlocking the co-design of optical paths and vertical power topologies in 2030 AI infrastructure.

Abstract:

AI infrastructure is increasing the electrical, thermal, and reliability demands placed on HDI boards and advanced package substrates. Higher interconnect density, finer routing, and more complex build-up/core architectures are pushing copper metallization beyond conventional design windows, particularly for high-aspect-ratio blind via filling, through-hole conformal plating, and reliable electroless copper seed-layer formation. This presentation discusses Qnity’s integrated copper metallization approach for future AI-driven interconnect development, balancing Microfill™ EVF series acid copper, Copper Gleam™ PPR series pulse acid plating copper, and Circuposit™ 6900 electroless copper technologies across HDI and advanced package substrate use cases.

The Microfill™ EVF series acid copper is positioned for copper electroplating of high-aspect-ratio blind vias, targeting AR up to 1.5 while enabling void-suppressed filling, controlled dimple/bump profiles, and process optimization across feature size, plating thickness, and bath condition. The Copper Gleam™ PPR series pulse acid plating copper addresses through-hole conformal plating and throwing power requirements where board thickness, via geometry, and current distribution increasingly challenge uniform copper deposition. By applying pulse-reverse waveform control and bridge/fill process concepts, the Copper Gleam™ PPR series pulse acid plating copper supports metallization in demanding multi-layer boards configuring beyond 6.5 mm in depth with aspect ratio larger than 30. Circuposit™ 6900 electroless copper complements these electrolytic solutions through electroless copper metallization, supporting continuous, adherent seed-layer formation on advanced laminate systems and enabling downstream copper electroplating and via-fill reliability.

Reliability validation is central to this approach. Test vehicles are designed and fabricated to represent emerging AI infrastructure requirements, then characterized through cross-section inspection, process metrics, and external reliability testing. OM Thermal Stress Test (Object Measurement / Optical Modification System) validation conducted at Robisan Laboratory, Inc. is incorporated as an independent reliability reference, without overstating results beyond available data.

Beyond individual chemistries, the work highlights Qnity’s capability to combine test vehicle design, fabrication, reliability characterization, analytical metrology, and data-driven customer collaboration. This integrated framework connects material/process learning to customer design rules and supports scalable interconnect development for HDI, advanced package substrates, and next-generation AI electronics.

Abstract:

The rapid growth of artificial intelligence (AI) and high-performance computing (HPC) is driving a fundamental transformation in power delivery architectures. As power density and current demand continue to increase within increasingly compact system designs, thermal management has become a critical challenge for next-generation power PCBs. Conventional PCB materials are often unable to simultaneously meet the requirements for thermal conductivity, electrical insulation, mechanical reliability, and manufacturability, creating new demands for advanced material solutions.

This presentation discusses how advanced thermally conductive PCB material technologies can address these challenges by improving heat dissipation while maintaining compatibility with conventional PCB manufacturing processes. It will highlight key design considerations and application opportunities for AI power boards and other high-power electronic systems, demonstrating how optimized material platforms can improve thermal performance, system reliability, and overall design flexibility.

As a provider of advanced material solutions, Qnity works closely with customers and partners across the electronics value chain to accelerate product innovation and enable the next generation of AI power electronics.

Abstract:

As PCI Express technology continues to scale toward 256 GT/s operation, the printed circuit board is becoming one of the most critical limiting factors in future high-performance copper interconnect design. While previous PCIe generations could often be supported through incremental improvements in routing strategy and signal conditioning, PCIe 8.0 introduces a substantially tighter electrical margin environment in which PCB material selection, stackup construction, conductor loss, via design, breakout density, and manufacturing tolerance must be evaluated together at the early platform planning stage.

This paper investigates the PCB technology challenges associated with next-generation 256 GT/s PCIe copper channels for data center and AI computing platforms. Instead of focusing only on a single routing structure, the study examines the broader channel design tradeoffs required to support future high-speed interconnects, including frequency-dependent insertion loss, impedance discontinuity, crosstalk coupling, via transition behavior, and high-density escape routing from advanced CPU and GPU packages. Simulation-based analysis is used to compare practical PCB design options and identify the key parameters that most strongly influence channel feasibility and design margin.

The results highlight that successful PCIe 8.0 implementation will require a more integrated PCB design methodology, where material capability, stackup planning, breakout architecture, routing layer assignment, and manufacturing control are co-optimized rather than treated as independent design variables. The paper provides practical signal integrity considerations and early design guidelines for evaluating PCB technology readiness, reducing channel risk, and enabling robust 256 GT/s PCIe copper links in next-generation data center platforms.

Abstract:

This paper presents a pin-to-pin passive channel measurement methodology for high-speed server interconnects, including PCIe Gen6 and CPU-to-CPU channels. As data rates continue to increase, accurate passive channel characterization plays a significant role in high quality HSIO design. There are many factors affecting measurement accuracy for assembled DUT systems such as fixture effects, reference-plane uncertainty, de-embedding structure, multiple interconnect discontinuities, etc. These challenges reduce measurement accuracy and make signal integrity validation and hardware debugging more difficult.

The proposed methodology combines calibrated Vector Network Analyzer (VNA) measurements with fixture characterization and de-embedding techniques to extract passive channel characteristics directly between system pins. The measurement flow is validated through S-parameter comparison, TDR analysis, measurement repeatability, and correlation with simulation results to verify channel extraction accuracy and robustness.

The methodology is demonstrated on practical server platforms for both PCIe Gen6 and CPU-to-CPU interconnects. Measurement results show that the proposed approach effectively identifies signal integrity issues caused by sockets, connectors, vias, and PCB structures while providing reliable passive channel measurement models for system-level simulation and design verification. The proposed methodology offers a practical solution for passive channel characterization, validation, and hardware debug, and can be readily extended to future high-speed server interconnect technologies.

Abstract:

As DDR5 and next-generation high-speed memory interfaces scale toward higher data rates, the signal integrity (SI) margin available to system designers becomes increasingly sensitive to localized impedance discontinuities. Among the key SI challenges in high-speed digital design, including impedance mismatch, inter-symbol interference (ISI), insertion loss, return loss, and crosstalk, impedance control within the printed circuit board (PCB) escape region has become a critical design consideration. In dense memory interfaces, high pin count packages and tight via-to-via pitch constraints limit the available routing space, forcing escape traces to use narrower geometries than the main routing region. This trace-geometry difference introduces a characteristic impedance discontinuity between the escape region and main channel route, which can degrade signal quality through increased reflections and reduced timing and voltage margins.

To improve impedance continuity, an escape tab structure is commonly incorporated into the escape trace to locally adjust the effective trace width and reduce the characteristic impedance mismatch between escape and main routing regions. While this approach provides a practical method for impedance tuning, tab manufacturability introduces an additional design concern. In actual PCB fabrication, tab dimensions may deviate from nominal values because of etching, registration, and process tolerance variations. These deviations can alter the intended impedance compensation and affect the overall channel response. Despite this risk, the impact of escape tab manufacturing tolerance on system-level DDR margin is not widely quantified in current design practice, creating uncertainty in how much tolerance should be allocated during PCB design and validation.

This paper presents a margin sensitivity study of DDR PCB escape trace impedance and escape tab manufacturing tolerance. A 3D electromagnetic modeling approach is used to evaluate the electrical behavior of escape structures with and without tab implementation, as well as tab geometries varied across representative manufacturing tolerance conditions. The study examines frequency- and time-domain electrical metrics, including time-domain reflectometry (TDR), insertion loss (IL), and return loss (RL), to characterize the local discontinuity and its influence on channel performance. In addition, system-level eye-margin simulations translate the electrical response into practical DDR design impact, enabling direct comparison between the margin improvement from tab integration and the margin degradation from tab dimensional variation.

The simulation results are further supported by lab measurement correlation to validate the modeling methodology and confirm the observed design trends. The analysis demonstrates that adding tabs in the escape region provides a measurable improvement in impedance matching and overall SI margin compared with a baseline escape design without tabs. Although tab-size manufacturing tolerance introduces some performance variation, the resulting degradation remains smaller than the margin benefit achieved through tab implementation. These findings indicate that escape tab structures are an effective and robust design technique for mitigating impedance discontinuity in dense DDR PCB escape regions, and that their performance advantage can be preserved under realistic manufacturing tolerance conditions. The study provides practical guidance for DDR PCB layout optimization and tolerance assessment in high-speed memory interface designs.

Abstract:

This paper presents a practical crosstalk mitigation methodology for stacked micro-via high-density interconnect (HDI) designs targeting PCIe Gen6 and future high-speed serial interfaces. As data rates continue to increase, localized electromagnetic coupling from closely spaced and vertically stacked micro-vias becomes a critical signal integrity challenge, degrading far-end crosstalk performance and reducing receiver eye margin. To address this, multiple stacked and staggered micro-via configurations are evaluated using 3D electromagnetic extraction and SEASIM LTI system-level simulation. The study correlates passive crosstalk behavior with active eye-margin impact to identify layout configurations that reduce coupling while maintaining routing feasibility and manufacturability. The optimized HDI configuration achieves up to 4.8 dB improvement in power-sum FEXT compared with baseline design, demonstrating measurable system-level benefit without requiring major design rule changes. The proposed approach provides actionable layout guidance for mitigating micro-via coupling in dense HDI channels and supports robust signal integrity design for PCIe Gen6 and beyond.

Abstract:

As a large language model (LLM) inference continues to scale in both context length and serving concurrency, the key value (KV) cache has emerged as a dominant system of bottleneck. What was once a localized, GPU resident optimization now places pressure on the entire platform, affecting memory capacity, scheduling behavior, and overall resource utilization.

The initial response to this "KV cache explosion" has naturally focused on memory centric approaches, including capacity growth and disaggregated memory thinking. These solutions are effective in relieving immediate memory pressure, but they also reveal a deeper challenge: KV cache behavior increasingly depends on coordination across CPU, memory, and GPU, rather than on any single component in isolation.

This talk argues that KV cache should be viewed as a system level coordination problem, not merely a memory placement problem. We propose a system level rethinking of hardware roles, in which the CPU evolves beyond a passive data loader and instead plays a more active, coordinating role—shaping how KV cache is handled across the system—while GPUs remain focused on high throughput execution and memory systems provide scalable capacity.

Abstract:

The rapid growth of AI workloads has driven demand for higher-performance CPUs and GPUs, increasing both component power and board-level temperatures. While component thermal solutions have advanced, power-plane heating on PCBs has not kept pace: recent measurements show board hotspots exceeding 100°C in some real-world scenarios. Conventional PCB analyses that consider only Joule heating often yield overly pessimistic results and prompt excessive copper pours, and existing tools rarely capture the coupled electrical and complex thermal interactions among components, heatsinks, and power planes.

Failure to perform accurate thermo-electrical co-simulation leads to multiple technical and business consequences: increased resistive losses and lower system efficiency; elevated board temperatures that raise junction temperatures and cause CPU/GPU throttling; conservative, costly capacitor derating or selection; degraded transient PDN response that can impair processor performance; shortened component lifetime and higher warranty/field-failure costs; and larger cooling, BOM, and time-to-market penalties.

This paper identifies gaps in current thermo-electrical co-simulation approaches and proposes a modified full-system co-simulation methodology that achieves high correlation with laboratory measurements. We also present a simplified, IP-safe simulation model that substantially reduces simulation time and compute requirements while maintaining good correlation with measurements, enabling safe distribution to customers for system design without exposing proprietary board details.

Table 1: Board temperature Lab vs Sim

Figure 1: Lab measurement

Figure 2: Simulation data

Abstract:

This presentation introduces the challenges of CoW hybrid bonding associated with the scaling of Sony’s CIS hybrid bonding to finer pitches. Based on recent research results, it discusses the understanding of bonding misalignment behavior and countermeasures for Cu recess. In addition, the electrical characteristics after CoW hybrid bonding with a 1.4 µm pad pitch are presented.

Abstract:

To address SeWaRe defects induced by the coefficient of thermal expansion (CTE) mismatch between glass and resin, stress-relief structures consisting of resin-filled corner regions and edge-protection materials were introduced into a glass-core build-up substrate. The proposed structures effectively mitigated stress concentration during dicing and chip assembly. As a result, a TGV-equipped glass-core package substrate with high-density copper wiring and 11 build-up layers on each side was successfully fabricated without SeWaRe defects.

Abstract:

Advances in AI technology are increasing demand for higher-performance and lower-cost AI modules. As a result, semiconductor packages require larger formats, finer interconnects, and higher integration. Glass core substrates are gaining attention as a key technology to meet these demands.
A major challenge for glass core substrates is TGV metallization, where achieving both reliability and mass production capability remains difficult.
This presentation introduces ULVAC’s PVD sputtering technology and equipment for TGV seed-layer formation, focusing on adhesion, high purity, low contamination, and step coverage.

Abstract:

AGC’s TGV technology is a next-generation material solution that meets the electrical performance, thermal stability, and dimensional accuracy required for high-density, high-frequency packages. This presentation outlines the features of TGV processing technology and presents the results of electrical, thermal, and mechanical reliability evaluations, summarizing AGC’s contributions toward enabling next-generation packaging.

Abstract:

With the advent of the AI era, the performance requirements for semiconductors and its packaging technologies have increased dramatically. In this technology trend, redistribution layers (RDLs) require materials and processes that offer higher functionality, higher density, and lower loss.
In this presentation, we introduce a high-resolution photosensitive polyimide developed by the authors. Furthermore, to enable finer patterning of high-performance polyimide, we also investigated a dry etching process using Photo-SOG as a mask, and the results will be presented.

Abstract:
PCI Express* 6.0 doubles the data rate to 64 GT/s using four-level pulse-amplitude modulation (PAM4), which significantly reduces voltage and timing margins compared with prior non-return-to-zero (NRZ) generations. As a result, card electromechanical (CEM) electrical compliance becomes far more sensitive to channel loss, fixture correlation, stress calibration, setup control, and link-training behavior. This paper presents a Gen6 CEM electrical compliance validation methodology from a system perspective, aiming to improve repeatability and reduce ambiguity during platform bring-up. Because the Gen6 channel-loss budget is substantially tighter, small deviations in parameter configuration, calibration conditions, or execution sequence can lead to Link Training and Status State Machine (LTSSM) instability, incomplete link equalization (LEQ), or false failures.
The test environment integrates a high-bandwidth oscilloscope, Gen6 CEM fixtures, a bit error rate tester (BERT), and SigTest and SeaSim analysis tools. Relative to Gen5, Gen6 compliance introduces several key changes: 64 GT/s PAM4 signaling, a reduced channel-loss budget, PAM4 top-eye criteria, first-bit error rate (FBER)-based Rx validation, and additional RLM/SNDR requirements.
The transmitter methodology comprises preset verification, PAM4 signal-quality evaluation, RLM/SNDR, and 100 MHz clock-jitter testing. Signal-quality evaluation represents the most significant change from previous NRZ generations: instead of directly assessing an NRZ eye, the 64 GT/s PAM4 waveform is captured through a tuned fixture path and processed by SeaSim with channel embedding, CTLE/DFE equalization, and top-eye extrapolation to the 1e-6 criterion, with the resulting PAM4 top eye evaluated against the required eye-width (EW) and eye-height (EH) limits.
The receiver methodology covers calibration, LEQ, and FBER testing. TP3 sets the baseline path, TP2 adds differential- and common-mode interference (DMI/CMI) stress, and TP2P defines the stressed eye after package embedding. The device under test (DUT) must enter the required Loopback state, complete LEQ under stress, and meet the pre-forward-error-correction (pre-FEC) FBER target.
A key Gen6 validation challenge is the methodology transition from Gen5 NRZ-based testing to Gen6 compliance built on PAM4 signal quality (Tx) and FBER-based receiver validation (Rx). PHY test conditions, stress calibration, preset configuration, and loopback-entry flow must be applied consistently; otherwise the DUT may fail to reach a stable LTSSM/Loopback state, complete LEQ at a non-representative operating point, or produce inconsistent results across platforms and customer setups. Common sensitivity areas include Tx top-eye margin after channel embedding, Rx stressed-eye calibration correlation, LTSSM/Loopback entry stability, and LEQ convergence under stress. To distinguish setup-induced failures from board-design issues, the debug flow first checks run-to-run repeatability, fixture/cable correlation, calibration consistency, and receiver equalization settings.
By standardizing stress calibration, preset configuration, and loopback-entry flow, the methodology improves run-to-run repeatability and reduces setup-induced false failures during platform bring-up, while separating setup-induced failures from genuine board- or channel-design limitations. Detailed customer/platform observations and representative failure analysis will be presented in the full paper.

Abstract:
With the rapid development of artificial intelligence(AI) and high performance computing (HPC) applications, the high-bandwidth memory required for die-to-die (D2D) communication faces challenges. High bandwidth memory Gen4 with high channel density and high transmission speeds is a great solution. However, HBM4 requires a high-density fine-line structure to be implemented. ASE FOCoS is a promising advanced package that can achieve high channel density and high bandwidth. This paper proposes a structure for HBM4 with D2D high-speed. By optimizing the line width and line spacing of various interconnect channels, design architectures for high-bandwidth memory (HBM4/HBM4E) enabling high-speed chip-to-chip communication were implemented using 9 RDL with 7 fine-line routing layer design.
In the design of fine-line interconnects for Die-to-Die (D2D) communication, crosstalk is a primary factor affecting signal integrity performance. The analysis of the channel S-parameter performance encompasses insertion loss, return loss, near-end crosstalk power sum (NEXTPS), and far-end crosstalk power sum (FEXTPS). 3D simulation tools were employed to calculate for variations in signal-ground configurations, redistribution layer (RDL) thickness, and polyimide (PI) thickness. During eye diagram analysis, both even-mode and odd-mode signal coupling across all fine-line routing layers were considered. Furthermore, in accordance with the JEDEC HBM4 EQ specifications, a simple decision feedback equalizer (DFE) design was implemented at the transmitter (TX) side. After optimization, this approach significantly enhanced the D2D transmission rate.

In this paper, we propose a distinct line/space (L/S) design implemented within 9-layer redistribution layer (RDL) structures. The simulation results of the HBM4 eye diagrams take into account the even-mode and odd-mode signal coupling in the D2D channels. The worst-case channel transmission rates exceed 12 Gbps, easily meeting JEDEC specifications. With the integration of a simple equalization (EQ) scheme, the maximum data rates reach over 15 Gbps, fully complying with the current mainstream HBM4 speed requirements.

Abstract:
Millimeter-wave (mmWave) radars operating at 76–81 GHz are integral to advanced driver-assistance systems (ADAS) for their high angular resolution and compact design. Nonetheless, high-frequency electromagnetic (EM) losses might lead to significant heat generation, causing thermomechanical stress and substrate warpage due to the mismatch in coefficient of thermal expansion (CTE) between organic substrates and copper (Cu) traces. This paper systematically evaluated how substrate warpage affects microstrip comb-line antenna characteristics through 3D EM simulations (ANSYS HFSS) and hardware characterization via an anechoic chamber and a vector network analyzer (VNA). Experimental and numerical results indicated that substrate warpage minimally impacts the reflection coefficient (S11) and gain (G). However, it induced a distinct shift in the radiation pattern’s main lobe, which ultimately degrades the angular resolution and detection accuracy of automotive radar infrastructure.

Abstract:
With the rapid evolution of 5G, emerging 6G networks, and low-Earth-orbit (LEO) satellite communication systems, millimeter-wave (mmWave) technologies have become a key enabler for high-data-rate and spectrum-efficient wireless communications. To meet the increasing demand for compact, high-performance, and highly integrated radio-frequency (RF) front-end modules, advanced organic package substrates have emerged as a promising platform for RF integration.
This work presents a dual-band antenna-and-diplexer-in-package (ADiP) implemented on a 14-layer Bismaleimide Triazine (BT) substrate for 5G FR2 applications operating in the n257 (28 GHz) and n260 (39 GHz) bands. The proposed architecture integrates a broadband antenna array and a compact diplexer within a single package substrate, enabling reduced interconnection loss, compact module size, and enhanced system integration density.
To realize broadband operation, a stacked-patch antenna incorporating multilayer artificial magnetic conductor (AMC) structures is developed. The antenna achieves an impedance bandwidth exceeding 50%, covering the frequency range from 26.5 GHz to 40 GHz. Simulated and measured radiation characteristics demonstrate stable performance across both operating bands. To further improve array performance, a 1×5 antenna array is employed together with a novel decoupling structure and a defected ground structure (DGS). These techniques effectively suppress parasitic resonances and mutual coupling, resulting in improved gain flatness and an isolation enhancement of 13.9 dB between adjacent antenna elements. The antenna array achieves a 10-dB impedance bandwidth of 42% and a peak realized gain of 10.8 dBi.
A compact dual-band diplexer based on fourth-order step-impedance resonator (SIR) bandpass filters is also designed and integrated within the package substrate. The diplexer exhibits insertion losses below 2 dB, return losses better than 15 dB, and channel isolation exceeding 30 dB, providing excellent frequency selectivity and out-of-band rejection.
The integrated ADiP module occupies an overall size of only 4.4 × 23.0 × 1.12 mm³. Simulated results demonstrate realized gains of 9.3 dBi and 10.0 dBi for the n257 and n260 bands, respectively, while achieving out-of-band gain suppression exceeding 40 dB. The proposed architecture validates the feasibility of co-integrating antenna arrays and passive filtering functions within a compact organic package substrate, showing strong potential for future 5G FR2, 6G, and LEO satellite communication applications.

Abstract:
With the rapid growth of datacenter applications and increasing demand for higher data rates in artificial intelligence (AI) servers, high-speed interconnect (HSIO) channel designs are adopting multi-connector topologies that incorporate cable assemblies to connect multiple boards, PCIe switches, and end devices, including graphics processing units (GPUs), Smart Network Interface Cards (SmartNICs), and computational storage devices. Accordingly, cable optimization in high-density AI server designs is essential for maintaining signal integrity and achieving low bit error rates (BER), particularly as four-level pulse amplitude modulation (PAM4) replaces conventional non-return-to-zero (NRZ) signaling.
The high-speed cable assembly illustrated in Figure1 was evaluated in this study. The assembly utilizes SFF-TA-1016 Mini Cool Edge IO (MCIO) connectors with an x8 lane configuration. Two such cables were interconnected between main board 1 (MB1) and main board 2 (MB2) to establish an x16 lane-width link of, Intel® Ultra Path Interconnect 3.0 (UPI3.0) interface, enabling cross-CPU-socket I/O communication within an AI server platform, as shown in Figure2. The electrical validation (EV) setup depicted in Figure2 was employed to characterize the first bit error rate (FBER), timing margin, and voltage margin at the CPU receiver using the Intel® IO Margin Tool (IOMT). In parallel, return loss and impedance characteristics were measured using a dedicated test fixture in conjunction with a vector network analyzer (VNA), as illustrated in Figure3.
As summarized in Table1, six 70-cm high-speed cables—three round and three flat designs with distinct characteristics—were selected for evaluation. As depicted on Figure4, flat cable consists of differential wires bundled in parallel ribbon to form a flat surface while the round cable has strands of wires twisted around each other to create a round cylindrical shape.
As shown in Figure5, the round cables (highlighted in the blue region) exhibit lower return loss compared to the flat cables, while the impedance profiles in Figure6 remain within the specified range of 84–92 Ω for all cable designs. In addition, the 56 GT/s FBER values measured at the CPU, as shown in Figure7, are below the specification limit of 1e-6 across all cable types. However, as shown in Figure8, the timing margin of certain cables falls below the specified threshold, while the voltage margin of all cables is above the threshold.
As summarized in Table2, round cables exhibit superior electrical performance compared to flat cables, with lower return loss and higher voltage and timing margins. However, since the overall channel design complies with specification limits and the CPU receiver is effectively equalized, both cable types demonstrate comparable performance under 56 GT/s PAM4 operation. These results highlight that optimized cable selection, combined with robust electrical validation, is critical for ensuring reliable high-speed interconnect performance in high-density AI datacenter board designs.

Abstract:
As data center silicon advances toward PCIe 7.0/8.0, 224 Gb/s SerDes, and AI-scale interconnect fabrics, printed circuit board (PCB) channels demand characterization methodologies that deliver significantly higher accuracy, repeatability, and efficiency than legacy approaches. The Delta‑L methodology, originally developed to isolate PCB trace loss from connector, launch, and probing artifacts, has served as a de facto reference for PCB material qualification for over a decade and has been incorporated into IPC standards.
Conventional PCB characterization methodologies are typically limited to 40 GHz, and extending accurate measurements beyond this range remains challenging due to limitations in test structures, launch designs, and ecosystem-level methodologies. While coaxial connector-based techniques can support higher frequencies in controlled laboratory environments, they are not scalable for high-volume sampling or production scenarios.
This work presents the latest evolution of the Delta L methodology—a comprehensive framework that extends measurement bandwidth from 40 GHz to 67 GHz, replaces complex coaxial implementations with scalable contact-based probing, improves correlation fidelity, and introduces automation to meet next-generation high-speed design requirements.
The proposed approach advances four key pillars: de-embedding algorithms, unified footprint design, test coupon optimization, and probing hardware. An enhanced eigenvalue-based physical fitting algorithm enables accurate loss extraction beyond the 40 GHz ceiling of prior implementations, addressing the >20% per-inch uncertainty observed at higher frequencies. A redesigned test coupon structure with optimized pad footprints and via anti-pad geometries suppresses resonance and ensures broadband impedance consistency across diverse stack-ups, including 4 mil core/5 mil prepreg, 3 mil core/4 mil prepreg, and microstrip configurations.
Probe technology is co-developed with industry partners, transitioning from conventional 40 GHz G S S G 500 µm probes to certified 60+ GHz contact-based solutions. In parallel, a robotic probing system replaces manual operation, significantly improving measurement repeatability and reducing labor overhead.
The methodology is aligned with data center and AI platform requirements through defined material categories and loss targets spanning PCIe Gen5 through PCIe Gen8 and UALink. These targets map platform evolution—from current data center systems to next-generation GPU and AI platforms—to representative loss budgets, including approximately 1.0 dB/in at 16 GHz and 32 GHz, and 1.4 dB/in at 53 GHz. Experimental results demonstrate accurate de-embedded loss extraction up to 67 GHz. Probe Quality Characterization (PQC) confirms high-quality launches without insertion loss/return loss (IL/RL) crossover, while robotic Delta L measurements show significantly improved repeatability compared to handheld approaches.
By enabling consistent, high-fidelity measurements across materials, processes, and laboratories, the proposed Delta L framework reduces cross-laboratory variation and accelerates qualification cycles for next-generation platforms, including PCIe 7.0, 800G/1.6T Ethernet, UALink, and AI accelerators.
In summary, this work establishes a robust, scalable, and production-ready reference methodology for PCB electrical characterization, delivering expanded frequency coverage, improved accuracy, and enhanced measurement efficiency through coordinated advances in algorithms, structures, hardware, and automation.

Abstract:
Modern server processors' increasing pin density forces narrowed breakout (NB) PCB traces into a signal-over-void (SOV) condition as they route through via antipads with repeated jogs. These NB escape traces increase differential impedance, insertion loss (IL), and notably, IL variation. This work evaluates IL at 5, 8, 16, 18.75, and 28 GHz by characterizing two jogged routing types against a straight baseline, using 1,600 data points across seven ultra-low-loss copper-clad laminates, two lamination structures, and five PCB fabricators. Impedance screening is insensitive to the pattern, with a median jog-straight difference of only 0.98 to 1.34 Ω. At 16 GHz and above, IL outliers and penalties from jogged SOV routing become non-negligible. Outlier rates reach 9.5%, 10.5%, and 11.5%, with IL penalties up to 5.9%, 6.6%, and 10.8%, at 16, 18.75, and 28 GHz, respectively. A split build extending the reference ground toward the antipads largely removes the paired penalty, identifying the SOV condition as the root cause. NB IL upper limits are then anchored to the measured jogged population, up to 7.2%, 7.9%, and 17.2% above the anchored straight baseline at 16, 18.75, and 28 GHz, respectively. Furthermore, the temperature-induced IL increase up to 100 °C is demonstrated to complete the comprehensive characterization. Consequently, coupon-based NB trace characterization is essential for modern high-speed PCB designs.

Abstract:
The transition from 112 Gbps to 224 Gbps data transmission is placing increasingly stringent demands on signal integrity within advanced PCB and package substrate architectures. As operating frequencies continue to increase, conductor losses associated with copper surface roughness become a critical contributor to channel performance degradation due to reduced skin depth and increased current confinement near the conductor surface. Consequently, copper surface morphology has emerged as a key consideration in the design and evaluation of next-generation interconnects.

This paper examines the relationship between copper surface topography and high-frequency electrical performance by reviewing the mechanisms linking surface roughness, conductor loss, and insertion loss. Industry-standard roughness models, including the Hammerstad, Huray, and Cannonball-Huray approaches, are discussed to highlight their applicability, assumptions, and limitations for predicting conductor losses in advanced high-speed channels.

In addition, practical factors influencing the use of these models are evaluated from the perspective of PCB and package substrate manufacturing. Particular attention is given to the influence of surface morphology, roughness characterization, process uniformity, cosmetic characteristics, and adhesion-related surface treatments on overall interconnect performance and model relevance. Practical observations from surface engineering studies are used to illustrate the challenges associated with relating measured copper surface characteristics to conductor loss behavior in real manufacturing environments.

Finally, future requirements for 224 Gbps and beyond technologies are discussed, including the evolving trade-offs between conductor roughness, manufacturability, and electrical performance. The paper provides an industry perspective on the role of copper surface morphology and roughness modeling in enabling next-generation low-loss PCB and package substrate technologies.

Keywords: Copper surface roughness, Signal integrity, Insertion loss, Hammerstad model, Huray model, Cannonball-Huray, 224 Gbps, PCB, Package substrate

Abstract:
INTROUDCTION
AI servers and high-speed interconnects have moved PCB impedance verification from a coupon-level check to a system-level quality issue shared by system companies and PCB manufacturers. Traditional TDR instruments remain attractive for production because they are simple to operate [1]; however, their compensation is mainly temperature compensation. They do not provide a complete methodology to remove cable, probe, fixture, and path-loss effects [2][3]. As the measurement path becomes longer or more lossy, these residual effects can accumulate as apparent TDR impedance, resulting in inconsistent acceptance judgment even when the DUT itself has not changed. The representative measurement structures, impedance responses, and summarized numerical comparison are indicated in Fig. 1 to Fig. 6 and Table I.
METHODOLOGY
This paper proposes a VNA-based TDR measurement flow with correction, de-embedding algorithm, and launch-aware PCB test-vehicle design. A coaxial structure based on IEEE P370-style 1xOpen and 2xThru concepts and the NIST-traceable de-embedding evaluation approach [4][5] is first used to separate DUT behavior from fixture behavior, as shown in the coaxial-based measurement process in Fig. 1. The corresponding coaxial TDR impedance accumulation and de-embedding comparison are shown in Fig. 2. SOLT is treated as the reference condition, and the method is then extended to probe-based PCB measurement, as shown in Fig. 3, where launch mismatch and contact variation are closer to actual production inspection.
RESULTS AND DISCUSSION
After VNA-based 2xThru de-embedding, the extracted main-routing TDR remains close to the SOLT reference even when fixture loss is changed, as shown in Fig. 2, Fig. 4, and Table I. For the coaxial-based cases, the SOLT reference was 81.55 ohms; without effective de-embedding, the apparent TDR impedance increased to 82.56 ohms for the 1x-fixture case and 83.55 ohms for the 2x-fixture case. After 2xThru de-embedding, the extracted DUT impedance returned to 81.61 ohms and 81.83 ohms, respectively. For the probe-based setup, the SOLT reference was 51.27 ohms, while the 2xThru results were 51.30 ohms and 51.23 ohms, indicating good agreement with the reference main-routing impedance.
PROBE-MEASUREMENT UNCERTAINTY
To suppress this over-compensation mechanism, a likely-connector interface open launch pad is recommended on the PCB and used as a launch-compatible open reference during de-embedding. This launch-aware concept corresponds to the probe-measurement uncertainty and SOLT limitation shown in Fig. 5 and Fig. 6. Therefore, the launch-compatible open pad makes the extracted error box closer to the real measurement interface and helps prevent over-compensation in local discontinuity regions.
CONCLUSION
The proposed launch-correction VNA-based TDR flow bridges system companies and PCB manufacturers. Its goal is not only to improve one measurement result, but also to create a fairer, more transparent impedance verification ecosystem: system companies obtain more trustworthy IQC data, while PCB suppliers reduce false failures caused by path loss and inconsistent launch correction. The likely-connector open launch pad is positioned as a design-for-measurement guideline for future high-speed PCB test kits, with the complete evidence flow indicated by Fig. 1 to Fig. 6 and Table I.

Abstract:
The rack-level server production line yield rate optimization to meet weekly and monthly productivity throughput target would be the key to fulfilling the booming demand of high-density AI data center construction in this decade. One of the most unwanted scenarios would be errors found during system-level stress testing as major system yield killer and could potentially result in production line down disaster. Other than the known method of reducing the mean time to detect (MTTD) errors will increase effective production yield, our proposed method would focus on the early design, validation phases and small volume pre-production builds' link stability, channel quality assurance with good enough margin to error found threshold as quick error-free link’s channel indicator that details will be introduced in this paper.

Abstract:
This paper presents an electrical study of the impact of channel design affecting crosstalk in a DDR5 memory interface. The paper seeks to determine the limitations and tackle issues caused by complex design elements in combination with ever-increasing memory signal speeds. The study focuses on channel design by identifying the impact of signal-to-signal coupling through via length, channel routing schema and long serpentine signal routing. The correct implementation of the proposed methods yields improved margin performance in terms of eye height/Vref (mV) and eye width/delay (UI) margins. Of note, they maintain printed circuit board (PCB) design flexibility while enabling improved eye margins especially at higher memory data rates. A well-designed system can extend design limits while minimizing platform cost. In turn, a highly correlated simulation methodology capable of accurately predicting feasible routing solutions in pre-silicon evaluation of complex platform topologies is essential. This capability enables PCB designers to optimize hardware parameters such as layer count and board thickness. Consequently, it enables scalable and accelerated server hardware development for cost-efficient solutions, while maintaining system electrical integrity throughout the product lifecycle by enabling reliable signal integrity (SI) trade-off analysis and mitigating risks associated with suboptimal designs.
Keywords: Active Via Length, Channel Routing Schema, DDR5, Memory, Sensitivity Study, Serpentine Routing, Signal Integrity.

Abstract:
The semiconductor packaging industry is increasingly seeking cost-effective alternatives to conventional gold (Au) bonding wires. Au-coated Ag (ACA) wire has emerged as a promising candidate; however, its interfacial reliability and intermetallic compound (IMC) evolution under high-temperature conditions require further investigation. This study evaluates the interfacial behavior of 0.6mil 99.0% Au and 0.7mil Au-coated Ag (ACA) wires under high-temperature storage (HTS) at 125 °C, 150 °C, and 175 °C using a die-attached stacked wire bond BGA package with forward wire bonding. Bonding performance, IMC growth kinetics, activation energy, and microstructural evolution were systematically analyzed using SEM/EDS and EBSD. ACA exhibited superior bonding performance, slower IMC growth, higher activation energy (1.174 eV), and no Kirkendall void formation compared to Au (0.8372 eV). These results demonstrate that ACA provides improved interfacial stability and reliability under prolonged thermal aging conditions.

Abstract:
The growing number of I/O connections in advanced computing has raised current densities, making solder joints highly sensitive to electromigration (EM) damage. Following the ban on toxic lead, Sn-Ag-Cu (SAC) alloys became the standard choice. However, their high melting temperatures (>200°C) worsen thermal stress and assembly defects. To solve this, low-temperature solders (LTS) like Sn-Bi alloys are widely used. While Sn-Bi offers good initial strength, operational heat causes bismuth (Bi) to separate, making the joints brittle and lowering reliability. Hybrid solder joints combining SAC305 and Sn-Bi offer a balanced solution. This combination lowers overall thermal stress, while the softer SAC solder absorbs mechanical strain, reducing the brittleness caused by Bi separation. [1]
As electronic devices shrink, EM challenges in these joints become more critical. The directional movement of atoms during EM causes structural damage, typically appearing as solder being pushed out at the anode and voids forming at the cathode, eventually breaking the connection. [2] Under high current density, SAC resists EM better than Sn-Bi. In Sn-Bi systems, the separation of Sn and Bi is made much worse by the electron flow. [3] In hybrid solders, Bi shows a strong tendency to move in the direction of the electron flow. Furthermore, because the structure of a hybrid joint is asymmetrical, it results in different types of failures. [4] [5]While most research focuses on large-scale electrical testing, basic studies on how atoms diffuse and move between these two different solders are still lacking.
To address this research gap, our study investigates electromigration in hybrid solder strips prepared inside grooves etched on Si (001) wafers. Using standard semiconductor processing, we can precisely control the testing area to apply and reflow the two solders step by step, starting with the higher-melting SAC and followed by the lower-melting Sn-Bi. (Fig.1. &2.) Furthermore, dedicated copper pads are added to help the current flow smoothly into the test samples. This specific design reduces current crowding and prevents test probes from physically damaging the solder during the experiment. After applying a high current density over 10⁴ A/cm², we used microstructural observation and elemental analysis to clearly understand the different current-induced atom movements at the cathode, anode, and the SAC/SnBi interface. By tracking how these atoms migrate, we can better explain the fundamental failure mechanisms of hybrid solders.

Abstract:
In recent years, driven by the explosive demand for artificial intelligence (AI) and high-bandwidth memory (HBM), hybrid bonding has become increasingly crucial in advanced packaging. Hybrid bonding with high-density interconnects is critical for advanced electronic packaging. However, a major challenge in Cu/SiO2 hybrid bonding is the high susceptibility of Cu to oxidation. During the chip-on-wafer (CoW) process, exposed Cu reacts with atmospheric oxygen to form copper oxides (CuxO). This oxide layer severely impedes Cu interdiffusion and degrades manufacturing yield. Consequently, numerous surface modification methods—such as self-assembled monolayers (SAMs), metal cap passivation, plasma activation, and wet chemical cleaning—have been developed to suppress the formation of the copper oxide layer.
To enhance bonding performance, we introduce a method utilizing a Cu-Mn alloy self-forming diffusion barrier, where Mn is doped into the Cu seed layer. During the bonding process, thermally induced diffusion drives Mn to migrate toward the bonding interface. Upon reaching the interface, Mn effectively reduces Cu2O, thereby eliminating its presence at the bonding interface.
Under low-temperature 200℃ and low-pressure 10 MPa bonding conditions, the Cu-Mn alloy self-forming barrier exhibits significantly higher bonding strength and a lower interfacial void ratio compared to conventional fine-grained Cu (FG-Cu). Notably, while Cu2O is observed along the bonding interface in FG-Cu samples, it is completely absent in the Cu-Mn samples. Instead, Mn oxides are formed as a result of the Mn-induced reduction of Cu2O. Because Mn oxides are electrically conductive—unlike the insulating copper oxides—their presence has a negligible impact on the electrical properties and does not severely degrade conductivity.
Furthermore, applying this identical process to coarse-grained Cu (CG-Cu) yields the same beneficial effects, successfully enhancing bonding strength, minimizing interfacial voids and eliminate the Cu oxide. From an industrial manufacturing perspective, doping Mn during the physical vapor deposition (PVD) of the Cu seed layer requires neither the acquisition of new capital equipment nor additional processing steps on separate tools, thereby offering a highly cost-effective solution for high-volume manufacturing.

Abstract:
Indalloy 227 (Sn-20In-2.8Ag, wt%) is a promising low temperature solder for next-generation electronic packaging, but reflow-induced segregation forms transient β-In₃Sn, whose low melting temperature may contribute to partial melting during downstream packaging processes. This study combines experiments and modeling to quantitatively investigate the sub-solidus dissolution and homogenization kinetics of β-In₃Sn within the γ-InSn₄ matrix.
To establish the thermodynamic boundary conditions of the initial state, Scheil solidification simulation was performed using Pandat software with the PanNob2025 database. The simulation predicted the formation of solute-rich β-In3Sn phase at 113°C. To simulate the physical shrinkage and dissolution kinetics of the β-In3Sn particles while avoiding the intensive computational overhead of mesh regeneration inherent to finite element analysis, a sharp-interface moving boundary model was implemented using custom Python code. Assuming a spherical geometry based on scanning electron microscope (SEM) observations, the instantaneous volume fraction was tracked as a function of the shrinking precipitate radius. The model dynamically updated the bulk matrix concentration at each time step, explicitly accounting for local solute enrichment as the interface migrated inward.
The numerical predictions of macroscopic phase fraction evolution were validated against experimental datasets obtained under isothermal holding at 75, 90, and 105 °C. The experimental data points were characterized using low-temperature differential scanning calorimetry (DSC) enthalpy, selected because in-situ microscopic are limited in providing continuous and quantitative phase evaluation within solid matrices at these low temperatures. Low temperature DSC resolves this limitation by measuring the phase transformation heat flow, which directly correlates to the transient phase fraction and yields statistically representative macroscopic kinetics. The calculated simulation curves show quantitative agreement with these enthalpy-derived experimental data points across all evaluated temperatures.
The model captured the gradual deceleration of dissolution characterized by the progressive deceleration of the interface velocity over time. The physical mechanism governing this deceleration is determined by solute redistribution within the finite matrix volume. As the phase transformation proceeds, indium atoms accumulate at the advancing front, leading to transient solute enrichment and localized saturation. Because the matrix volume is limited, this localized accumulation reduces the indium concentration gradient across the reaction front. The reduction in the concentration gradient decreases the chemical potential gradient and the thermodynamic driving force acting at the interphase boundary, resulting in the observed kinetic deceleration.
This study investigated β-In3Sn dissolution kinetics in Indalloy 227 using Pandat and a Python moving boundary model. Validated by low temperature DSC enthalpy data, the simulations predicted a non-linear kinetic retardation where the interface velocity decelerates over time. This deceleration is governed by transient indium enrichment and localized saturation within the finite matrix volume, which flattens the concentration gradient and diminishes the thermodynamic driving force at the interphase boundary.

Abstract:
In microelectronic packages, the formation of intermetallic compounds (IMCs) is necessary to ensure the metallurgical bonding of the solder/pad interface. Insufficient IMC growth accompanying by material defects may lead to poor interfacial bonding, threatening the overall reliability of microelectronic packages. To mitigate excessive IMC growth, minor alloying addition has been widely attempted to control interfacial reactions for years. Recently, minor indium (In) addition (2 wt.%) to tin (Sn) has been prone to suppresses the Cu3Sn growth as well as kirkendall’s voids formation during aging, thereby enhancing solder joint reliability. This study will further probe into the benefits of minor In addition on electromigration reliability of micro joints and the underlying mechanism related to the In effect on the electromigration behavior.

Abstract:
With the explosive growth in artificial intelligence (AI) computing demands, the thermal design power (TDP) of next-generation AI chips and server hardware has drastically surged beyond 2500 W. Because traditional air-cooling technologies have reached their physical limits, liquid-cooled cold plate systems have become a vital paradigm shift in modern thermal management. However, under the dual impact of high-pressure fluid circulation and extreme chip heat flux, cold plates face not only severe thermal dissipation challenges but also substantial structural stress and thermal deformation risks. These risks are primarily induced by fluidic pressure loads and the mismatch of coefficients of thermal expansion (CTE) among heterogeneous materials.
This study investigates the thermal performance and mechanical stress of a high-power cold plate through thermal-fluidic-mechanical coupling simulation. The structure of the cold plate is shown in Figure 1. For a TDP of 2500 W, the simulation applies an inlet temperature of 40°C and a coolant flow rate of 3 LPM. Utilizing FloEFD software, the thermal-fluidic and mechanical simulations are fully coupled within a single platform, streamlining the workflow as illustrated in Figure 2.
Numerical simulation results demonstrate that the integrated microchannel and optimized manifold design successfully stabilize the chip junction temperature within safe limits, exhibiting excellent convective heat transfer performance (Figure 3). Figures 4 and 5 display the velocity and pressure distributions, respectively. However, the temperature gradients and fluid pressure resulting from conjugate heat transfer (CHT) induce significant mechanical stresses. High Von Mises stress concentrations, peaking at approximately 150 MPa, are observed near the constraint regions, specifically around the four-corner mounting bolts and certain structural edges (Figure 6). This localized stress distribution directly correlates with the material's yield strength and long-term fatigue life. Without precise optimization, such thermal stresses can lead to micro-deformations, posing a critical threat of coolant leakage or degradation of the thermal interface material (TIM). By systematically analyzing the trade-offs between geometric fin configurations and stress concentrations, as well as the effects of flow rate and inlet temperature, this research provides crucial co-design guidelines for high-efficiency, high-reliability liquid cooling systems in next-generation AI data centers.

Abstract:
Advanced heterogeneous packages, including chiplet and CoWoS-format structures, are increasingly sensitive to thermo-mechanical warpage caused by material mismatch among dies, interposers, substrates, underfills, solder joints, and molding compounds. This study presents a GPU-accelerated nonlinear thermo-mechanical finite element framework for package-level warpage prediction. The framework integrates incompatible-mode hexahedral solid elements, thermal strain, cure-shrinkage eigenstrain, nonlinear geometry, GPU sparse solving, and automated U3 warpage extraction. A staged validation ladder was established using the NAFEMS LE11 thermal-stress benchmark, the Timoshenko bimetal analytical warpage solution, Abaqus matched-surrogate comparison, ANSYS CoWoS-format proxy comparison, and public Thin FCBGA literature reconstruction. The framework achieved 0.03% error in the NAFEMS LE11 benchmark and 0.04% error in the bimetal benchmark. It also showed less than 0.13% warpage and branch-delta error against Abaqus, and below 0.08% Case A/B warpage error against ANSYS medium-proxy models. A 145k-DOF CoWoS-format proxy model was further solved using the GPU backend without silent CPU fallback. These results indicate that the proposed framework provides a validated foundation for rapid warpage assessment and design-space exploration in advanced packaging.

Abstract:
This work uses integrated 2D materials, either conductive or insulative, to engineer a thermally conductive composite-film encapsulant that preserves circuit signal integrity while exploiting their unique electrical properties to improve on conventional packaging materials. Unlike conventional epoxy (0.2–0.3 W/m·K), the 2D-material composite film is substantially more thermally conductive (10–12 W/m·K in-plane, 1–4 W/m·K off-plane), promoting heat spreading and chip cooling. Through the dielectric loss of its conductive network, the graphene/CNF composite concurrently achieves the lowest jitter, highest oscillation frequency, and most ideal duty cycle, and the SRAM gains an expanded operating margin with reduced current and power, whereas the h-BN composite matches ambient/air solutions for low-loss applications. Heat dissipation and signal integrity, traditionally competing requirements in advanced packaging, are thus addressed concurrently by the 2D composite-film encapsulant, offering a practical pathway for the thermal–electrical co-optimization of high-performance integrated circuits.

Abstract:
This work investigates the effect of underfill materials on the mechanical reliability of VCSEL array packaging for co-packaged optics (CPO) applications. Finite element method (FEM) simulations in ANSYS are used to evaluate the maximum equivalent stress in Au bumps under thermal loading up to 150°C, with and without underfill. Results show that underfill significantly reduces Au bump stress. The lowest stress is achieved when the underfill CTE closely matches that of Au, minimizing thermal mismatch effects. Experimental results further confirm stable light emission after underfill application, demonstrating suitability for AI, HPC, and data center optical interconnect applications.

Abstract:
An AlGaInP-based red micro-LED array for co-packaged optics
(CPO) applications is investigated using ANSYS mechanical thermal
simulation. A flip-chip micro-LED array structure is analyzed under
operating powers from 1 mW to 5 mW. The results show that junction
temperature increases with input power due to self-heating effects,
leading to localized hotspot formation within the emitting region. The
study provides thermal design guidelines for improving the reliability
and thermal management of microLED-based optical transmitters in
future CPO systems.

Abstract:
As electronic packages continue to move toward higher integration density, finer interconnect pitch, and more compact structures, solder joint reliability has become a critical concern in advanced packaging design. In WLCSP and flip-chip packages, solder balls function not only as electrical interconnects but also as mechanical load-bearing components between the chip and substrate. During thermal cycling, the mismatch in the coefficient of thermal expansion among the silicon chip, solder joints, and package substrate induces repeated thermo-mechanical deformation. This deformation promotes plastic strain accumulation in the solder balls, which may lead to fatigue damage, crack initiation, and eventual package failure.
Underfill is commonly applied to improve solder joint reliability by providing mechanical support and redistributing thermal stress. However, conventional full underfill may increase process time, material consumption, and rework difficulty. In addition, flow control during dispensing can become challenging, especially for compact package structures. Therefore, selective reinforcement has become an attractive alternative for improving reliability while maintaining process flexibility. In this study, epoxy flux is investigated as a localized reinforcement material for WLCSP applications, as shown in Fig. 1 and Table 1. Instead of filling the entire gap between the chip and substrate, epoxy flux reinforces the regions near the solder balls where plastic deformation is more likely to accumulate. This approach has the potential to reduce material usage while still providing effective mechanical support.
A three-dimensional finite element model was established to evaluate the effect of epoxy flux design on solder ball reliability. The package model was subjected to a temperature cycling condition from -40°C to 85°C, and SAC305 solder was used as the interconnect material. The equivalent plastic strain increment in the solder balls was selected as the main reliability indicator. Different epoxy flux heights, including 60%, 80%, and 100% of the solder ball height, were compared with the no-flux condition, as shown in Fig. 2. In addition, different area coverage ratios were considered to examine the influence of reinforcement range, as shown in Fig. 3.
The simulation results show that epoxy flux can effectively reduce the equivalent plastic strain increment compared with the no-flux model, as shown in Fig. 4. Among the investigated conditions, the 60% flux height showed the best reliability improvement. When combined with 100% area coverage, the strain increment decreased from 1.479% in the no-flux model to 1.106%, indicating a significant reduction in solder ball plastic deformation. In contrast, although 80% and 100% flux heights also improved the reliability compared with the no-flux case, their effects were less significant than that of the 60% flux height. This suggests that a higher flux height does not necessarily lead to better reinforcement performance. Meanwhile, increasing the area coverage under the same flux height slightly reduced the strain increment, but its influence was relatively limited compared with the effect of flux height.
In conclusion, this study demonstrates that localized epoxy flux reinforcement can enhance solder joint reliability under thermal cycling without requiring full underfill. The results indicate that flux height is the dominant design factor, while area coverage provides a secondary improvement. An appropriate epoxy flux design should balance mechanical support and deformation flexibility, making it a promising reinforcement approach for compact, high-reliability, and cost-sensitive WLCSP applications.

Abstract:
This study presents a numerical prediction framework for investigating solder wetting and bridging behavior in FC-QFN (Flip Chip Quad Flat No-Lead) packages during reflow. Because solder spreading in fine-pitch packages is strongly influenced by interfacial forces, pad geometry, and the arrangement of neighboring bumps, accurately predicting molten solder evolution is essential for mitigating bridging defects and improving package reliability. A computational fluid dynamics model was developed to describe the transient spreading of molten solder. The solder and surrounding air were treated as a two-phase system, and the Volume of Fluid (VOF) method was employed to capture deformation and motion of the gas–liquid interface. Since the solder joint has a micrometer-scale characteristic length and relatively low flow velocity, the spreading process was modeled as laminar flow governed primarily by viscous forces and surface tension.
The reliability of the simulation approach was evaluated through experimental validation. The simulated solder profile was compared with the profile observed after reflow, and good agreement was obtained in terms of the wetting profile, spreading extent, and overall solder morphology. These results demonstrate that the proposed CFD-based method can predict solder wetting behavior in FC-QFN packages and can be used to evaluate process conditions and geometric design parameters before experimental trials.
Based on the validated model, further simulations were performed to investigate solder spreading on bare copper pads using array-based models. First, the influence of bump pitch was examined at pitches of 160, 180, and 200 μm. The results showed that the final wetting profiles and spreading areas were nearly identical for the investigated pitch conditions. In all cases, the molten solder remained confined within the pad boundary, and neither direct solder contact nor bridging was observed. Although decreasing bump pitch did not significantly alter the wetting behavior of an individual solder joint under the present solder volume and wetting conditions, it reduced the clearance between adjacent joints. Therefore, a smaller bump pitch may decrease the geometric tolerance against solder bridging.
The effect of pad size was also investigated using pad dimensions of 90 × 90, 100 × 100, and 120 × 120 μm² while maintaining the same bump pitch. Larger pads provided greater available wetting area and enabled more extensive lateral solder spreading within the pad boundary. In contrast, smaller pads produced a more confined wetting region and a relatively higher final solder profile. These findings indicate that pad size governs the balance between lateral spreading and solder height, thereby affecting the final solder morphology and the clearance available between adjacent solder joints. Overall, the proposed framework provides a practical basis for evaluating wetting behavior and bridging tolerance in fine-pitch FC-QFN package design.

Abstract:

Introducing Resonac co-creation activity for Advanced Packaging technical field.

Co-creation target, strategy, and attractive activities, and so on.

Abstract:

The advantages of glass as a substrate core have been widely publicized. More than two dozen companies are researching glass core substrates and some companies have established pilot lines. While most applications target high performance, large body packages other applications such as RF and image sensors can use lower layer counts and smaller body sizes. This presentation describes the research status today and discusses the remaining challenges. Reliability requirements based on customer needs are presented. Potential solutions to issues are presented. Alternatives to glass core substrates are discussed with updates on options.

Abstract:

As glass core substrates gain momentum for AI, HPC, and advanced chiplet packaging, manufacturing yield has emerged as the key challenge for high-volume adoption. While Through-Glass Via (TGV) formation is widely recognized as a critical process step, the dimensional uniformity of these features ultimately determines the success of downstream metallization, RDL formation, assembly, and reliability performance.

Abstract:

Glass core substrates and glass interposers are displacing organic substrates and silicon interposers for next generation chiplet, HBM, and AI-accelerator packaging, owing to their area, thermal, and interconnect-density advantages. The strategic case is settled; the remaining constraint is yield learning rate, which is governed by a metrology problem that surface-only inspection cannot solve. This paper presents Holotomography (HT) as a non-destructive 3D root-cause metrology layer for glass-substrate high-volume manufacturing (HVM).

Abstract:

Glass and quartz core substrates are increasingly considered key enabling technologies for next-generation semiconductor packaging driven by artificial intelligence (AI), high-performance computing (HPC), advanced networking infrastructure, and heterogeneous integration. Compared to conventional organic laminate substrates, selected glass compositions and quartz materials offer improved dimensional stability, favorable coefficient of thermal expansion (CTE) compatibility with silicon, and reduced dielectric loss. These characteristics support fine-line redistribution layers, increased interconnect density, and improved signal integrity.

This paper presents a requirements-driven technical assessment of glass- and quartz-based substrate technologies. Material-related requirements are analyzed with respect to thermomechanical behavior, dimensional stability, and electrical performance. Through-glass via (TGV) integration is discussed as a key enabling technology for vertical interconnect routing, with particular focus on Laser Induced Glass Etching (LIGE) as a state-of-the-art fabrication approach. Furthermore, metallization requirements for glass substrates are xamined, including adhesion mechanisms, conformal deposition, and reliability considerations.

Special attention is given to multilayer integration and high frequency applications, where low dielectric loss and controlled electromagnetic behavior become increasingly important. Quartz substrates are discussed as a particularly attractive platform for frequencies in the approximate 10–100 GHz regime. Finally, manufacturing scalability, process robustness, and quality control requirements are evaluated as critical factors for future industrial adoption.

Abstract:

This paper presents the SCHMID InfinityBoard, a panel-level packaging technology-platform integrating glass-core substrates with Through Glass Vias (TGVs) and with damascene-patterned ultra-fine vertical interconnects and embedded Redistribution Layer (RDL) to address the scaling, warpage, and performance limitations of advanced IC substrates and AI server boards. The platform combines laser assisted TGV formation, selective etching, scalable metallization, and a proprietary AnyLayer Embedded Trace (ET) process enabling sub-2 µm line/space at panel scale. Reliability, electrical, and mechanical performance demonstrate manufacturing readiness and a compelling cost performance roadmap for next-generation heterogeneous integration.

Abstract:

Opening remarks will highlight the continued evolution of Advanced Electronic Packaging and the convergence of semiconductor packaging, substrates, PCBs, and system-level assembly. The remarks will focus on the critical package-to-PCB interface and connecting the supply chain to identify emerging technology gaps, challenges, and needs that can inform next-generation guidelines and standards.

Abstract:

Driven by the rapid scaling of AI/HPC, the semiconductor industry has shifted toward heterogeneous and chiplet integration, includes 2D large fcBGA-MCM, 2.1D/2.5D integration and 3D packaging solutions. This presentation will highlight the distinct advantages of these advanced packaging and substrate integrations as well as OSAT’s perspective from 2D technologies to 3D technologies.

Abstract:

In response to the rapid advancement and explosive growth of AI and HPC, the technologies and ecosystem of IC substrates and PCBs are undergoing changes essentially. The semiconductor-like evolution of substrates and the substrate-like evolution of PCBs are becoming major trends, and the industry must prepare early to address the challenges ahead.

Abstract:

As larger SoCs and HBM-stacked BGAs are placed on system PCBs, increased package size and weight create SMT assembly challenges, including solder-joint fatigue, board warpage, placement drift and reflow defects. This talk focuses on system-level SMT package-to-board solutions: co-design rules, materials (underfill, board stiffeners), placement and reflow strategies (vacuum nozzles, sequential reflow, fixturing), and practical validation methods to improve reliability and manufacturability for high-volume production.

Abstract:

The discussion session will build on the speaker presentations to explore the key challenges, gaps, and solutions across advanced packaging, substrates, PCBs, and board-level assembly for AI-driven HPC systems. Participants will discuss where greater industry alignment and collaboration are needed to enable next-generation package-to-board integration.

Abstract:

As a large language model (LLM) inference continues to scale in both context length and serving concurrency, the key value (KV) cache has emerged as a dominant system of bottleneck. What was once a localized, GPU resident optimization now places pressure on the entire platform, affecting memory capacity, scheduling behavior, and overall resource utilization.

The initial response to this "KV cache explosion" has naturally focused on memory centric approaches, including capacity growth and disaggregated memory thinking. These solutions are effective in relieving immediate memory pressure, but they also reveal a deeper challenge: KV cache behavior increasingly depends on coordination across CPU, memory, and GPU, rather than on any single component in isolation.

This talk argues that KV cache should be viewed as a system level coordination problem, not merely a memory placement problem. We propose a system level rethinking of hardware roles, in which the CPU evolves beyond a passive data loader and instead plays a more active, coordinating role—shaping how KV cache is handled across the system—while GPUs remain focused on high throughput execution and memory systems provide scalable capacity.

Abstract:

As AI workloads drive increasing power density, direct liquid cooling (DLC) is becoming essential for next-generation datacenter infrastructure. Effective rack-scale cooling requires coordinated monitoring and control across cooling and power components. This presentation introduces Intel’s Intelligent Rack Liquid Cooling Control Center architecture, integrating CDU, flow, pressure, and thermal sensors, energy control valves, leakage detection, and PDU telemetry through open Modbus RTU and TCP/IP protocols. Multi-layer intelligent event control enables real-time detection and localization of leakage and thermal anomalies at rack and node levels, supporting automated valve control, power management, thermal management, and flow balancing. A layered software architecture spanning device communication, data acquisition, monitoring, and visualization enables scalable deployment, system-level debugging, and validation. The presentation also demonstrates the rack implementation and opportunities to scale from single-rack validation to higher-density, pod-level deployments through ecosystem collaboration and open interfaces.

Abstract:

As artificial-intelligence (AI) and highperformance-computing workloads drive rack-level directcurrent (DC) distribution into the thousands-of-amperes level, the conventional thermal-unaware modeling of power integrity (PI) systematically under-predicts both IR drop and Joule heating, because the resistivity of copper is temperature dependent. This paper presents a rack-level power busbar Multiphysics methodology that couples three-dimensional (3D) electro-thermal (E/T) field solving with computational fluid dynamics (CFD) of Celsius Thermal Solver to deliver thermal-aware power integrity (PI) results. In terms of 48 V busbar assembly feeding six voltageregulator modules (VRMs) and twenty-two current sinks, neglecting temperature dependence is shown to underestimate the bus voltage drop by 21% and the dissipated power by approximately 20%. A two-way E/T–CFD iteration further raises predicted Joule heating about 10% and worsens IR drop about 9% relative to default thermal boundary conditions, while power connectors of VRMs/Sinks are identified as the dominant contributor to IR drop along with power busbar. The results establish that 2-ways iteration co-simulation is required to address reliability concern of temperature rising and power dissipation that implication from system power busbar architecture.

Abstract:

To accommodate the increasing demand for larger memory capacity and a growing number of PCI Express (PCIe) ports, the pin count of the CPU (Central Processing Unit) in the Host Processor Module (HPM) has significantly increased across successive generations. However, form factor constraints require a trade-off between pin pitch and package size. While a larger pin pitch eases PCB manufacturing complexity and improves signal integrity (SI), it inevitably increases the package footprint. Consequently, the trend toward finer pitch designs has become unavoidable, introducing substantial challenges in both PCB (Printed Circuit Board) fabrication and SI performance. Both experimental measurements and simulation results demonstrate that maintaining controlled trace impedance (Z) becomes increasingly challenging under fine-pitch conditions, resulting in channel performance degradation and observable eye diagram degradation in both PCIe and DDR interfaces, highlighting that manufacturing limitations in fine-pitch PCB processes pose a critical bottleneck to signal integrity in next-generation HPM designs.

Abstract:

This presentation eleborates the systematic Electrical Validation (EV) methodology to optimize high-speed interconnect (HSIO) channel design to ensure the AI server design and high-speed signal quality are meeting the specification especially when operating at higher speed PCIe Gen6 64GT/s with Pulse Modulation Amplitude 4 (PAM4) encoding and beyond

Abstract:

As data rates rise in the AI era, high-speed interconnect channel design becomes ever more critical for PCB designers.
This section elaborates on using Agentic AI to review PCB high-speed routing design and provide real-time risk assessment and trade-off suggestion. This methodology helps reduce PCB development time and ensure low signal-integrity risk.

Abstract:

As package body sizes continue to increase, the industry must explore all options to manage both cost and yield. Panel-level packaging was originally adopted for some smaller, simpler applications. Now, in this second wave of panel-level packaging, advancements have been made that may support larger, complex packages built on panels. However, there are a multitude of panel sizes currently being pursued across the industry, with no clear answer on which panel size may be optimal. This analysis focuses on two panel sizes: 310x310mm and 510x515mm, with a 300mm wafer baseline included for comparison. Activity-based cost modeling is used to compare processing costs for 50x50mm, 100x100mm, and 150x150mm molded RDL interposers across all three formats. Key cost drivers and design trade-offs are identified, and the impact of yield is included.

Abstract:
In recent years, the advancement of generative AI and large language models (LLMs) has been enabled not only by increased chip computational performance, but also by high-speed interconnects between chips. To address future demands for higher I/O density, redistribution layer (RDL) manufacturing faces challenges in achieving finer patterning, improved signal transmission efficiency, and enhanced scalability. To overcome these challenges, numerous studies have reported a transition from silicon interposers to organic interposers.
RDLs in organic interposers are generally patterned using lithographic processes with photosensitive dielectric materials. However, photosensitive materials present a challenge in achieving fine patterning (line/space ≤ 2/2 μm) while maintaining material properties. By adopting non-photosensitive dielectric materials, it becomes possible to preserve and improve material characteristics. However, this introduces a new challenge in achieving fine patterning without the use of conventional lithography.
Furthermore, RDLs are typically formed using a semi-additive process (SAP), which has been widely implemented in the formation of build-up layers in semiconductor package substrates. However, in applications requiring finer patterning, SAP presents several issues, including pattern collapse caused by undercut during seed layer etching and critical dimension (CD) errors due to surface waviness generated during multilayer stacking.
To address these challenges, fine patterning of non-photosensitive dielectric materials using KrF excimer laser ablation is considered an effective solution. Since the material does not need to be photosensitive, it allows for greater focus on improving material properties such as dielectric constant. Additionally, the short wavelength of the KrF excimer laser makes it well-suited for high-resolution microfabrication. The equipment system employs a mask pattern reduction projection method, enabling batch processing over a large area. It can fabricate not only vias but also a wide variety of pattern geometries.
Compared to conventional galvanometer mirror–based laser processing systems that machine holes sequentially, this system can maintain high productivity even as pattern density increases. Furthermore, because it utilizes mask transfer, it is well suited for improving various accuracy parameters, including alignment precision.
Moreover, precise control of processing depth can be achieved by adjusting the number of laser pulses.
This capability enables compatibility with the dual damascene process, in which vias and trenches are simultaneously filled with copper plating. This process has a proven track record in front-end semiconductor manufacturing and offers advantages such as eliminating the seed layer etching step and suppressing surface waviness through planarization by chemical mechanical polishing (CMP). As a result, this approach provides a solution to conventional process challenges while achieving both miniaturization and improved transmission performance.
In this study, fine patterning was performed on non-photosensitive dielectric materials using a mask projection system equipped with a high-power KrF excimer laser for ablation. As a result, via diameters of 3 μm and line/space of 2/2 μm were successfully fabricated, with taper angles of approximately 85° achieved in both cases. These results demonstrate that KrF excimer laser ablation enables fine RDL formation even with non-photosensitive dielectric materials and is compatible with the dual damascene process.

Abstract:
This study employs empirical equivalent material property models to investigate the influence of copper routing pattern geometry on the equivalent Young's modulus of a redistribution line-like (RDL-like) structure in advanced packaging and to develop pattern-correction models that more accurately predict the effective material properties of complex routing structures.
Classical analytical approaches, including the rule of mixtures (ROM) and inverse rule of mixtures (IROM), are adequate for unidirectional patterns but fail to account for the effects of trace geometry, directionality, and connectivity in complex routing configurations, resulting in relatively large prediction errors. In this study, a set of standard routing patterns representative of advanced packaging layouts is adopted as the basis for FEM homogenization modeling using ANSYS APDL. Equivalent material properties are evaluated across a range of copper volume fractions, pattern arrangements, and geometric parameters, and the applicability of classical analytical models (ROM, IROM, and the Halpin-Tsai model) is assessed.
The results show that the equivalent Young's modulus of diagonal-type and sinusoidal-waveform trace patterns is governed not only by the copper volume fraction, but is also coupled with the wire inclination angle and waveform amplitude. To capture this pattern effect, an angular correction function and geometric correction terms are introduced to calibrate the semi-empirical Halpin-Tsai model, which accounts for the influence of trace directionality on stiffness and reduces the prediction error of conventional analytical models.
The corrected equivalent model is further applied to the mechanical analysis of practical redistribution layer (RDL) structures, where finite-element simulations are conducted to compare mechanical responses between the equivalent and full-geometry models. Results show that the equivalent model can substitute for complex copper trace patterns while maintaining satisfactory prediction accuracy, thereby reducing both degrees of freedom and computational cost. Across various RDL trace configurations and copper distribution conditions, the proposed model provides consistent predictions of equivalent stiffness, making it suitable for stress assessment and rapid design verification in advanced packaging.
In addition, the pattern-property database built in this study can be combined with image recognition and artificial intelligence techniques in future work to predict equivalent material properties directly from routing geometry.
Keywords – Advanced packaging; Finite element method (FEM); RDL-like, ROM, IROM

Abstract:
As Moore’s Law gradually approaches its physical limits and the demand for high performance in artificial intelligence (AI) chips continues to increase, advanced packaging has become an important approach for improving overall system performance. Fan-out packaging redistributes chip I/O terminals through redistribution layer (RDL), thereby increasing the number of I/O connections and enhancing layout flexibility. Depending on the carrier format, fan-out packaging can be classified into fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP). Compared with wafer-level packaging, panel-level packaging provides higher material utilization and lower manufacturing costs. However, its larger structural dimensions also result in more significant warpage.

During packaging processes, multiple thermal cycles cause stress accumulation and warpage due to mismatches in the coefficients of thermal expansion (CTE) among different materials. Warpage may affect alignment accuracy, product reliability, and manufacturing yield. Therefore, the rapid and accurate prediction of warpage has become an important issue in advanced packaging.

This study first investigates mesh modeling strategies for FOPLP structures and validates the models using multiple sets of experimental measurements. The prediction accuracy of a uniform mesh model is compared with that of a hybrid mesh model incorporating local mesh refinement at the four corners. The results show that the uniform mesh model yields an average error of 9.64%, whereas the hybrid mesh model reduces the average error to 3.44%. This demonstrates that local mesh refinement effectively captures the stress and deformation behavior in the corner regions, thereby improving the accuracy of FOPLP warpage prediction.

For multilayer RDL structures, equivalent structures and material properties are employed to avoid the excessive computational cost associated with directly modeling fine copper traces. The average reference temperature method is then introduced into the hybrid mesh model. The results indicate that the conventional reference temperature method produces an average error of 72.33%, whereas the average reference temperature method reduces the error to 3.44%, demonstrating its suitability for thermal stress analysis of multilayer RDL structures.

Based on the validated finite element model, a large simulation database is established, and a quarter-symmetry model is employed to reduce modeling and computational costs. Machine learning methods are subsequently integrated to predict not only the maximum warpage value but also the global warpage profile of the entire FOPLP structure.

Furthermore, a recursive prediction model is developed to progressively predict the global warpage of subsequent layers based on the prediction result of the preceding layer. This approach reduces the required amount of data and model development costs while achieving an average error of only 3.70% compared with experimental measurements. The developed model can rapidly and accurately predict global warpage and can be further applied to parameter analysis and optimization to identify appropriate process conditions for warpage reduction.

In summary, this study integrates finite element analysis and machine learning to establish a comprehensive framework for global warpage prediction and parameter optimization. The hybrid mesh and average reference temperature methods improve simulation accuracy, while the recursive machine learning model enables highly accurate warpage prediction and packaging design optimization with reduced computational costs.

Abstract:
ABSTRACT
As the demands of artificial intelligence, high-performance computing, and high-speed communication increase, advanced packaging has become a key approach for improving chip performance and system integration. Fan-out panel-level packaging (FOPLP) has attracted attention because of its high input/output density, material utilization, and large-area manufacturing potential. In FOPLP, redistribution layers (RDLs) rearrange chip I/O terminals to improve layout flexibility. However, as RDL layers increase and circuit patterns become more complex, local surface topography variations become more significant, affecting subsequent stacking, process stability, and surface planarity.
In multi-layer RDL fabrication, polyimide (PI) is commonly used as a dielectric material. During post-curing, PI shrinkage, copper trace constraint, and local pattern-density variation can induce dishing deformation. PI dishing is affected by linewidth, spacing, copper coverage, and circuit geometry, and may accumulate during multi-layer stacking. Although finite element analysis (FEA) can evaluate PI dishing and surface topography, modeling numerous RDL regions over a full panel requires considerable preprocessing and computational time. Therefore, a fast prediction method is required for multi-layer RDL process design.
This study integrates FEA and deep learning to establish a prediction framework for PI dishing and surface topography in multi-layer RDL processes. Regions of interest (ROIs) with different circuit features are extracted from a single-unit circuit layout, and corresponding RDL finite element models are constructed using Moldex3D. The simulated Z-direction displacement after PI post-curing is used as training and validation data. RDL layouts are converted into binary images, while simulated displacement results are transformed into image-format datasets, allowing the models to learn the relationship between circuit geometry, PI dishing, and surface topography.
For single-layer RDL prediction, convolutional neural network (CNN) and U-Net models are developed, and their prediction results are compared. The CNN model extracts geometric features from RDL patterns through convolution operations, whereas the U-Net model, with its encoder–decoder structure and skip connections, preserves local image details and is suitable for pixel-wise surface topography prediction. This comparison evaluates different architectures in predicting edges, corners, and high-gradient deformation areas.
After completing the single-layer prediction model, this study extends the framework to multi-layer RDL processes. To describe layer-by-layer surface topography evolution, a recursive U-Net model is developed. The current RDL layout and previous-layer height map are used as inputs, and the Z-direction displacement after the current process is predicted as the output. The predicted result of one layer is then used as the input for the next layer, enabling sequential prediction of surface topography in multi-layer RDL structures.
The results show that both CNN and U-Net models can capture the relationship between RDL geometry and PI dishing distribution, while U-Net provides better performance in local detail preservation and surface reconstruction. Therefore, U-Net is adopted as the main architecture for multi-layer and recursive prediction. Finally, a user interface (UI) integrating full-panel RDL layouts and the trained model is developed to rapidly predict surface topography after multi-layer RDL stacking. The proposed platform can support RDL process development, layout evaluation, and surface planarity improvement for FOPLP applications.
Keywords: Fan-Out Panel-Level Packaging (FOPLP), Redistribution layer (RDL) process, Polyimide (PI), Convolutional neural network (CNN), Surface topography.

Abstract:
Glass substrates have emerged as a promising material for next-generation semiconductor packaging due to their ultra-smooth surfaces, excellent thermal and mechanical stability, low coefficient of thermal expansion, and superior dimensional control. Compared with conventional organic substrates, glass also exhibits significantly lower dielectric loss at high frequencies, making it highly attractive for advanced computing, artificial intelligence (AI), and high-speed communication applications. In addition, glass substrates are cost-effective, available in large panel sizes, and free from material scarcity concerns. These advantages position glass as a key enabling material for future semiconductor packaging and an important technology for extending Moore’s Law.
　　Despite these benefits, several technological barriers remain before glass substrates can be widely adopted in advanced packaging. One of the challenges is the development of reliable metallization processes with strong interfacial adhesion, as poor adhesion can significantly compromise both circuit performance and long-term package reliability. To address this challenge, our group has developed a wet metallization process based on electroless deposition (ELP) Cu using a self-adsorbing palladium nanoparticle catalyst capped with 3-aminopropyltriethoxysilane (APTES) in combination with a titanium dioxide (TiO2) adhesion-promoting layer (APL). The TiO2 APL provides a nanoporous structure that facilitates mechanical interlocking between the deposited copper and the underlying glass substrate. As a result, electroless copper layers with peel strengths exceeding 1300 gf/cm have been achieved on alkali-containing glass substrates.
　　In this work, the effects of TiO2 APL processing parameters on ELP Cu adhesion and reliability are systematically investigated. The influence of TiO2 thickness, pore morphology, and post-deposition thermal treatment conditions is examined to establish the structure–property relationships governing interfacial bonding. In addition, TiO2 APLs fabricated by spin coating are compared with those prepared by atomic layer deposition (ALD) to elucidate the role of film density, porosity, and microstructure in adhesion enhancement. Peel-strength measurements, microstructural characterization, and reliability evaluations are conducted to identify the optimal APL architecture for robust metallization.
　　The results provide important insights into the adhesion mechanisms of electroless copper on glass and demonstrate the critical role of nanoporous TiO2 interlayers in achieving high-reliability metallization. This study contributes to the development of scalable, cost-effective wet metallization technologies for advanced glass-based semiconductor packaging applications.

Abstract:
The exponential growth of data-intensive applications, particularly within the demanding domains of high-performance computing (HPC) and artificial intelligence, is generating an insatiable demand for data throughput that has pushed traditional architectures to their limits. This has created an unprecedented and critical I/O bottleneck on the communication pathways connecting logic and memory. To surmount this fundamental performance barrier, the semiconductor industry is strategically pivoting towards heterogeneous integration schemes, with a primary focus on advanced packaging that combines System-on-Chip (SoC) logic with High Bandwidth Memory (HBM) modules. The ultimate success of these complex, multi-chip architectures is critically dependent on the ability to fabricate ultra-high-density redistribution layers (RDLs), the intricate nervous system of the package, which must deliver both immense bandwidth and superior energy efficiency.
Conventional mask-based lithography, a cornerstone of semiconductor fabrication, struggles to compensate for the non-linear substrate distortions inherent to large-format wafers used in advanced packaging. This forces the use of conservative design rules, such as oversized landing pads and wider traces, which directly limits routing density and becomes a primary source of yield loss from registration errors. This paper introduces a production-ready digital lithography technology that operates without a physical mask. At its core, the technology performs real-time topological mapping of the substrate, adjusting the projected pattern on a die-by-die basis to dynamically compensate for wafer warpage and distortion (Fig. 1). The process performance enabled by this adaptive approach is exceptional. We demonstrate robust fabrication of 1 µm line/space patterns, 2 µm vias, and 3 µm landing pads on 300mm wafers. Critically, this is achieved with an overlay accuracy better than 0.25 µm, a metric essential for multi-layer RDL builds. This tight registration control allows for the aggressive scaling of via landing pads, directly enabling denser vertical interconnects while mitigating a primary source of yield-killing electrical opens. Furthermore, the process exhibits a within-wafer critical dimension uniformity of <3%. This level of control ensures consistent electrical characteristics (e.g., resistance, capacitance) across all interconnects on the wafer, broadening the process window and guaranteeing predictable, high-speed signal integrity for every die. The combination of these tightly controlled process capabilities facilitates a transformative, greater-than-four-fold improvement in interconnect density over conventional 2/2 µm RDL nodes, without compromising manufacturing yield or long-term system reliability (Fig. 2). This advancement provides a critical and economically viable manufacturing pathway for the future of advanced packaging. By providing manufacturing certainty for finely pitched interconnects and minimized via structures, it fundamentally empowers system architects to pursue designs previously considered unmanufacturable, unlocking a new generation of heterogeneous systems with superior bandwidth efficiency, reduced power consumption, and greater functional density.

Abstract:

Ensuring the thermomechanical reliability of microelectronic packaging is a critical manufacturing challenge as the industry demands highly efficient hardware for next-generation computing. This presentation explores practical, data-driven methodologies, specifically Finite Element Modelling (FEM) and Machine Learning (ML), to predict and mitigate reliability issues at both the macro-package level and the micro-interconnect level. At the package level, we track out-of-plane deformation sequentially across manufacturing milestones to evaluate warpage evolution in Very Fine Ball Grid Array (VFBGA) and Mold Array Process Ball Grid Array (MAPBGA) formats. Utilizing advanced predictive FEM, we capture the complex mechanics driving warpage. Targeted sensitivity analyses isolate dominant variables, such as Die Attach Film (DAF) thickness, die loading, and Epoxy Molding Compound (EMC) properties, demonstrating how virtual optimization can proactively reduce final package deformation. Scaling down to the interconnect level, the mechanical integrity of lead-free solder joints under shear loading is examined. We investigate the microstructural evolution of SAC305 and low-temperature Sn-Bi solders modified with minor alloying elements (Ni, Al, Co) via novel flux doping and conventional techniques. By coupling experimental lap shear and nanoindentation testing with computational stress analysis, we map critical stress concentrations near brittle Intermetallic Compound (IMC) layers. To address the highly non-linear relationships between fabrication methods, strain rates, reflow temperatures, and alloy compositions, Artificial Neural Network (ANN) and Random Forest (RF) machine learning models are deployed. These ML frameworks successfully predict critical outputs, including joint shear strength, IMC thickness, and localized nanomechanical properties, providing a powerful, real-time optimization tool for manufacturing reliability.

Abstract:
The increasing demands for thermal management and mechanical reliability in semiconductor devices have led to growing interests in advanced packaging architectures and materials. One of the key challenges in advanced packaging is heat dissipation, driven by the persistent increases in power density, diverse functionality, and package size. Existing materials used in the packaging structure are progressively prone to insufficiencies in thermo-mechanical reliability and power delivery. Glass substrates containing through glass vias (TGVs) have emerged as promising solutions, due to their low dielectric loss, excellent dimensional stability, and tunable coefficient of thermal expansion (CTE) to better match those of the surrounding materials. TGVs also offer improved signal integrity compared to through silicon vias (TSVs). More recently, silicon carbide (SiC) interposers or substrates have gained recognition, due especially to its much higher thermal conductivity than other interposer materials such as silicon and glass. More effective heat spreading in both the lateral and through-thickness directions can thus be achieved by SiC. Its superior thermal stability and high-temperature mechanical properties also help support large area heterogeneous assemblies.

While interposers of different materials have their respective advantages, thermal stresses induced by the mismatch in CTE always exist inside the structure itself. The through-substrate vias are primarily made of copper which has a relatively high CTE (~17×10^(-6) K^(-1)) compared to those of Si (~3×10^(-6) K^(-1)), glass (~ 0 to 9×10^(-6) K^(-1)) and SiC (~4.5×10^(-6) K^(-1)). Upon cooling down from the fabrication or annealing temperature, stresses are generated in both the vias and surrounding matrix, leading to possible damages such as void formation in the metal, delamination at the interface, and cracking in the brittle matrix. The evolution of thermal stresses, however, is not solely determined by the CTE difference between dissimilar materials. To reach mechanical equilibrium, the internal deformation process also depends on the stiffness and possible plastic yielding of the constituents. Computational modeling is therefore an important tool for such analyses.

In this presentation, we shed light on the thermal stress and deformation fields through a comparative numerical study, using three different interposers (substrates) containing through-thickness copper vias. Systematic finite element analyses are conducted, assuming regular square arrays of copper vias inside the Si, glass, and SiC substrates. Representative via–matrix models with various via concentrations are constructed, with appropriate boundary conditions applied to ensure symmetry and periodicity during thermal cooling. The simulation results show that, with the same via concentration, the hydrostatic tension in copper, interfacial shear stress, and maximum principal stress in the matrix are much greater in the case of SiC than the cases of Si and glass. This is due to the notably high stiffness of SiC substrate. Significantly higher plastic strains in copper also exist when the surrounding material is SiC. The overall lateral dimensional change of the interposer increases with the via fraction, but the extent of increase differs for the three substrate materials. Implications of the numerical findings on potential thermo-mechanical reliability of the different interposer structures are discussed.

Abstract:
SOFTWARE ARCHITECTURE
Co-Packaged Optics (CPO) often involves integration of photonics channels with different wavelengths and spectral responses [1]. This requires bespoke design of silicon photonics (SiPh) components, including the grating couplers for each channel. In this work, we developed a deep neural network (DNN) to custom design the mixed pitch grating couplers from user’s requirements.
Fig. 1 (in the attached pdf) shows its software architecture. The grating couplers are 4-region mixed pitch gratings on silicon-on-insulator (SOI) platform, with similar concepts as their 2-region counterpart reported previously [2]. Mixed pitch grating couplers are selected for optimal bandwidth. For the training data, we used finite-difference time-domain (FDTD) technique to simulate ~10,000 sets of data, with grating parameters and their corresponding power-wavelength spectrum as the output and input, respectively. Users can specify the desired peak wavelength and the full-width half-maximum (FWHM) values. A Gaussian curve will be generated and used as the input of the model. The model will suggest a set of grating parameters for FDTD simulation to obtain the spectral response. The mean absolute error (MAE) between the Gaussian curve and the FDTD-simulated spectra will then be computed. If the MAE is satisfactory, a GDSII layout will be automatically generated.

MODEL PERFORMANCE
Fig. 2(a) (in the attached pdf) shows the typical performance of the trained DNN model. We specified the peak wavelength at 1.58 µm with FWHM = 0.124 µm to undergo the process described in the previous section. The Gaussian, simulated, and measured curves (experimental setup in Fig. 2(c) and (d) in the attached pdf) have similar morphology. The FWHM values of the simulated and measured curves are 0.110 and 0.124 µm (0.14 and ~0 µm error); while the peak wavelengths are 1.575 and 1.28 µm (0.005 and ~0 µm error). To further test the model performance, we used ~1,000 combinations of FWHM = 0.08 – 0.145 µm and peak wavelengths = 1.535 – 1.615 µm as inputs. The MAEs between the Gaussian and FDTD-simulated curves are computed (Fig. 2(d) in the attached pdf). In general, the model performs better at higher peak wavelengths between 1.57 to 1.6 µm. and FWHM between 0.95 to 0.115 µm. The error of this region ranges from 0.6 – 4%. This DNN technique can be further expanded to other SiPh components in CPO applications, including photonics switches, wavelength filters, and photodetectors. We have also prepared a graphical-user interface for model usage, where the demonstration video of the usage is shown in ref. [3].

REFERENCES
[1] M. Tan et al., “Co-packaged optics (CPO): status, challenges, and solutions,” Dec. 01, 2023, Higher Education Press Limited Company. doi: 10.1007/s12200-022-00055-y.
[2] Y. D. Lim, P. Zhao, L. Guidoni, J. P. Likforman, and C. S. Tan, “Development of Mixed Pitch Grating for the Optical Addressing of Trapped Sr+ Ions with Data Analysis Techniques,” Opt. Express, vol. 31, no. 15, pp. 23801–23812, 2023, doi: 10.1109/JPHOT.2023.3281134.
[3] Y. D. Lim, “AI-Native Design: Mixed Pitch Grating Coupler | InPhAI Demo,” YouTube. Accessed: Jun. 11, 2026. [Online]. Available: https://www.youtube.com/watch?v=L4-jOLQg2Tk

Abstract:
This study proposes a physics informed encoder-decoder model that predicts key material properties influencing warpage in semiconductor package substrates directly from process conditions. By integrating this model with a data driven pattern profile prediction model, we develop a process window design framework that recommends process windows meeting multiple property requirements simultaneously, thereby reducing packaging development costs.
The rapid increase in data traffic has intensified demands for smaller, higher performance electronic devices, accelerating the development of high density packaging technologies in back end processes. In package design, finite element analysis (FEA) is widely used to evaluate warpage and stress distributions, and there is a need to co optimize structural and material design with advanced substrate manufacturing processes. As functional materials increasingly dominate thermal stresses and interconnection reliability, it is essential to optimize materials and design robust process windows. However, the expansion of the material–process design space, along with reliance on experimentation, has made rising development costs a major challenge.
Machine learning is a powerful tool for modeling complex relationships among multivariate data, but in back end packaging processes, a system that consistently predicts material properties from process conditions has not yet been established. Moreover, many thermomechanical properties are high‑dimensional, posing challenges for prediction.
To address these challenges, we propose a data driven process window design framework that integrates thermomechanical property and pattern profile prediction models. Each property is predicted by a regression model relating it to material and process conditions. Viscoelastic behavior measured by dynamic mechanical analysis (DMA) is predicted using a physics informed model, composed of an encoder-decoder module and a parameter prediction module. The encoder compresses DMA data into low dimensional Prony-series parameters, and the decoder reconstructs the DMA response from these parameters based on the generalized Maxwell model. The parameter prediction module is constructed to predict the encoded parameters from process conditions, and the corresponding DMA response can be obtained via the decoder. This model consistently predicts viscoelastic behavior from process conditions across multiple process steps while retaining physical interpretability.
A case study was conducted on a black-matte solder resist (SR), a permanent insulating layer on the outermost surface of the substrates. SR is a negative type photosensitive functional material whose properties are influenced by multiple interacting processes, and appropriate process design is critical for reliability. We constructed prediction models using DMA, coefficient of thermal expansion (CTE), and cross sectional profile data, then identified a process window that simultaneously satisfied the FEA derived thermomechanical requirements for warpage reduction and the specified pattern profiles for both conductors and organic substrates. This approach reduced the prototyping workload by 75% compared with conventional trial-and-error methods.
This framework is expected to reduce development costs by enabling front-loading and minimizing rework in package substrate manufacturing. Expanding the application to a broad range of functional materials and realizing end‑to‑end analysis from optimal process conditions through to device‑level physics simulations could enable efficient exploration of material and process conditions that satisfy the required characteristics of semiconductor package substrates. We expect that establishing such an integrated analysis platform will contribute to the development of the semiconductor packaging market.

Abstract:
Efficient access to equipment maintenance records is critical for manufacturing operations, yet practical queries—cross-field aggregation, statistical computation, and part-level summarization—still rely on manual data export and spreadsheet processing. We present an on-premise Equipment Maintenance System Chatbot (EMS Chatbot), a factory-deployable question-answering system that combines large language models with structured filtering and hybrid retrieval. Unlike conventional retrieval-only RAG systems, EMS Chatbot decomposes a natural-language query into time-parsing, intent analysis, retrieval, and multi-step statistical planning, allowing it to answer questions that require computation rather than passage lookup alone. For retrieval, structured fields first restrict candidate records, while vector and BM25 keyword retrieval run in parallel, followed by reranking. For computation, a planning module maps each query to an ordered sequence of tool calls. LoRA fine-tuning is applied to a 7B model for time parsing and tool selection, reducing reliance on a larger model for these structured subtasks. We evaluate EMS Chatbot on real factory maintenance queries. The fine-tuned 7B model reaches 95.92% accuracy on 49 time-parsing cases and 96% on 50 task-planning (tool-orchestration) cases, while the end-to-end hybrid retrieval pipeline reaches 90% on 30 RAG cases. In a representative workflow, processing time drops from about 60 minutes to about 7 seconds, demonstrating a significant reduction in manual effort under tight on-premise data security constraints.

Abstract:
Fan-out panel-level packaging (FOPLP) is a promising route to low-cost, large-area, high-density, high-frequency multi-chip integration. In a chip-first flow, dies are bonded to a carrier before dielectric build-up and redistribution-layer (RDL) formation, enabling fine-pitch routing but introducing die-placement variation from bonding accuracy, process disturbance, and downstream material processing. Once die shift occurs, the nominal RDL layout no longer matches the actual pad locations. Maskless lithography can restore physical connectivity by re-routing to the measured pad positions, but for coplanar waveguide (CPW) interconnects, geometric reconnection alone is insufficient: routing length, bending, line width (LW), and line spacing (LS) all shape impedance matching, return loss, and insertion loss, so a geometrically corrected trace can still exhibit degraded high-frequency response.

This work proposes an AI-assisted compensation method that selects LW and LS for die-shifted CPW interconnects in FOPLP. A reference CPW is modeled under the no-shift condition, and electromagnetic simulations quantify how die shift alters S11 and S21 — with the deviation most pronounced in S21. To avoid case-by-case simulation in production, we build an offline compensation database: offset coordinates (Δx, Δy, Δθ) are combined with candidate LW/LS settings; each combination is converted to a GDS layout, simulated in COMSOL, and screened by a weighted-RMSE criterion on S11 and S21 (with additional weights at 5 and 10 GHz). Accepted settings are stored in a K-nearest-neighbor (KNN) database, so a measured die shift maps directly to a compensation setting at runtime.

For a 60 μm x–y shift under a 5% weighted-deviation criterion, the nominal LW/LS = 2/2 μm fails, while (4, 2) μm and (2, 1) μm satisfy both S11 and S21 criteria. The method extends die-shift correction from geometric reconnection to high-frequency-aware compensation, and integrates with maskless lithography to address a key bottleneck for high-frequency FOPLP.

Abstract:

Surface-activated bonding (SAB) is a method of bonding activated solid surfaces using adhesive forces between surface atoms. It requires extremely smooth bonding surfaces (root-mean-square roughness: 1 nm or less), and there is a major issue of difficulty in bonding when ultra-precision polishing processes, such as chemical mechanical polishing (CMP), cannot be applied.
In response, we developed a smoothing method using additive processing by combining template stripping and surface-activated bonding. We demonstrated the smoothing of plated Au surfaces for direct Au bonding at room temperature.

Abstract:
As semiconductor packaging technologies continue to evolve toward higher integration densities, wafer-to-wafer (W2W) bonding has emerged as a key enabling process for advanced three-dimensional (3D) integration, heterogeneous integration, and hybrid bonding applications. The success of W2W bonding strongly depends on the surface topography and edge geometry of the wafers being bonded. Among various geometric parameters, wafer edge roll-off (ERO), defined as the gradual deviation of wafer surface height near the wafer edge, has become an increasingly critical factor affecting bonding yield, overlay accuracy, wafer handling stability, and post-bonding reliability. Excessive edge roll-off may induce localized gaps, non-uniform bonding pressure distribution, void formation, and edge-related defects, ultimately reducing manufacturing yield and device performance. Consequently, accurate characterization of ERO at nanometer-scale resolution has become an essential metrology requirement for high-volume semiconductor manufacturing.

Various metrology techniques have been investigated for ERO measurement. Atomic Force Microscopy (AFM) is widely recognized for its exceptional vertical resolution at the nanometer and sub-nanometer scale. AFM enables detailed characterization of local surface morphology and provides highly accurate topographic information. However, its practical application to ERO inspection in production environments is limited by its relatively small field of view, slow scanning speed, and difficulty in measuring long edge profiles over several millimeters. As semiconductor manufacturing increasingly demands full-wafer and high-throughput inspection capabilities, AFM is primarily utilized for reference measurements and localized verification rather than inline process monitoring.

Optical triangulation techniques represent another widely adopted approach for measuring wafer edge geometry. These methods offer non-contact operation, relatively simple system architectures, and fast acquisition speeds. Optical triangulation can efficiently measure large-scale geometric profiles and is often used for wafer edge inspection and dimensional metrology. Nevertheless, its measurement accuracy is fundamentally constrained by spot size, sensor resolution, and triangulation geometry. Furthermore, measurement uncertainty tends to increase when inspecting highly reflective semiconductor surfaces or when nanometer-level height precision is required. These limitations restrict the applicability of optical triangulation for advanced hybrid bonding processes where extremely tight topography specifications must be satisfied.

Interferometric metrology has emerged as a promising solution for overcoming the limitations of existing measurement techniques. By exploiting optical phase information, interferometric systems provide nanometer-scale vertical resolution while maintaining a relatively large measurement field and high acquisition efficiency. Various interferometric approaches, including phase-shifting interferometry (PSI), white-light interferometry (WLI), and coherence scanning interferometry (CSI), have demonstrated excellent capability in measuring ultra-flat semiconductor surfaces. However, the measurement of wafer edge roll-off presents unique challenges due to steep local slopes, large measurement ranges, and the requirement for high-speed operation compatible with mass-production environments.

In this study, a high-precision and high-speed interferometric metrology system was developed specifically for quantitative ERO characterization in wafer-to-wafer bonding applications. The proposed system combines advanced interferometric measurement principles with optimized optical design and dedicated signal processing algorithms to achieve accurate edge profile reconstruction over extended measurement regions. Unlike conventional interferometric systems that are often optimized for central wafer inspection, the developed architecture was designed to maintain measurement fidelity in the wafer edge region where topographic gradients become increasingly significant.

The developed methodology enables nanometer-scale vertical measurement precision while covering the entire ERO region within a single measurement sequence. Through optimized acquisition strategies and high-speed image processing, the system significantly reduces measurement time compared with traditional scanning-based methods. Experimental evaluations were performed using semiconductor wafers representative of advanced packaging processes. The measurement results demonstrated excellent repeatability, reproducibility, and correlation with reference metrology methods. The proposed interferometric approach successfully captured subtle edge profile variations that are difficult to resolve using conventional optical triangulation systems while achieving substantially higher throughput than AFM-based measurements.

Furthermore, the obtained ERO profiles provided valuable quantitative information for process optimization and quality control in wafer bonding production lines. The ability to rapidly characterize edge topography enables early detection of process-induced variations, supports wafer quality classification, and contributes to improved bonding yield prediction. The measurement data can also serve as an important input for process modeling and predictive manufacturing frameworks aimed at reducing defect formation during bonding operations.

In conclusion, accurate ERO characterization is becoming increasingly important as wafer-to-wafer bonding technologies advance toward tighter process tolerances and higher manufacturing volumes. While AFM and optical triangulation each offer unique advantages, their limitations in throughput, measurement range, or precision restrict their effectiveness for high-volume production environments. The interferometric metrology system presented in this work demonstrates that high-speed and high-precision ERO measurement can be simultaneously achieved through optimized interferometric design. The proposed approach provides nanometer-scale measurement capability, large-area coverage, and production-compatible throughput, making it a highly promising solution for next-generation semiconductor bonding processes. The developed technology is expected to contribute significantly to process control, yield enhancement, and reliability improvement in advanced semiconductor manufacturing.

Abstract:
With the rapid advancement of next-generation augmented reality (AR) near-to-eye displays and high-performance computing (HPC) hardware, the technical demand for high-density, high-bandwidth, and low-latency vertical interconnects has significantly escalated across the semiconductor industry. To achieve sub-10 micrometer pixel pitches in monolithic Micro-LED displays, conventional solder-based bump bonding schemes encounter severe physical and manufacturing limits, such as solder bridging, brittle intermetallic compound (IMC) formation, and high thermal budgets during reflow. Consequently, gold-to-gold (Au-Au) direct bonding at low temperatures has emerged as a highly compelling alternative, offering exceptional electrical conductivity, superior thermal dissipation, and excellent chemical stability.
In this study, patterned Au pads with four distinct micro-scale dimensions 14, 8, 4, and 2 micrometers are successfully designed, fabricated, and characterized, specifically tailored for ultra-fine-pitch optoelectronic and heterogeneous integration. Unlike conventional sputtered metal schemes, the fabricated interconnect structure comprises a total metallization thickness of 1.0 micrometer, featuring a 600 nm-thick functional Au layer fabricated by a precise lift-off process deposited over a 400 nm-thick adhesion and diffusion barrier underlayer. Atomic force microscopy (AFM) characterization of the micro-pads reveals a highly uniform surface morphology with an average surface roughness (Ra) of 4.22 nm across all pad geometries, representing a typical micro-scale topography of lift-off metallization.
This paper systematically evaluates the surface topography, structural integrity, and scaling effects of these micro-pads. Based on the measured surface roughness of 4.22 nm, a comprehensive analytical assessment of the thermo-mechanical requirements for successful solid-state diffusion bonding is conducted. While atomically flat surfaces (Ra < 1.0 nm) are traditionally desired for pressure less room-temperature surface-activated bonding (SAB), the obtained roughness of 4.22 nm indicates that a controlled thermo-compression process is necessary to facilitate localized plastic deformation at the micro-asperities.
The 600 nm Au film thickness provides an optimal metallurgical balance, offering sufficient ductile volume to absorb the 4.22 nm surface asperities while successfully mitigating the risk of lateral metal squeeze-out and electrical shorting at the ultra-fine 2 micrometer pad pitch. Theoretical modeling of the bonding interface indicates that a high-quality, void-free joint can be accomplished at temperatures below 300 degrees Celsius under optimized bonding pressures, which effectively prevents thermal degradation of active optoelectronic devices. The scaling behavior of the 2, 4, 8, and 14 micrometer pads is thoroughly analyzed to delineate the critical relationship between pad area, contact compliance, and resulting shear strength. This study provides a solid foundation for optimizing the bond parameters of sub-five-micrometer gold pads, establishing a high-yield process flow for cost-effective micro-system manufacturing under strict thermal budget limits. These research findings demonstrate that the fabricated micro-pads are highly viable for enabling robust, ultra-fine-pitch vertical interconnects, thereby successfully bridging the technical gap between high-yield advanced packaging and next-generation high-resolution AR micro-display integration.

Abstract:
INTRODUCTION
Fine-pitch Cu–Cu hybrid bonding is a key interconnection technology for chiplet integration, high-bandwidth memory, and co-packaged optics, enabling solderless interconnection with reduced pitch, lower parasitic loss, and higher vertical integration density. However, Cu bump surfaces are highly vulnerable to organic contamination and native oxidation during the queue time between surface activation, alignment, and bonding. Native Cu oxide generally forms a multilayer structure, with Cu2O-rich–(a p-type semiconductor) Cu1+ near the metallic Cu base and CuO/Cu(OH)2 -rich Cu2+ species at the outer surface. The Cu2+-rich layer acts as a resistive, defect-rich barrier that suppresses intimate Cu–Cu contact and increases contact-resistance fluctuation[1]. Therefore, this work implements sequential 172 nm VUV irradiation and citric-acid treatment on Cu bump chips as a low-temperature, mechanism-driven Cu valence-state control route for organic removal, Cu2+ suppression, citrate passivation, and improved low temperature Cu–Cu bonding.
CONCEPT & METHOD
The proposed process separates dry VUV activation from wet chemical passivation. The 172 nm VUV irradiation decomposes adventitious carbon and oxygen-containing residues through C–C, C–H, and C–O bond scission[2], while citric acid selectively chelates Cu oxide/hydroxide species, especially Cu2+-rich CuO/Cu(OH) 2, forming a temporary Cu–citrate/carboxylate termination[3]. This ultrathin passivation layer is designed to suppress non-uniform re-oxidation during queue time while remaining transformable or removable during thermal compression bonding. CMP-planarized Cu bump chips and blanket Cu reference samples were processed using VUV-only, citric-acid-only, and sequential routes. Surface chemistry was evaluated by XPS C 1s, O 1s, Cu 2p, and Cu LMM Auger spectra to resolve Cu0, Cu1+, and Cu2+ states[1]. ATR-FTIR verified citrate/carboxylate coordination, while AFM/contact-angle measurements evaluated morphology and activation. Treated Cu bump chips were bonded below 250 °C using immediate and delayed splits to evaluate queue-time stability and low-temperature bonding compatibility.
BONDING VALIDATION
For packaging validation, the VUV/citric-acid process is implemented on Cu bump test chips and evaluated against untreated, VUV-only, and citric-acid-only controls. C-SAM/SAT inspection is used to quantify bonded area and interfacial voiding; die shear evaluates mechanical strength; cross-sectional SEM/EDS examine Cu-Cu interfacial continuity and residual C/O; and Kelvin/daisy-chain structures verify electrical continuity and contact resistance across bonded bump arrays. This links surface valence-state control directly to bonding yield, mechanical integrity, and electrical performance in advanced packaging.
Figure 1. OM of hybrid bump (a)before and (b)after VUV/citric acid treatment
Figure 2. Mechanism of passivation layer formation on Cu surface
RESULT AND DISCUSSION
VUV treatment acted primarily as an organic-removal and surface-activation step. After 20 min VUV exposure, the C:Cu ratio decreased from 2.9 to 0.09 and the water contact angle decreased from 76.3 deg to approximately 30.6 deg, indicating effective removal of adventitious carbon and improved wettability. Cu 2p and Cu LMM spectra after citric acid treatment showed suppression of Cu2+-rich hydroxide-related components, while the near-surface region remained dominated by Cu0+/Cu1+-related states.
Figure 3. XPS C1s spectra of VUV exposed copper surface
Figure 4. (a)XPS Cu2p spectra & (b)Cu LMM Auger spectra of VUV + citric acid treated copper surface
Citric acid served as the oxide-state control and passivation step. The 5 wt.% condition provided an effective balance between Cu oxide removal and surface stability. After sequential 20 min VUV + 5 wt.% citric acid treatment, XPS indicated a Cu0/Cu1+-dominant surface with strong suppression of Cu2+ species and residual C–O/O–C=O signals related to Cu–citrate/carboxylate termination. This citrate-derived layer stabilizes Cu valence states, suppresses localized re-oxidation, and supports low-temperature Cu–Cu bonding compatibility.
Figure 5. Contact angle of VUV treated copper surface
Figure 6. AFM morphology measurement on copper surface, (a) No VUV, Image Ra = 3.9 nm, (b)20 min VUV, Image Ra = 2.5 nm
Figure 7. Cross sectional image of the bonded interface
CONCLUSION
Sequential VUV–citric acid passivation demonstrated improved Cu bump oxide-state control, queue-time stability, and bonding compatibility in Cu–Cu hybrid bonding structures. Initial low temperature bonding trials are promising, and further roughness control, electrical reliability evaluation and contact resistance studies are going on.

Abstract:
As the desperate demand of high-performance computing (HPC) driven by artificial intelligence (Al) applications such as next-generation high-bandwidth memory (HBM) toward beyond 16-Hi stacks or the hybrid integration with photonic (PIC) and electronic integrated circuits (EIC) in co-packaged optics (CPO). Heterogeneous integration with advanced 2.5D/3D architectures requiring Cu/SiO2 hybrid bonding with ultra-fine pitch and low thermal budget processes has become a crucial technology with urgent needs. Such low-temperature(<250 °C) processing prevents temperature-sensitive devices from damage and suppresses warpage of thinned stacked wafers and ensures high-precision alignment. In this study, we propose fine-grained Cu (FC-Cu) as bonding interconnects. Recently, FC-Cu has been recognized as another promising materials in Cu direct bonding due to the high density of grain boundaries, which serve as fast diffusion pathways and promote interfacial atomic diffusion, recrystallization, and grain growth across the bonding interface. Thus, demonstrating advantages for low temperature bonding process and aggressive interconnect downscaling in advanced packages.
In this work, FC-Cu is deposited by tailoring the microstructure of the Cu using different plating parameters. Dense FC-Cu with grain sizes of 100~200 nm detected by a electron backscatter diffraction (EBSD) analysis and results shown a high-angle grain boundary fraction exceeding 90% are uniformly electroplated into Cu/SiO2 damascene structures with a diameter of 2 µm. During chemical mechanical planarization (CMP), dishing of the FC-Cu pads can be controlled to less than 3 nm enabling the SiO2 dielectric layers to contact first and form a Van Der Waals bond in the pre-bond stage. This subsequently drives micro-protrusion by the thermal expansion of the Cu pads during post-annealing process at 200 °C under vacuum ambient, yielding void-free Cu-Cu and SiO2-SiO2 bonding. The bonding quality is further analyzed by FIB-SEM and revealing well bonded interface with no obvious cracks and low interfacial void area fraction providing evidence of atomic diffusion bonding. Bonding strength further quantified by using die-shear testing, demonstrating adequate mechanical strength.
In summary, low thermal budgets bonding process is compatible with back-end-of-line (BEOL) processes and reduces warpage in wafer stacks guaranteeing alignment accuracy. Through synergistic morphology control across the fabrication process, the FG-Cu unifies mechanical integrity and electrical performance under low thermal budget. This provides a highly reliable and cost-effective hybrid bonding pathway for ultra-fine pitch 3D-stacked devices such as HBM, CPO optical engines, MEMS, and other advanced packaging applications.

Abstract:
ABSTRACT
In three-dimensional integrated circuits (3D ICs), low-temperature Cu-Cu direct bonding is essential to prevent thermal stress. Crucially, this study validates the low-temperature bonding capability of highly (111)-oriented nanotwinned Cu (nt-Cu) fabricated completely under organic additive-free and continuous direct current (DC) conditions, thereby avoiding the complexities of conventional pulse electrodeposition. Based on a stress-relaxation mechanism where controlling the current density from 0.1 to 0.4 A/cm2 tailors the nanotwin fraction up to 50%, this work successfully applies these tailored microstructures to advanced packaging interconnects. Cu-Cu direct bonding at 240°C for 1 hour realized a completely defect- and void-free bonded interface. Furthermore, the complete absence of organic impurities eliminated boundary pinning sites, enabling the observation of active, micrometer-scale grain growth directly across the bonded interface, which optimizes both mechanical and electrical properties for next-generation advanced packaging.

INTRODUCTION
Next-generation 3D ICs require reliable, low-temperature metal bonding to prevent thermal degradation and minimize residual stress. [1] Cu-Cu direct bonding using (111)-oriented nanotwinned Cu (nt-Cu) is highly advantageous due to its superior electrical and mechanical properties [2], alongside the high surface diffusivity of the (111) plane [1]. Conventionally, nt-Cu synthesis relies on organic additives or complex pulse electrodeposition. However, additives cause impurity incorporation at grain boundaries [3], while pulse plating increases industrial manufacturing costs and reduces overall production efficiency.
To resolve these technical limitations, an additive-free direct current (DC) electrodeposition method is introduced, utilizing current density control (0.1-0.4 A/cm2) under low-temperature conditions to induce highly pure nt-Cu structures driven by a stress-relaxation mechanism. [4] Building upon this foundation, this work extensively validates the low-temperature Cu-Cu bonding capability of these additive-free films. By eliminating impurities, boundary pinning sites are removed, enabling the unique observation of active micrometer-scale grain growth across the joint interface at 240°C.

EXPERIMENTAL
Cu films were electrodeposited using an additive-free 1.0 M CuSO4-5H2O electrolyte adjusted to pH 0.8 with sulfuric acid. The process was conducted at 0°C to restrict adatom surface diffusion and promote stress-relaxation-induced twin formation. The DC density was varied to tailor the microstructural transition. For bonding evaluation, 0.3 A/cm2 samples were utilized. Thermal compression was performed under a nitrogen (N2) atmosphere at 240°C and 2 MPa for 1 hour. Cross-sectional microstructures and the bonded interface were comprehensively analyzed via focused ion beam (FIB) microscopy.

RESULTS AND DISCUSSION
Under low-temperature, additive-free conditions, the microstructure transitioned from nanocrystalline to (111)-oriented nt-Cu solely through DC density control. As the current density increased from 0.1 to 0.4 A/cm2, the nanotwin column density systematically elevated from 0% to approximately 50%. Chronovoltammetry and stress analyses revealed that a higher current density restricts the time available for adatom surface diffusion relative to charge transport, inducing high initial residual stress in the growing film. [4] To alleviate this elevated strain energy, (111)-oriented nanotwins are preferentially formed as a stress relaxation mechanism, which subsequently leads to a significant reduction in intrinsic macro-stress. This behavior aligns with the Strain Energy Release Maximization (SERM) model, where stress relaxation drives preferential crystallographic evolution. [4]

Thermal compression of the nt-Cu film electrodeposited at 0.3 A/cm2 demonstrated an exceptionally stable and defect-free joint interface at 240°C for 1 hour. Notably, active grain growth spanning several micrometers occurred directly across the original bonding interface. This phenomenon strongly deviates from conventional nt-Cu bonding literature, where interdiffusion is typically restricted to surface creep along the (111) planes without massive grain boundaries migration. [1] In this work, the use of an additive-free electrolyte successfully prevented the incorporation of organic impurities or co-deposited codeposits within the Cu matrix. The complete absence of these embedded impurities eliminated the grain boundary pinning sites (Zener pinning effect). [3] Consequently, the substantial stored strain energy and twin boundary defects within the nt-Cu acted as a powerful driving force, accelerating massive grain growth across the contact boundary during annealing. This distinct microstructural evolution effectively eradicates interfacial voids, minimizes electrical resistivity, and significantly enhances mechanical bond strength.

CONCLUSION
In conclusion, this study successfully demonstrates a reliable low-temperature Cu-Cu direct bonding pathway utilizing highly pure, (111)-oriented nt-Cu films controlled solely via an additive-free DC electrodeposition process. By precisely optimizing the direct current density, the intrinsic stress-relaxation mechanism successfully tailored the nanotwin fraction up to 50% without requiring conventional organic additives or complex pulse current parameters. Thermal compression bonding of these tailored films at a reduced temperature of 240°C for 1 hour realized a completely defect- and void-free bonded interface. Crucially, the complete absence of organic impurities eliminated boundary pinning sites, enabling the unique observation of active, micrometer-scale interfacial grain growth, which provides a highly dependable integration solution for next-generation 3D packaging applications.

Abstract:
The downscaling of semiconductor devices has positioned advanced packaging at the forefront of microelectronics evolution. Cu-Cu hybrid bonding is indispensable for achieving ultra-high input/output (I/O) densities, circumventing traditional solder joint limitations. However, conventional thermo-compression bonding requires processing temperatures exceeding 300°C, imposing severe thermal budgets. Consequently, engineering robust Cu interconnects for low-temperature bonding is imperative.
Nanocrystalline Cu (NC-Cu) enables low-temperature bonding due to its massive internal energy and dense grain boundaries serving as rapid atomic diffusion paths. However, NC-Cu is highly susceptible to room-temperature self-annealing, dissipating its thermodynamic driving force. Here, we investigated the microstructural evolution of electrodeposited Cu films—prepared with Chemleader Corporation additives—across different current densities. Analysis revealed highly current-dependent grain sizes: 1 ASD yielded coarse grains (~600 nm), 4 ASD showed intermediate grains (~200 nm), and 12 ASD produced NC-Cu grains (~80 nm). After one month of room-temperature storage, the 1 ASD and 4 ASD samples maintained structural integrity, whereas the 12 ASD sample underwent severe self-annealing, abnormally coarsening to over 3 μm.
To clarify this disparate stability, Secondary Ion Mass Spectrometry (SIMS) was conducted. Results showed an inverse correlation between current density and impurity incorporation. The stable 1 ASD film trapped higher impurity concentrations (C, N, O, S, Cl), effectively pinning grain boundaries. Conversely, the 12 ASD layer contained far fewer impurities, leaving its active grain boundaries unpinned and thermodynamically unstable.
Bonding tests were conducted at 200°C for 1 hour. Due to insufficient diffusion, the 1 ASD sample exhibited prominent interfacial gaps, and the 4 ASD sample retained a distinct straight bonding interface. Although the freshly prepared 12 ASD sample demonstrated remarkable cross-interface grain growth, its susceptibility to self-annealing severely limits the practical storage window, creating a critical material trade-off.
To overcome this limitation, a double-layer Cu architecture was engineered via a single-bath electrodeposition process. A coarse-grained foundation was formed at 1 ASD, followed by switching current density to deposit a thin (<1 μm) NC-Cu layer on top. Because this top layer is thin, it lacks sufficient energy to initiate self-annealing. Evaluations confirmed the as-deposited top NC-Cu grains were ~80 nm. Even after one month of storage, the cross-sectional structure remained stable, and the top NC-Cu grain size stayed below 100 nm, preserving its bonding energy.
Leveraging this stabilized driving force, bonding was successfully achieved at 200°C. The double-layer structure exhibited a dense, zig-zag bonding interface. Transmission electron microscopy (TEM) validated that curvature-driven thermodynamic imbalance caused the foundation's coarse grains to consume the top NC-Cu grains. This cross-interface grain growth successfully eliminated interfacial defects, providing a promising and reliable solution for next-generation advanced packaging.

Abstract:

This presentation introduces innovative vertical interconnect technologies utilizing copper nanomaterials. As advanced packaging becomes increasingly important, vertical interconnect technologies—rather than only lateral interconnect scaling—are becoming critical. We will introduce two technologies enabled by copper nanomaterials: DeepVia™, which enables high-aspect-ratio vias, and SAphire™, a copper sintering paste for advanced bonding applications.

Abstract:
Since their advent in the 1990s, laser formed blind microvias (BMV) have become a common design feature in modern PCBs as they offer unrivalled opportunities for device miniaturization. However, as their use has expanded into ever more challenging applications, there has been a growing concern regarding their long-term reliability performance, especially when replacing a traditional “staggered” or “offset” design with the more enabling “BMV stack”
Initially, such concern was addressed through investigations that reported on the physical testing of stacked BMVs, but more recently, there have been a number of publications regarding the metallurgical characteristics of plated and filled BMVs. In such investigations there have been two predominant microstructures identified, one being considered as “ideal” and the other being less favored as it has been shown to be mechanically weaker. In view of these findings there has been ongoing desire to not only understand how such structures are formed, but to ensure that the ideal situation becomes the norm for high volume manufacturing.
In this paper, we summarize our current findings regarding the two dominant plated structures and identify some factors which impact their formation. We follow this by introducing the concept of “Normalized Crack Length” (NCL) as a means for evaluating crystallographic epitaxy in a BMV. Using examples taken from production made PCBs, the derived NCL is then shown to be a positive indicator for relative reliability performance, and can be used as a viable means to compare and evaluate the performance of plated BMVs.

Abstract:
The rapid expansion of servers and electric vehicles has driven significant demand for high-layer-count (12+ layers) and high-density interconnect (HDI) PCBs. These complex architectures require large stacked vias and high-aspect-ratio through-holes paired with fine-pitch Ball Grid Array (BGA) patterns to support high-speed signal transmission, thermal management, and power efficiency. However, conventional direct current (DC) plating processes have limitation to plate through holes on a thick board, which can lead to non-uniform copper distribution, such as the "dog-bone" effect and severe surface thickness variations that disrupt impedance matching and compromise solder joint reliability. This paper reviews process optimizations to address these challenges, specifically focusing on high-aspect-ratio through hole configurations and high-hole-density regions where localized potential drops reduce throwing power and increase the thickness variation on surface. The deployment of periodic pulse reverse (PPR) plating technologies combining with PPR products such as brand names of PC 600 and PC 610 mitigate the issues and ensure robust hole plating to achieve a planarized surface and high throw power inside holes.

Abstract:
Continued scaling of IC substrate interconnects toward finer line/space dimensions and increasing package complexity places growing demands on patterned blind microvia (BMV) filling in build-up layers. In addition to void-free via filling and low surface copper thickness, advanced IC substrate manufacturing requires excellent within-unit and within-panel copper thickness uniformity across a wide range of layouts and operating conditions, while maintaining high productivity in volume production environments.
Organic IC substrates are a key enabler for next-generation AI accelerators and high‑performance computing (HPC) modules, driving strong growth in advanced substrate technologies. Market forecasts expect the advanced substrate market to reach approximately USD 31 billion by 2030, driven by AI, HPC, and increasing package complexity [1]. To meet these requirements, leading substrate manufacturers are transitioning toward line/space dimensions of 10/10 µm and below, where the semi-additive process (SAP) is the dominant build-up layer approach. Within this process flow, patterned BMV filling represents a major yield and performance risk, as local copper thickness variation within the unit can directly impact impedance control, pad-to-trace height uniformity, and downstream assembly margins. Consequently, stable copper thickness distribution at practical current densities is a key performance metric for advanced IC substrate processes [2].
This paper presents a new electrolytic copper process for patterned DC BMV filling in vertical plating systems using insoluble anodes. The process is designed to deliver robust via filling and uniform copper deposition for advanced IC substrate and redistribution layer (RDL) applications. Experimental evaluation focuses on BMV filling performance, within-unit distribution and uniformity, current-density capability, and benchmark comparisons across four different board designs. Performance metrics include plated copper thickness range, relative thickness range, dimple depth, and line-profile control for fine-line features.
The results demonstrate reliable BMV filling with dimple depths below 2 µm and improved thickness uniformity compared with benchmark processes across all evaluated board designs. The process shows reduced layout sensitivity, maintaining consistent copper thickness distribution for dense and isolated features. Stable filling and uniformity are achieved over a current density range from 1 to 3 A/dm², supporting both productivity and process flexibility. Overall, the new electrolytic copper process provides a layout-robust and benchmark-competitive solution for patterned BMV filling, enabling advanced IC substrate designs with increasing density, complexity, and manufacturing demands.

Abstract:
The rapid growth of electric vehicles (EVs) is driving increased demand for highly reliable electronic assemblies used in battery management systems, power conversion modules, onboard charging systems, vehicle control units, and advanced driver-assistance systems. As manufacturers seek cost-effective, lead-free solutions that can meet stringent automotive reliability requirements, immersion tin has emerged as an attractive final finish due to its excellent solderability, flat surface profile, and compatibility with fine-pitch assembly processes.
This presentation reviews recent advances in immersion tin final finish technology that have enhanced its suitability for demanding EV applications. Key developments in process chemistry, bath stability, deposit quality, corrosion resistance, and whisker mitigation will be discussed. In addition, the presentation will highlight emerging applications of immersion tin in EV electronics, including battery management systems, power electronics, and vehicle control modules. Current industry trends, technical challenges, and future opportunities will be explored, with an emphasis on how ongoing innovations in immersion tin technology are supporting the evolving requirements of next-generation automotive electronics.
The results demonstrate that continued improvements in immersion tin chemistry and process control are expanding its capability as a reliable, sustainable, and cost-effective final finish solution for the rapidly growing EV market.
Keywords: Immersion Tin, Final Finish, Electric Vehicles, Automotive Electronics, Battery Management Systems, Power Electronics, Solder Joint Reliability, Whisker Mitigation.

Abstract:
With the rise of advanced packaging and 3D ICs, low-temperature (<250°C) Cu-Cu direct bonding is crucial for high-density interconnects. However, ambient or low-temperature oxidation forms native Cu2O and CuO layers that inhibit atomic diffusion and degrade bond quality, making accurate oxide quantification crucial. While previous research focuses on high-temperature oxidation kinetics, phase-resolved thickness quantification of thin CuO/Cu2O layers formed below 200°C remains limited. This study utilizes galvanostatic coulometric reduction (GCR) paired with Faraday’s law to quantify CuO and Cu2O thicknesses in low-temperature oxidized copper films. Electrochemical data confirmed a stepwise reduction sequence CuO→Cu2O→Cu, supported by interrupted-reduction Raman and XPS analyses. Notably, the SAE outperformed NaOH by providing clearer reduction plateau separation and minimizing signal overlap. Furthermore, TEM and Alpha-step analyses validated the accuracy of the electrochemically estimated thicknesses. Ultimately, this study establishes a reliable electrochemical method for phase-resolved copper oxide quantification, serving as a valuable process-control tool prior to Cu-Cu bonding.
Keywords: Cu-Cu bonding, copper oxide, galvanostatic coulometric reduction

Abstract:

The semiconductor industry is being reshaped by megatrends such as AI, high-performance computing, cloud infrastructure, 5G, automotive electrification, and others. These applications are driving increasingly demanding system requirements. As front-end scaling becomes more challenging, the industry is turning to system-level scaling, positioning advanced packaging as a critical enabler.
This presentation will provide an overview of the advanced packaging market, which is forecast to grow with a CAGR of more than 12% in the next five years, driven by strong adoption of 2.5D/3D packages for AI and HPC applications. It will then explore co-packaged optics as a key emerging architecture for next-generation data-center networking, where optical engines are brought closer to switch ASICs to reduce electrical interconnect length, lower power consumption, and increase bandwidth density.
A deep dive will address the packaging technologies enabling CPO, from EIC/PIC integration using 3D stacking, hybrid bonding, and fan-out approaches, to system-in-package (SiP) assembly roadmaps moving from FCBGA substrates toward 2.5D interposers, photonic interposers, and other heterogeneous integration platforms. The presentation will also review market examples such as NVIDIA Quantum-X, discuss the potential role of panel-level packaging for larger CPO modules, and map the emerging supply chain involving foundries, IDMs, OSATs, and ecosystem collaborations across optical engine and CPO assembly.

Abstract:

Driven by generative AI and Large Language Models (LLMs), chip-to-chip communications within AI clusters are facing severe bottlenecks due to the "I/O Power Wall" and thermal limits. Traditional pluggable optical modules can no longer meet the demands for ultra-high bandwidth, low latency, and extreme power efficiency required at 1.6T/3.2T data rates and beyond.

This presentation provides a deep dive into the evolutionary roadmap of optical interconnects—transitioning from Near-Packaged Optics (NPO) to Co-Packaged Optics (CPO)—and outlines the timeline for commercial deployment. We will focus on next-generation Optical Interposers and 3D heterogeneous integration technologies, demonstrating Bonding between Electronic Integrated Circuits (EICs) and Photonic Integrated Circuits (PICs) eliminates parasitic capacitance. Furthermore, addressing the critical manufacturing challenges of large-die packaging, we present a comprehensive Package Total Solution encompassing warpage control, advanced thermal management, high-precision passive optical alignment, ..etc to enable the next wave of AI infrastructure.

Abstract:

Scaling AI workloads demands unprecedented bandwidth, shifting high-performance computing to heterogeneously integrated architectures. This presentation explores how panel-level scaling and glass core substrate integration leverage packaging innovations to overcome constraints in power delivery, I/O scaling, signal integrity, and mechanical reliability - essential pathways for building tomorrow’s robust AI infrastructure.

Abstract:

AI-driven datacenter infrastructure is fueling unprecedented growth in photonics-based applications, where scaling governed by Moore’s Law is no longer applicable. Current deployments support data rates of up to 400 Gb/s per optical channel, while R&amp;D efforts targeting 800 Gb/s per channel are showing promising results. This evolution is paving the way toward the ultra-high bandwidth required for latency-free AI workloads, targeting a bandwidth of 12.8 Tb/s. Previous generations of electro-optic circuits have proven too power-hungry to efficiently support the scale of AI infrastructure, driving the development of a new generation of E-PIC devices incorporating shared, multi-channel optical emitters. This is where co-packaged optics (CPO) becomes a critical, enabling technology. The adoption of CPO represents a significant innovation in addressing the bandwidth, power, and density requirements of these next-generation AI systems. At the same time, however, it introduces substantially greater test complexity. Test flows now involve more insertion points, simultaneous optical and electrical measurements, and significantly more demanding mechanical configurations. Optical and electrical interfaces may be located on the same side, opposite sides, or perpendicular sides of the device under test (DUT), creating new challenges for alignment, probing, handling, and automation. This presentation will review the mechanical, electrical, and optical requirements of test insertions 1, 2, 3, and 4 and will relate many of these challenges to solutions available from MPI Corporation.

Abstract:
The application of communication integrated circuits (IC) of high-bandwidth and high-speed products (networking, switch and connection equipment) is needed. Moreover, demands for package size reduction, performance enhancement and lower power consumption are always required in network communication applications with advanced wafer node, the trace routing with a thinner line width/space (L/S) is necessary. Hence, the multi-die Fan-out (FO) strip form package with fine pitch bumping is presented to accommodate large amounts of input/output (I/O) ports. The strip form package means that the redistribution layer (RDL) substrate is first fabricated on a temporary glass panel. After the RDL substrate is fabricated, this panel substrate is then cut into smaller strips, and all remaining processes are assembled on the strip substrate. However, when the FO strip form package with a thinner line width/space is developed in electronic devices, the manufacturing capability, warpage and structure characterizations and package level/board level reliability (BLR) must be considered. Meanwhile, the package performance of whether there is a heat spreader or not is also observed. With full consideration of the warpage and structure characterizations of the unit package, package level/board level long-term reliability tests and failure analysis are achieved. Through these results, the multi-die FO strip form package is also verified to accommodate advanced wafer node with higher routing density.

Abstract:
The rapid growth of artificial intelligence (AI) applications has accelerated the demand for diverse, low-volume, and fast-turnaround semiconductor development. Conventional manufacturing approaches are often associated with high mask costs and long development cycles, making them less suitable for startups and emerging applications requiring rapid prototyping. To address these challenges, this work proposes and demonstrates a mask-sharing shuttle service platform for advanced redistribution layer (RDL) fabrication in fan-out packaging technologies.
In this study, multiple customer designs and applications were integrated within a shared photomask architecture through optimized wafer-layout planning. The developed platform utilized an RDL-first fan-out process on a 12-inch glass carrier to fabricate multilayer RDL structures. A multilayer architecture consisting of five copper metal layers (5M) and five polyimide passivation layers (5P) was successfully realized, while a fine-pitch 6P6M structure was further demonstrated. The fabricated RDL structures achieved minimum line/space dimensions of 2 μm/2 μm and 8 μm PI via openings, demonstrating the capability for high-density interconnection applications.
To improve process stability and scalability, several warpage-control techniques were implemented, including coefficient of thermal expansion (CTE) compensation, PI thickness optimization, layout uniformity enhancement, and backside balance-film integration. Through these approaches, overall warpage reduction of up to 72% was achieved, enabling successful extension of the multilayer process from 5P5M to 12P12M structures.
Electrical reliability was evaluated using embedded daisy-chain and comb-structure test element groups (TEGs). Daisy-chain measurements exhibited stable electrical characteristics with variations within ±10%, while comb structures demonstrated picoampere-level leakage current performance, confirming the integrity and reliability of the fabricated RDL structures. In addition, high-aspect-ratio (AR > 3.5) RDL structures with 2 μm/2 μm line/space were successfully fabricated, exhibiting well-defined line profiles and sidewall morphology. Furthermore, Cu/Ni/SnAg bump structures fabricated at both the center and edge regions of the 12-inch wafer showed excellent dimensional uniformity and stable metallurgical interfaces.
The proposed shuttle service platform demonstrates strong potential for low-cost AI chip prototyping, heterogeneous integration, and next-generation high-density advanced packaging applications.

Abstract:
In this research, we have used the MW(Micro-Wave) process for CoWoS advanced semiconductor packaging on under-fill high 10 um process. Because the gap is very narrow space distance within die and substrate. MW plasma treatment technology provides a solution to avoid delamination in the under-fill process.

We need to adjust the parameter for Taguchi design method and got the best hydrophilic. Experimental results are measured by applying the water contact angle method to the treated substrate. The cleaning process is carried out under the best vacuum in the chamber. This experimental results provide that the high frequency (2.45 GHz) can ensure the substrate stably reaches hydrophilic quality. and it can be applied to CoWoS advanced packaging of under 10 um under-fill narrow space for MW plasma treatment process. (Fig.1)

In this study, we design the four-stage rotation mode software based on the MW plasma process for treatment under-fill. The substrate specimen module has under-fill space under 10 um, and microwave plasma treatment processing in narrow space and prevents bump delamination. On the other hand, its dry process features eliminate residual solution stains and organic solvent emission problems caused by wet processes, meeting the current green and environmental requirements.

The water contact angle of the treated substrate was measured in the experiment. After treatment substrate surface also has varying degrees of hydrophilicity and hydrophobicity, and the optimal process parameters was obtained through contact angle measurement. This experiment uses the Taguchi method to design the Orthogonal Array. The Complex Process Capability index (Cpk) appears under various treatment processing. Experimental results show that the hydrophilicity of the test vehicle becomes more significant not because of the increase in Power and Oxygen flow, but as the treatment time increases, the optimal hydrophilic state is reached when Power: 900 W; Oxygen: 400 sccm and Time: 600 sec, the water drop angle is less than a tiny 20 degrees. Therefore, This study focuses on using the Taguchi design method to get the best results in hydrophilicity testing. (Fig.2)

This experimental result proves that the MW plasma can ensure the substrate stably reaches hydrophilic quality during the plasma treatment process and can be applied to CoWoS advanced packaging of under 10 um under-fill narrow space.
Key Words: CoWoS, MW(Micro-Wave), Under-fill, Water Contact angle, Taguchi design method.

Abstract:
As the IC dimensions continuously scale down, the challenge of
fabricating high-density interconnections for heterogeneous
integration significantly increases. Cu-to-Cu diffusion bonding is
widely considered to be a promising solution to this challenge.
However, traditional bonding techniques face the problem of high
thermal budgets, which induce severe thermal stress and substrate
warpage due to the mismatched thermal expansion coefficients of the
packaging materials. Hence, developing a low-temperature and rapid
bonding process is in need. While highly <111>-oriented
nanotwinned Cu (NT-Cu) has attracted significant attention due to the
high surface diffusivity of its <111> crystal plane and excellent
oxidation resistance, its specific microstructure makes it highly
challenging to be electroplated into ultra-fine or high-aspect-ratio vias.
To circumvent this limitation, nanocrystalline Cu (NC-Cu) is regarded
as the candidate because its ultra-fine grains facilitate uniform
electroplating inside vias. Furthermore, NC-Cu contains a large
volume fraction of grain boundaries, which can not only serve as fast
diffusion paths for atomic transport but also store high internal energy,
thereby enhancing the kinetics of bonding interface elimination. This
mechanism provides an accelerated atomic flux, allowing substantial
plastic deformation and void closure under reduced thermal budgets.
However, directly quantifying the Cu diffusivity of grain boundary
(Dgb) is difficult because the bonding mechanism includes surface
diffusion and grain boundary mechanism. Without the explicit
determination of the Dgb, the quantitative understanding regarding
kinetic advantages of NC-Cu remains unclear. In our work, we
endeavor to obtain the value of Cu diffusivity of the grain boundary
through experiment measurements rather than simulation. We
deposited the Cu film for 3 μm thick by DC electrodeposition in an
acidic electrolyte. Following electroplating, chemical mechanical
planarization (CMP) was conducted to achieve a planarized surface
with proper surface roughness. After planarization and the post
cleaning steps, the samples were diced into 6×6 mm2 and 12×12 mm2
to serve as top dies and bottom dies, respectively. The bottom dies then
underwent photolithography and etching to create artificial voids with
a width of 4.8 μm and a depth of 300 nm. Finally, the samples
underwent the thermal compression bonding process at 300 °C under
a compressive pressure of 30 MPa for 15, 30, 45, and 60 min,
respectively. Cross-sectional analysis was carried out using focused
ion beam (FIB) to measure the shrinkage area of the artificial voids as
the bonding time increased. To evaluate the effect of the grain size,
three distinct types of substrates including highly <111>-oriented NT-
Cu, random NC-Cu, and random coarse-grained Cu (CG-Cu) were
utilized for comparison. Preliminary results show that the void
shrinkage in NC-Cu is much more substantial. This suggests that NC-
Cu exhibits the advantage in accommodating Coble creep due to its
ultra-high density of grain boundaries. Future work will focus on
calculating the exact values of Dgb for the respective microstructures
by fitting the final experimental results to the Ostwald ripening model
V = md ⋅ πr2 = J ⋅ A ⋅ t ⋅ Ω=
DS
σ
r (2πrd)t.

Abstract:
In recent years, artificial intelligence (AI) has been widely applied in various industries, driven by the powerful computational capabilities of integrated circuit chips enabled by advanced packaging technologies. In CoWoS advanced packaging, the precision of TSV interconnections is crucial for achieving high-bandwidth communication and significantly impacts the computational performance of integrated circuits. Therefore, achieving global planarization of heterogeneous materials such as copper (Cu), silicon (Si) and silicon nitride (SiN) is essential for the subsequent TSV interconnection processes. In this paper, the H2O2-SiO2-based slurry was utilized to investigate the polishing behavior of heterogeneous materials, including Cu, Si and SiN. Based upon the test conditions, the low concentration H2O2 exhibited the highest Si removal rate and favorable removal selectivity among the three type materials.

Abstract:
Flexible and large-area electronic packaging requires interconnection materials that can maintain electrical stability and mechanical reliability under thermal and mechanical deformation. In particular, anisotropic conductive film (ACF)-based interconnections used in display and flexible electronic packages are strongly affected by thermally induced deformation because excessive warpage can disturb conductive-particle contact uniformity and degrade package reliability. In display applications, non-uniform deformation may also contribute to optical non-uniformity, such as the Mura effect. Therefore, controlling warpage and stress in large-area interconnection structures is essential for achieving reliable next-generation flexible and high-density electronic packaging. In this study, the thermo-mechanical behaviors of stretchable anisotropic conductive film (SACF) and conventional anisotropic conductive film (ACF) were systematically compared using finite element method (FEM) analysis. The effects of film thick

Abstract:
Advanced packaging technologies, including 3D integration, chiplets, and hybrid bonding, are increasingly required for AI/HPC and HBM-based semiconductor devices. Metal-to-metal direct bonding is a promising alternative to solder-based bonding because it can overcome pitch scaling and reliability limitations in advanced packaging. However, conventional Cu-based direct bonding generally requires temperatures of 300 °C or higher to achieve sufficient interfacial diffusion and stable metallic bonding. Although plasma-assisted surface activation and passivation layers have been explored for low-temperature bonding, they may require additional processes and show limited compatibility with existing interconnect and CMP processes. Here, we propose low-temperature direct bonding by inducing a metastable CuAg alloy state and controlling its nanoscale structure.
CuAg alloy films were deposited by co-sputtering using Cu and Ag targets, and the substrate rotation speed was controlled at 0, 4, 7, and 10 RPM to modulate the compositional structure. The metastable alloy state was induced through non-equilibrium sputtering, while periodic Cu-rich/Ag-rich nano-multilayer structures were formed by substrate rotation. Cross-sectional STEM-EDS analysis showed no clear periodic modulation in the 0 RPM condition, whereas repeated Cu-rich/Ag-rich regions were observed in the rotation-deposited films. As the rotation speed increased from 4 to 10 RPM, the modulation period decreased from approximately 20 to 8 nm, corresponding to an about 2.5-fold reduction. This confirms that the rotation speed is closely related to the deposition amount per rotation and that the nano-multilayer period can be controlled by substrate rotation.
The crystallinity and electrical properties of the as-deposited films were analyzed by XRD and four-point probe measurements. XRD results showed the main diffraction peaks of Cu and Ag, with variations in peak position and intensity depending on the rotation condition. These changes indicate that the metastable alloy and nano-multilayer structure affected the crystallographic characteristics of the films. The CuAg nano-multilayer films exhibited lower resistivity than the monolayer CuAg film, with a maximum reduction of approximately 21.4%, suggesting that the resistivity increase generally caused by alloying can be partially mitigated by nano-multilayer structure control. XRD and resistivity measurements were also performed after annealing at 200 °C for 6 h to evaluate structural and electrical stability.
The bonding characteristics were evaluated after metal-to-metal direct bonding at 200 °C under 5 MPa for 1 h. Cross-sectional STEM-EDS analysis after bonding confirmed that the Ag-rich bonding interface and CuAg nano-multilayer structure were maintained, indicating that the Ag-rich interface and compositional modulation contributed to low-temperature bonding interface formation. The interfacial adhesion energy measured by double cantilever beam testing increased from 1.27 ± 0.19 J/m² for the 0 RPM condition to 3.46 ± 0.55 J/m² for the 10 RPM condition. The 7 and 10 RPM samples exhibited mixed fracture behavior involving the bonding interface, film interior, and deposition interface, indicating strengthened interfacial adhesion. These results demonstrate that metastable CuAg nano-multilayer films enable reliable metal-to-metal direct bonding at 200 °C and provide a promising low-temperature interconnection strategy for 3DIC, HBM, chiplet, and hybrid bonding-based advanced packaging.

Abstract:
Due to the demand for interconnects between high-density chips, solder bump miniaturization has been progressing, and pitch has reached the ultra-fine scale below 20 μm. In conventional solder bonding, flux is used to reduce Sn oxides on the solder surface and enable electrical interconnection; however, flux residues may adversely affect not only the reliability and performance of solder interconnects, but also the filling ability during underfill encapsulation. Therefore, fluxless bonding methods that reduce the Sn oxide layer without using flux have been developed, such as heating in a formic acid atmosphere. However, they involve challenges including carbonaceous residues, substrate corrosion and environmental burdens. In this study, with the aim of developing an activation process that reduces these problems, we developed a method to reduce Sn oxide on solder using Vacuum Ultraviolet (VUV) light with a central wavelength of 172 nm emitted from a xenon excimer lamp (Ushio Inc.). The irradiation atmosphere consisted of 4 % hydrogen gas and 1.5 % water vapor with nitrogen base gas (H2 + H2O) at atmospheric pressure. Under VUV irradiation, photodissociation of H2O generates hydroxyl radicals (∙OH), which contribute to surface cleaning, and hydrogen radicals (H∙), which act as reducing species. In addition, ∙OH reacts with H2 to produce additional H∙, enhancing the reduction capability. The cleaning and reduction effects were evaluated by X-ray photoelectron spectroscopy (XPS).
When VUV irradiation was performed at room temperature (25 °C) under H2 + H2O atmosphere, a decreased signal in the XPS-C1s spectrum was observed, representing the removal of organic contaminants. In addition, the peak corresponding to metallic Sn increased in the XPS-Sn3d spectrum, indicating that Sn oxide was reduced by the treatment. Therefore, the VUV process under the H2 + H2O atmosphere contributed not only to surface cleaning but also to the reduction of the oxide layer formed on the solder surface. However, at higher accumulated light doses, the reaction tendency shifted from reduction to oxidation. This behavior is likely because ∙OH initially reacted with organic contaminants on the surface. After organic contaminants were removed, ∙OH began to react with Sn metal, forming Sn oxide. As a result, the exposed metallic Sn was reoxidized, leading to a decrease in the reduction effect at higher irradiation doses. To further enhance the reduction effect, the sample stage was heated to 100 °C. Under this elevated temperature condition, although the removal rate of organic contaminants became slightly slower, the reduction effect on Sn oxide was significantly enhanced. The slower organic removal behavior is likely because the elevated temperature accelerates reaction between H2 and ∙OH consumes ∙OH more rapidly. On the other hand, the reducing reaction of Sn oxide is accelerated due to higher temperature making the Sn oxide easier to react with H∙.
These results demonstrate that VUV treatment in an H2 + H2O atmosphere contributes to both surface cleaning and oxide reduction of Sn oxide. These combined effects indicate that this treatment method is highly promising as a surface activation technique for fluxless bonding applications.

Abstract:
Conformal tactile sensing has become increasingly important in the domain of robotic dexterous manipulation. In this domain, pressure information complements vision-based perception and enables stable grasping, object recognition, and manipulation tasks. However, the majority of reported capacitive pressure sensors are fabricated on planar substrates, which poses significant challenges to their integration onto the intricate three-dimensional curved surfaces of robotic fingers.
The present study introduces a vacuum-thermoformed, conformally capacitive tactile sensor that has been fabricated using screen-printing technology and flexible thermoplastic substrates. The proposed multilayer sensor consists of a shielding layer, insulating layers, printed electrodes, a dielectric layer, and a ground plane, resulting in a total thickness of approximately 200 μm. Finite element analysis was performed to investigate the electromechanical response under applied forces ranging from 0 to 3 Newtons (N). Simulation results predict a capacitance variation from 69.77 pF to 144.54 pF with a maximum structural displacement of 16 micrometers (μm).
In order to achieve three-dimensional conformational integration, a bespoke robotic finger mold was conceptualized and manufactured. This was followed by the implementation of vacuum thermoforming, a process that transformed the two-dimensional printed sensor into a curved sensing structure. The experimental results obtained demonstrate the successful implementation of a conformable attachment process onto the surface of a robotic finger, thereby establishing a foundation for stable capacitive responses under external loading conditions. The fabricated device demonstrates a discernible force resolution of 1 g and a capacitance change of approximately 5 pF at 3 N loading. In the low-force region (5–50 g), the sensor demonstrates enhanced sensitivity, as evidenced by a coefficient of determination (R²) ranging from 0.91 to 0.93 and a linearity error of approximately ±3% FSO. For forces greater than 50 g, the system exhibits highly linear behavior, as evidenced by an R² exceeding 0.995 and linearity errors below ±0.5% FSO.
The proposed approach offers a scalable manufacturing route for conformal tactile electronics and demonstrates significant potential for next-generation applications.

Abstract:
Abstract—Monolithic 3D (M3D) integration enables higher interconnect density, shorter signal paths, increased bandwidth, and reduced RC delay compared with conventional stacking technologies. However, the formation of high-quality upper single-crystalline silicon layers under a low thermal budget remains one of the major challenges for M3D integration. To address this issue, Green Nanosecond (GNS) laser recrystallization with crystal-orientation control has been proposed to transform amorphous silicon into single-crystalline silicon through liquid-phase epitaxy.

In our previous work, a 150-nm-thick single-crystalline silicon film was successfully demonstrated using the Elevated-Epi (ELEPI) technique. During laser irradiation, the amorphous silicon layer is melted and recrystallized from silicon seed pillars defined from the substrate, resulting in the formation of a continuous single-crystalline silicon film. The technique provides a potential approach for realizing high quality upper silicon layers while maintaining compatibility with sequential three-dimensional integration processes.

In this work, the ELEPI technique is further extended toward multi-tier M3D integration through the development of a multi-cycle laser-induced epitaxy process, where successive upper-layer single-crystalline silicon films are formed through repeated laser melting and epitaxial recrystallization. Since the laser power required to directly recrystallize a thick silicon film is prohibitively high, a multi-step laser recrystallization approach is adopted. Two different structural designs are investigated and compared.

In Structure 1, two sequential laser recrystallization processes are employed to form stacked epitaxial silicon layers. After the first recrystallization process, an additional amorphous silicon layer is deposited and subjected to a second laser irradiation. However, COMSOL thermal simulations indicate that the large-area silicon layer underneath rapidly dissipates heat during laser irradiation due to its high thermal conductivity, which may result in insufficient melting temperature during the second laser recrystallization process. Consequently, achieving complete melting and subsequent epitaxial regrowth becomes increasingly challenging as the silicon thickness increases.

To overcome this limitation, Structure 2 introduces a pillar-based seed structure prior to the second laser recrystallization step. By replacing the first continuous silicon layer with defined silicon pillars, the contact area between the first-layer single-crystalline silicon and the overlying amorphous silicon is significantly reduced, thereby suppressing rapid heat dissipation and increasing the peak temperature at the amorphous Si/Si pillar interface during laser irradiation. Simulation results show that the pillar-based structure achieves improved thermal confinement and facilitates complete melting of the overlying amorphous silicon under the same laser power, indicating enhanced feasibility for repeated laser-induced epitaxial growth.

These results provide valuable design insights for multi-step laser recrystallization and suggest that pillar-assisted structures are a promising approach for extending the ELEPI technique toward future multi-tier monolithic 3D integration. The proposed architecture also establishes a foundation for further experimental investigations of upper-layer silicon formation through repeated laser-induced epitaxy.

Abstract:
Direct copper-to-copper (Cu-Cu) bonding has emerged as a critical technology for high-density, three-dimensional integrated circuits (3D ICs) and advanced packaging architectures, which are essential for driving high-performance computing (HPC) and artificial intelligence (AI) hardware accelerators. As Moore’s law approaches its physical boundaries, conventional micro-bump interconnects face severe scaling bottlenecks, including bridging risks and high thermal resistance, at fine pitches. To overcome these limitations, advanced interconnect nanotechnology must pivot from traditional micro-bumps toward bumpless wafer-to-wafer (W2W) hybrid bonding. This evolution enables sub-micron interconnect pitches and superior thermal dissipation capabilities, facilitating monolithic logic-memory integration. Consequently, achieving a high-quality, void-free bonding interface at these nanometer scales is paramount for device reliability. However, conventional high-volume manufacturing (HVM) heavily relies on complex organic chemical additives to achieve dense copper electrodeposition within these interconnect structures. Upon prolonged processing operation, these organic additives inevitably induce electrolyte aging, impurity contamination, and a severe reduction in thermal stability, which severely complicates process control and limits interconnect reliability. To overcome these critical bottlenecks, this study investigates a novel direct Cu-Cu bonding approach at a low thermal budget utilizing an additive-free, carbon dioxide-assisted (7.38 MPa, 40°C) electroplating process.
By leveraging the high diffusivity and low surface tension of compressed CO2, this physical modulation approach eliminates electrolyte aging and additive degradation issues common in conventional high-volume manufacturing. The resulting as-deposited CO2-assisted copper films exhibit a highly refined, dense, and homogeneous microstructure characterized by a significantly reduced average grain size of 0.82 μm (compared to 1.13 μm for the non-CO2-assisted film), representing a grain size reduction of 27.4%, along with a remarkably high Σ3 twin boundary fraction of 77.3% (compared to 55.6% for the non-CO2-assisted film). Upon thermal annealing at 300°C, the film maintains a sustained twin density with a Σ3 fraction of 61.4%, which serves as a rich structural energy reservoir that significantly accelerates grain-boundary migration and atomic coalescence during the bonding stage. To quantify the microstructural relaxation and defect density, Grain Orientation Spread (GOS) analysis was conducted via electron backscatter diffraction (EBSD), confirming a superior, stress-free recrystallization fraction of 68% (compared to 40.8% for the non-CO2-assisted film). Furthermore, macro-level X-ray diffraction reveals a pronounced enhancement in the (111) preferred texture, reaching a texture coefficient of 1.28, which inherently lowers the thermodynamic activation energy for surface atom migration.
Consequently, these combined microstructural and crystallographic advantages provide exceptional atomic mobility and enhanced interdiffusion across the potential bonding interface. This synergistic effect enables the formation of a direct Cu-Cu metallic bond at a compliant low temperature of 300°C and a pressure of 20 MPa. By establishing a robust metallurgical joint embrittlement, this innovative CO2-assisted physical modulation strategy provides a highly reliable, thermally stable, and environmentally benign interconnect solution tailored for the reliability requirements of advanced 3D packaging and small-pitch chiplet stacking.

Abstract:
Driven by the growth of artificial intelligence (AI), high-performance computing (HPC), and advanced 5G systems, the semiconductor industry continues to require interconnects that are faster, denser, and more power-efficient. Cu–Cu direct bonding has accordingly become one of the key technologies for three-dimensional heterogeneous integration. A major obstacle, however, is the thin native oxide that forms on copper surfaces during queue time and thermal handling. Because copper oxide conducts heat and electricity far less effectively than metallic copper, an oxide film left at the joint interface raises contact resistance, impedes heat dissipation, and lowers bonding yield. Clarifying how this interfacial oxide decomposes, and where the liberated oxygen goes during heating, is therefore essential for obtaining reliable oxide-free Cu–Cu joints.

The main difficulty in studying this issue is that a conventional bonding process cannot keep the buried oxide interface in a truly oxygen-free, high-vacuum condition while it is heated, so the intrinsic thermal response of the oxide cannot be resolved in isolation. To address this, a controlled Cu/oxide/Cu proxy structure was designed. Following acid cleaning, a thin native oxide layer with a thickness of 6–8 nm was grown on a copper base layer with an average grain size of approximately 200 nm. Subsequently, a thin copper film was deposited onto the oxide layer by sputtering followed by electroplating, thereby sandwiching the oxide layer between the two copper layers. This encapsulated configuration reproduces the oxygen-isolated environment characteristic of an ideal high-vacuum bonded interface. To characterize the decomposition behavior of the interfacial oxide, specimens with different initial oxide thicknesses were annealed at temperatures ranging from 200 to 280 °C. This approach enabled the systematic determination of the critical process window—defined by the combined effects of annealing temperature, holding time, and initial oxide thickness—required for the progressive decomposition and eventual removal of the interfacial oxide.

The cross-sectional microstructure and the corresponding oxygen distribution were characterized by scanning electron microscopy (SEM), transmission electron microscopy (TEM), and energy-dispersive X-ray spectroscopy (EDS). The results showed that the morphological evolution of the interfacial oxide was strongly governed by both the annealing temperature and the initial oxide thickness. At 200 °C, the oxide layer remained almost unchanged and continuous, with no obvious decomposition. However, after a certain annealing time at 280 °C, the oxide layer began to decompose. The released oxygen mainly diffused toward the finer-grained copper regions. EDS analysis showed that the oxygen distribution spatially coincided with the grain boundaries, indicating that diffusion mostly occurred along these boundaries. Furthermore, for a sufficiently long annealing time at 280 °C, the oxide completely decomposed in certain areas, allowing a few copper grains to grow directly across the original interface.

These findings indicate that clearing native oxide from a Cu–Cu joint is not a single-step removal process, but a coupled sequence of oxide fragmentation, decomposition, oxygen dissolution, grain-boundary diffusion, and local interfacial rearrangement. By separating these intrinsic events from the mechanical factors of real bonding, the proxy approach clarifies how native oxide evolves under high-vacuum Cu–Cu direct bonding and helps define suitable ranges of oxide thickness and thermal budget for advanced packaging and hybrid bonding.

Abstract:
Cu-Cu hybrid bonding has emerged as a key technology for next-generation three-dimensional integrated circuits (3D ICs) and advanced heterogeneous integration due to its capability of achieving high-density interconnects with reduced electrical resistance and improved signal performance. However, the inevitable surface oxidation of Cu during fabrication and atmospheric exposure remains a critical challenge, as the formation of native copper oxides suppresses atomic diffusion across the bonding interface and deteriorates the bonding quality and long-term reliability. Therefore, developing an effective surface passivation strategy that can protect Cu surfaces while maintaining excellent bonding capability is of great importance.
Silver (Ag) capping layers have attracted considerable attention as a promising surface protection strategy due to their excellent electrical conductivity and the capability of Ag oxides to be readily reduced to metallic Ag at relatively low temperatures (~150˚C). The conventional spontaneous galvanic process for depositing Ag on copper (Cu) is generally performed using silver nitrate (AgNO₃). However, this approach typically suffers from rapid galvanic replacement reactions because of the high concentration of free Ag⁺ ions, leading to excessive Ag growth, rough surface morphology, non-uniform coverage, and dendritic structures. Furthermore, thick Ag layers may remain at the bonding interface after thermal compression bonding, acting as a diffusion barrier and limiting Cu grain growth across the bonding interface.
In this study, an ammonia-based complex ion strategy was developed to precisely regulate the galvanic Ag deposition behavior on Cu substrates. In contrast to the conventional galvanic reaction, which relies on direct redox reactions between Cu and silver ions (Ag⁺), the modified deposition mechanism involves the formation of Silver-ammonia complex ion (Ag(NH₃)₂⁺), complexes through the coordination between NH₃ and Ag⁺, thereby reducing the effective concentration of free Ag⁺. Meanwhile, excess NH₃ coordinates with Cu and residual copper oxides on the surface, enabling Cu to release electrons, which subsequently serves as the electrons source for the reduction of Ag(NH₃)₂⁺. By adjusting the total NH₃ concentration in the deposition solution, the Ag deposition amount and reaction kinetics can be effectively controlled, leading to a more moderate and uniform galvanic deposition process. Consequently, a smooth, compact, and continuous ultrathin Ag capping layer with a thickness below 5 nm was successfully fabricated. The optimized Ag nanolayer effectively suppressed Cu surface oxidation even after 72 hours of atmospheric exposure, demonstrating excellent oxidation resistance and surface stability.
Furthermore, the influence of the complex-ion-assisted ultrathin Ag capping layer on the subsequent Cu-Cu hybrid bonding behavior was systematically investigated. Microstructural analyses revealed that the ultrathin Ag layer did not remain as a continuous interfacial layer after bonding. Instead, Ag atoms preferentially segregated along Cu grain boundaries during thermal treatment, while Cu grains grew continuously across the original bonding interface, indicating enhanced atomic diffusion and the formation of a high-quality metallurgical bond. The proposed complex-ion-controlled galvanic deposition strategy provides an effective and scalable approach for producing oxidation-resistant ultrathin Ag capping layers, offering great potential for reliable ultra-fine-pitch interconnects, advanced semiconductor packaging, and future heterogeneous integration applications.

Abstract:
Background: Advanced System-in-Package (SiP) architectures, driven by heterogeneous integration, impose stringent requirements on Electromagnetic Interference (EMI) shielding. To meet these demands, physical vapor deposition (PVD), specifically magnetron sputtering, has become the mainstream technology for conformal EMI shielding. However, continuous target erosion during the sputtering process introduces significant challenges for production lines. The resulting dynamic changes in plasma distribution and deposition rates lead to severe thickness variations and a degradation of coating uniformity across the three-dimensional structures of SiP modules. Addressing this stability issue is critical for ensuring reliable EMI shielding performance in high-volume manufacturing.

Methods: This study investigates the target erosion behavior and its impact on the conformal shielding thickness over complex 3D SiP geometries. The thickness of the sputtered shielding layers was measured using a high-precision X-ray Fluorescence Spectrometer (XRF). To establish an objective baseline, the entire target life cycles (measured in kilowatt-hours, kWh) of both Cu and SUS targets were continuously monitored and recorded. Based on the erosion profiles, a One-Factor-at-a-Time (OFAT) experimental design was formulated and executed during specific erosion stages. This systematic approach aims to screen the key sensitive parameters and identify the corresponding process compensation mechanisms.

Results: Preliminary experimental results demonstrate two significant findings regarding the spatial and temporal variations in the sputtering process. First, extensive baseline tracking established critical target life milestones for the Cu target. Beyond these specific milestones, the coefficient of variation (CV) of the surface coating thickness significantly increased, indicating a transition from a stable state to a highly degraded uniformity phase. This specific cut-off point provides a reliable quantitative index for staging the target life. Second, spatial variance analysis across the multi-die wafer identified the exact critical failure location. The analysis pinpointed the bottom-sidewall of the dies located in the overall bottom region of the wafer as the worst-case scenario for thickness collapse. The statistical evaluation showed a tremendously powerful effect size (Cohen's d > 3), proving that this severe degradation is an irreversible physical inevitability rather than random sampling noise. Consequently, this specific geometric point dictates the minimum allowable step coverage (SC) and establishes the crucial lower control limit for the manufacturing process.

Conclusions: Moving forward, the acquired OFAT experimental data will be utilized to construct a robust regression model. This model will generate a dynamic parameter compensation table, providing precise, stage-by-stage adjustments. Ultimately, this approach ensures consistent EMI shielding compliance across the entire target lifespan while effectively extending the equivalent target longevity.

Limitations: Due to Proprietary Information Protection (PIP) policies and the highly sensitive nature of advanced SiP manufacturing data, exact empirical values regarding specific target life milestones (e.g., precise kWh thresholds) and proprietary process parameters are omitted from this abstract. Nevertheless, the proposed statistical methodology, spatial variance analysis, and the overarching dynamic compensation framework remain robust and universally applicable to similar high-volume PVD processes.

Abstract:
This study presents a comprehensive and rigorous investigation into the microstructural evolution, crystallographic phase orientations, and multi-physical properties of electroplated copper (Cu) thin films regulated by gelatin additives. Furthermore, it systematically elucidates the profound impacts of these gelatin-induced structural alterations on the interfacial healing behavior and macro-electrical reliability during subsequent solid-state Cu-Cu thermal compression bonding (TCB). As the advanced electronic packaging industry heavily transitions toward high-density three-dimensional integrated circuits (3D ICs) and fine-pitch micro-interconnects, achieving high-quality direct Cu-Cu bonding under minimized thermal budgets has emerged as a critical technological milestone. However, during the industrial electrodeposition process, the incorporation of organic additives like gelatin fundamentally alters the intrinsic crystallographic characteristics of the copper matrix. The specific underlying mechanisms by which these altered matrix properties interfere with trans-interfacial atomic diffusion and grain boundary migration during solid-state welding have previously lacked a detailed, quantitative crystallographic explanation.In this research, electroplated copper thin films synthesized with the incorporation of gelatin additives were systematically evaluated against gelatin-free control groups fabricated under varying electrolyte conditions containing $20\text{ g/L}$ and $80\text{ g/L of H}_2\text{SO}_4$. Surface morphological observations conducted via scanning electron microscopy (SEM) on the as-deposited, unannealed films revealed that the gelatin-free copper matrices exhibited coarse, irregular, and bulky grain structures. This morphologic feature is primarily attributed to a lower nucleation rate relative to the grain growth rate in the absence of suppressing agents. In stark contrast, the gelatin-added copper film displayed an exceptionally dense, smooth, and ultra-fine-grained microstructure. This extreme grain refinement conclusively demonstrates that gelatin molecules operate as highly potent cathodic suppressors during the electrodeposition process. By significantly elevating the cathodic overpotential required for copper ion reduction, the presence of gelatin forces the electrochemical system to continuously generate a high density of new nuclei to sustain the applied current density, thereby establishing a highly refined and interconnected grain network.The subsequent microstructural transitions and crystallographic textures induced by thermal processing were analyzed via X-ray diffraction (XRD) and electron backscatter diffraction (EBSD). Following a vacuum annealing treatment at 300°C for 30 minutes, the XRD diffraction patterns of the gelatin-added group exhibited a highly pronounced increase in the (111) preferred orientation peak intensity, accompanied by a noticeable rise in the relative intensity ratios of alternative crystallographic planes, such as the (200) and (220) orientations. This experimental trend indicates that the adsorption and structural embedding of gelatin during electroplating effectively provide an enhanced thermodynamic driving force for comprehensive crystallization optimization and recrystallization during subsequent thermal steps, significantly upgrading the overall crystalline perfection while retaining a polycrystalline matrix. Quantitatively, EBSD inverse pole figure (IPF) mapping revealed that while the 100°C-annealed gelatin-free film maintained a matrix heavily dominated by continuous, coarse (111) grains, the 300°C-annealed gelatin-added group displayed a multicolored, highly interwoven pattern characteristic of multi-orientation and random-texture features. Despite undergoing thermal grain growth, the absolute grain size of the gelatin-added matrix remained heavily restricted locally and was statistically comparable to the unannealed control groups. This remarkable resistance against unlimited thermal grain coarsening at elevated temperatures is driven by the severe grain boundary pinning effect exerted by trace organic residues, alongside the structural constraints of the random crystallographic texture.Mechanically, the unannealed gelatin-added thin film exhibited superior microhardness and yield strength, conforming precisely to the classic Hall-Petch relationship owing to its extreme grain refinement. However, the subsequent 300°C vacuum annealing driven recrystallization and grain growth caused the macro-hardness to drop substantially. Electrically, the high density of grain boundaries within the unannealed gelatin-added copper layer triggered severe electron scattering, resulting in an initially high sheet resistance. This value successfully decreased to a low level comparable to the pure copper control group after the high-temperature thermal treatment effectively eliminated lattice defects and promoted grain growth. Furthermore, residual stress analysis via the sin²ψ method indicated that gelatin embedding and its subsequent desorption during electrodeposition accumulate significant in-plane tensile stress, which acts as a primary driver for substrate warpage in advanced packaging substrates. Fortunately, the 300°C vacuum thermal treatment effectively relaxed these microstructural defects, noticeably diminishing the Kernel Average Misorientation (KAM) strain hotspots and successfully releasing approximately 40% of the surface residual tensile stress.The core scientific contribution of this research lies in unveiling the exact crystallographic and thermodynamic mechanisms that govern the joint line during Cu-Cu bonding. Following solid-state thermal compression bonding performed at 300°C under a 50 MPa vacuum, cross-sectional SEM images demonstrated that the original bonding interface of the gelatin-free joints had completely vanished. This interface was replaced by a highly dense crystalline joint where numerous grains successfully grew across the original joint line, driven by robust, stress-assisted atomic diffusion and comprehensive void annihilation. In stark contrast, the gelatin-added bonding interface remained densely populated with a continuous chain of unhealed microvoids, which severely suppressed any trans-interfacial grain growth and boundary migration.Quantitative EBSD analysis conducted on the cross-sections post-bonding revealed the decisive crystallographic determinant behind this structural degradation: the gelatin-added copper matrix possessed a significantly higher fraction of low-angle grain boundaries (LAGBs, 2°–15°) prior to bonding compared to the pure copper group. During the 300°C thermal compression process, these thermodynamically unstable, high-energy LAGBs triggered severe kinetic competition within the copper layer. The available thermal and stress-driven atomic diffusion energy was preferentially consumed by internal matrix relaxation, dislocation reorganization, and the internal recrystallization of these LAGBs into stable high-angle grain boundaries (HAGBs) or $\Sigma3$ twin boundaries inside the bulk film. Consequently, this internal consumption drastically depleted the effective atomic flux that would otherwise be available for surface and bulk diffusion to migrate toward and fill the interfacial gaps. This explicit quantitative data confirms that the ultimate determinant of Cu-Cu direct bonding quality is the internal grain boundary characteristics of the electroplated matrix rather than simple initial grain refinement; the high-density LAGB structure induced by gelatin kinetically suppresses trans-interfacial diffusion, leading to severely degraded crystallographic fusion.Finally, this failure to achieve interfacial healing induced catastrophic macro-electrical degradation across the interconnects. Four-point probe measurements indicated an anomalous sheet resistance spike in the bonded gelatin-added joints, rising by several to tens of times compared to the seamlessly fused gelatin-free joints. This severe electrical failure is successfully explained via the classic Constriction Resistance Model. The continuous, unhealed microvoids remaining at the gelatin-added joint line severely compressed and restricted the effective electrical conduction area. Consequently, the electrical current lines could no longer pass linearly across the interface and were forced to bend sharply around the minute, isolated metallic contact spots. This microscopic distortion of current streamlines creates a massive additional constriction resistance that manifests macroscopically as a severe impedance spike.In summary, this study systematically clarifies the double-edged sword effect of utilizing gelatin additives in copper electroplating for advanced electronic packaging. Although gelatin successfully refines the as-deposited grain structure and enhances initial mechanical properties, it introduces an unfavorable, high fraction of low-angle grain boundaries. These LAGBs create intense kinetic competition between internal matrix recrystallization and interfacial atomic diffusion during thermal compression bonding, preventing void healing and driving catastrophic constriction resistance. These findings offer crucial crystallographic insights and practical guidelines for optimizing electrolyte formulations, additive designs, and bonding process windows in high-reliability advanced semiconductor packaging.

Abstract:
As artificial intelligence semiconductor packages continue to advance toward higher integration density, smaller form factors, and higher computing performance, thermo-mechanical reliability has become an increasingly important challenge [1]. High-performance devices generate significant heat during operation, and this thermal loading can induce deformation, stress concentration, and reliability degradation within package structures. In advanced packages, various materials with different thermal, mechanical, and physical properties are integrated within a limited volume. In particular, heterogeneous interfaces, solder joints, polymeric materials, and substrates can respond differently to thermal loading, making it essential to accurately evaluate their deformation behavior under practical operating conditions.
Micro-scale Digital Image Correlation (DIC) provides a powerful, non-contact method for visualizing and quantifying surface deformation and strain with high spatial resolution [2]. Compared with conventional point-based measurement techniques, microscopy-based DIC enables spatially resolved observation of localized deformation at critical package regions. Therefore, it is well suited for evaluating microscale thermo-mechanical behavior in electronic packages, flexible devices, and interconnect structures [3, 4]. By combining optical microscopy with digital image correlation, micro-DIC enables micro-scale strain mapping and has been successfully applied to precision bonding components [5] and flexible packages [6].
In this study, micro-2D-DIC was applied to characterize localized deformation in semiconductor package interconnects, with particular focus on solder joints, which are highly susceptible to time-dependent deformation and reliability degradation under thermal loading. To better emulate the thermal environment experienced by practical AI semiconductor devices, a localized heating approach was adopted to reproduce operational heat generation and combined with in-situ DIC measurements. Using this methodology, the thermo-mechanical response of package interconnect structures was monitored under realistic thermal loading conditions. Special attention was given to solder joints, where solder creep can occur due to sustained thermal exposure and stress accumulation. The time-dependent deformation behavior associated with solder creep was quantitatively analyzed by tracking strain evolution during localized heating.
The analysis indicates that localized heating can significantly affect strain accumulation and creep-related deformation within solder joint structures. This approach may provide a useful basis for investigating reliability degradation mechanisms under localized heating conditions that more closely resemble practical device operation. In addition, the applicability of micro-DIC was extended beyond metallic interconnects to polymeric package components, including epoxy materials and substrates. This demonstrates the potential of DIC-based analysis for evaluating deformation in amorphous material systems as well as solder interconnects.
By providing detailed visualization of localized strain evolution and package-level deformation behavior, this approach offers a useful pathway for understanding thermo-mechanical failure mechanisms in next-generation semiconductor packages. The proposed methodology can contribute to the early identification of reliability risks, the reduction of package warpage, and the development of design strategies for enhancing the reliability of advanced AI semiconductor packaging technologies.

Abstract:
INTRODUCTION
Modern AI and HPC systems require compact, high-current integrated voltage regulators, driving interest in magnetic-core inductors for on-die and in-package power delivery. This work presents an experimental and simulation-based study of single- and dual-coil BEOL-fabricated CoZrTa-core solenoidal inductors with 4–20 turns and core widths of 150–800 µm. Key metrics, including self-resonant frequency, RDC, saturation behavior, and inductance-to-RDC ratio, are evaluated. Although dual-coil designs improve saturation performance, all structures exhibit excessive I2RDC loss and insufficient current-handling capability for future AI/HPC applications.

METHODOLOGY
This work evaluates BEOL-fabricated single- and dual-coil CoZrTa (CZT) core solenoids, shown in Fig. 1a through 1c, for on-die and in-package integrated voltage regulators (IVRs) using measurements and EM simulations. The inductors have 65-µm-wide coils with 4–20 turns and anisotropic 3-µm-thick and 150–800 µm wide CZT cores. Measurements and Ansys HFSS simulations up to 10 GHz are used to extract self-resonant frequency (SRF) and DC resistance (RDC), where SRF defines the frequency range over which inductance (L) remains stable, while RDC affects efficiency, power integrity, and thermal reliability. Ansys Maxwell simulations with currents from 0 to 10 A evaluate saturation performance and current-handling capability.

Fig. 1 a) Isometric views of simulated single-(left) and dual-coil (right) solenoids with 6 turns; b) Top view detail of fabricated dual-coil solenoid; c) Cross-section detail of 12-turn dual-coil solenoid.

RESULTS
Fig. 2a and 2b compare measured (dash-dot curves) and HFSS-simulated (solid curves) L and R for 4- and 6-turn single-coil solenoids with a 500-µm-wide CZT core. Inductances agree within 2% from 10–100 MHz, while high-frequency resistance discrepancies are attributed to variation in copper thickness/length in fabricated vs. simulated solenoids and eddy effects not being captured in HFSS models.

Fig. 2 a) L vs. frequency for 4-(blue) and 6-turn (red) single-coil solenoids; b) R vs. frequency for 4-(blue) and 6-turn (red) single-coil solenoids; c) L vs. current for 4-turn single-coil solenoids with 150-500-µm-wide CZT cores.

Fig. 2c shows the inductance–current characteristics of 4-turn solenoids with 150–500 µm core widths, revealing poor saturation performance with a maximum saturation current of only 1.1 A, well below AI and HPC requirements. A contour plot of inductance for a 14-turn dual-coil and 400-µm-wide CZT-core solenoid is shown in Fig. 3a. The coils are inversely coupled with independent currents I1 and I2. L varies by ~22% over – 10 A ≤ I1, I2 ≤ 10 A, indicating fairly good saturation performance. However, RDC ≈ 580 mΩ per coil results in excessive and unsustainable I2RDC loss. Fig. 3b plots L/RDC versus turn count for single-coil solenoids. L/RDC represents the trade-off between energy storage and conduction loss. The maximum values are 52.9 and 108.3 nH/Ω for 4- and 20-turn inductors, respectively, which are substantially lower than those reported for TSV-coupled (597 nH/Ω) and thin-film (425 nH/Ω) inductors.

Fig. 3 a) Contour plot of inductance for 14-turn dual-coil solenoid with 400-µm-wide CZT core; b) L/RDC vs. # of turns for single-coil solenoids.

NOVELTY AND IMPACT
This measurement- and simulation-based study of BEOL CZT-core solenoidal inductors identifies key limitations for high-current AI and HPC power delivery. Dual-coil designs improve saturation via inverse coupling, but RDC remains high. The maximum L/RDC of single-coil solenoids is 108.3 nH/Ω, well below reported TSV-coupled (597 nH/Ω) and thin-film inductors (425 nH/Ω). Although single-coil designs maintain high SRF stability, their low saturation current (1.1 A for 4-turn devices) limits applicability for vertical power delivery. The novelty of this work is in the systematic evaluation of key design parameters and demonstration of intrinsic constraints of CZT-core BEOL solenoids under extreme AI/HPC current demands.

Abstract:
As the semiconductor industry approaches the physical limits of Moore's Law, high-density advanced packaging technologies, such as 2.5D/3D heterogeneous integration, have become crucial for maintaining performance of high-performance computing (HPC) and artificial intelligence (AI) hardware. Currently, the mainstream industrial manufacturing methods for TSVs, mainly rely on laser-induced deep etching (LIDE) or wet chemical etching. However, these mainstream techniques require consumption of larger amounts of highly corrosive and toxic chemicals (e.g., hydrofluoric acid), which not only increases manufacturing complexity but also violates contemporary environmental, social, and governance (ESG) requirements due to the disposal of hazardous waste.
In this study, the Corning Eagle XG glass substrates with a thickness of 300 μm is investigated by the ultrashort pulse picosecond UV-laser. Figure 1 reveals a top entrance diameter of 24.549 μm and a bottom exit diameter of 8.025 μm that are observed by an optical profilometry and measured with a cross-sectional microscopy. Based on the calculation of formula (1), the value of taper angle yields 1.578°. Figure 2 shows that diameters of another top entrance and bottom exit vias on the glass substrate studied.
Experimental results show that the TGVs with a high-aspect-ratio greater than 12 can be obtained by using the picosecond UV-laser percussion. Furthermore, these diameters of the top and bottom vias of TGVs will be given and the optimized taper ratio and the via surface roughness will be examined in the coming full paper. The high-aspect-ratio TGVs with a good quality via structure will be the candidate of providing an environmentally sustainable manufacturing solution for next-generation interposers in advanced heterogeneous integrated packaging.

Abstract:
With the rapid advancement of high-speed computing, broadband communications, and AI data center applications, differential signaling has played an increasingly vital role in high-speed data transmission systems. As operating frequencies extend into the millimeter-wave band, signal vias inevitably introduce parasitic inductance and parasitic capacitance, which can increase signal reflections and insertion loss, thereby degrading signal integrity (SI) performance.
This study investigates a differential through-via structure operating near 110 GHz. The geometric parameters of the differential signal via, via-pad, and anti-pad are first optimized to establish a baseline struc-ture that exhibits optimal transmission characteristics near the target operating frequency. Full-wave Ansys HFSS simulator are then used to evaluate the effects of via-pad stub compensation on the signal in-tegrity of high-speed differential through-via interconnects. The inves-tigated structures include a baseline configuration with and without the via-pad stub compensation, including open stubs and short stubs. Dif-ferential return loss (SDD11) and differential insertion loss (SDD21) are used as the primary performance metrics to measure the effect of via-pad stub compensation.
To further analyze the electrical behavior of via-pad stub structures, equivalent RLC circuit models corresponding to the open-stub and short-stub configurations are established and compared with the full-wave simulation results. This approach provides additional insight into the compensation mechanisms of via-pad stubs in high-frequency differential through-via structures.

Abstract:
Driven by the urgent needs of artificial intelligence (AI), high-performance computing (HPC), and mobile devices for large data storage, high bandwidth, and ultra-low power consumption, multi-chip vertical stacking architecture for high-density 3D NAND flash memory has become the mainstream paradigm for advanced memory chip packaging. The conventional stand-off stitch bond (SSB) process, characterized by its intricate multi-loop trajectories and frequent motion-mode switching, results in an elongated c Unit Per Hour (UPH) of approximately 32 seconds per unit. This process creates a critical throughput and cost bottleneck that hinders high-volume manufacturing viability.
Compared to the conventional stand-off stitch bonding (SSB) techniques, the emerging Cascade wire bonding technology is employed for stacking 3D NAND flash memory chips. Cascade wire bonding technology is implemented to reduce micro-mechanical stress within ultra-low wire-looping in the ultra-thin multi-chip stacking architecture. In this study, a systematic Taguchi design of experiments (DOE) was employed to screen the critical process factors governing the newly developed cascade wire bonding technique.

Abstract:
Introduction & BackgroundIn recent years, with the rapid growth of applications such as Artificial Intelligence (AI), High-Performance Computing (HPC), 5G/6G communications, autonomous driving, and data centers, the demand for high-frequency, high-speed, and high-power semiconductor components has continuously escalated. To overcome the limitations of conventional packaging in signal transmission, thermal dissipation, and physical form factors, advanced packaging technologies have emerged as a critical cornerstone for the entire AI industry. Consequently, the pressing needs for higher I/O counts, shorter signal transmission distances, and superior thermal management have driven the significance of packaging substrates to unprecedented heights.
Material Characteristics of Ceramic SubstratesRecently, ceramic substrates have garnered significant attention due to their exceptional material properties. Compared to traditional organic PCB substrates, ceramics exhibit higher mechanical strength, a lower coefficient of thermal expansion (CTE), excellent thermal conductivity, and superior high-frequency electrical characteristics, which effectively enhance packaging reliability and heat dissipation efficiency.

Abstract:
Abstract—We present a transistor-to-package thermal modeling framework for advanced 2.5D integrated systems. The target structure is modeled as a representative 2.5D IC, consisting of a high-power H100 logic die integrated with six HBM dies on a silicon interposer and cooled from the frontside by single-phase liquid cooling. In the logic die, heat is generated from active devices in the FEOL layer and spreads through both the frontside and backside thermal paths. Along the frontside path, heat propagates from the FEOL through back-end-of-line (BEOL), bonding oxide, carrier wafer, thermal interface materials, Cu lid, and heat spreader before reaching the liquid-cooling boundary. Along the backside path, heat spreads through the backside power delivery network (BSPDN), micro-bumps, silicon interposer, and package substrate. This modeling setup captures both the local heat spreading around active devices and the global heat-removal path from the logic die to the package cooling boundary.
To reduce computational cost while preserving transistor-level thermal accuracy, the model retains detailed VD+M0 and BVD+BM0 structures near the FEOL and represents the remaining metal layers with equivalent thermal layers. The detailed transistor structure is embedded within the lumped FEOL region to capture anisotropic heat spreading, local temperature gradients, and transistor-level thermal effects. The total temperature rise is decoupled into three heating mechanisms: transistor self-heating (TSH), hotspot heating (HSH), and background heating (BGH). TSH captures the local temperature rise inside active devices and is therefore strongly affected by device structure and nanoscale power map. HSH represents the additional temperature rise caused by localized peak power-density and lateral heat spreading around the FEOL. BGH describes the global temperature rise mainly governed by package-level thermal resistance and frontside cooling. For nanosheet and n-on-p CFET structures, n-on-p CFET shows a higher maximum temperature due to its increased transistor power and peak power density caused by device stacking. However, the thicker FEOL in CFET provides better nanoscale heat spreading, which reduces transistor self-heating compared with one-tier nanosheet devices.
We further evaluate several thermal mitigation techniques, including BEOL dummy vias, AlN bonding oxide, thermal vias, and high-thermal-conductivity BSPDN dielectrics. These techniques provide additional heat-dissipation paths through the interconnect, bonding layer, and backside power delivery network, thereby reducing the thermal impact of localized hotspots. In addition, TSV-middle, TreeFET, semiconductor-metal junctions, and P/N junction isolation are investigated as FEOL boosters for nanosheet and CFET devices. By introducing additional metals or single-crystal materials into the FEOL region, these boosters improve local heat spreading near the active devices and mainly reduce transistor self-heating and hotspot heating.

Abstract:
Fine-pitch Cu bump wafers are essential interconnection structures for advanced semiconductor packaging, heterogeneous integration, and high-density chip-level assembly. As bump pitch and solder volume continue to decrease, oxidation on the solder surface becomes a critical factor affecting solder reflow behavior. In conventional processes, organic flux is used to remove surface oxides and protect the solder during heating, thereby improving wetting and solder ball formation. However, in fine-pitch bump arrays, flux residues are difficult to clean completely and may lead to surface contamination, ionic residues, void formation, and reliability degradation. Therefore, establishing a fluxless reflow process requires a clear understanding of Cu bump oxidation behavior, surface chemical composition, and their influence on solder ball formation during reflow. In this study, fine-pitch Cu-pillar SnAg solder bumps were investigated through comprehensive inspection and surface analysis to clarify the relationship between oxidation conditions and fluxless reflow performance, specifically examining the bumps' ability to reshape into spherical solder balls under fluxless conditions.
A 6-inch Cu-pillar SnAg bump wafer was fabricated in-house as the experimental platform. The bump diameter was designed as 50 μm, with a 50 μm spacing and the bump height of approximately 50 μm. The solder composition was Sn-1wt.%Ag. Scanning Electron Microscopy (SEM) was first used to inspect the bump geometry, dimensional accuracy, and structural uniformity. After confirming the bump structure, Energy Dispersive Spectroscopy (EDS) and X-ray Photoelectron Spectroscopy (XPS) were applied to analyze the surface composition and oxidation behavior before and after surface treatment. EDS provided qualitative surface characterization, while XPS depth profiling was used for quantitative near-surface analysis, especially for Sn, O, and oxide-related chemical states. After reflow, SEM observation was conducted to evaluate solder spheroidization, surface reconstruction, and reflow morphology.
Preliminary EDS results showed that the oxide-related surface signals on SnAg bumps decreased after surface treatment, suggesting the effective reduction or suppression of oxidation. SEM observations further indicated that the oxidation condition strongly affected reflow quality. Bumps with reduced surface oxidation exhibited improved wettability and formed smooth, continuous, and well-defined solder balls after reflow. In contrast, untreated bumps showed wrinkled surfaces, incomplete reconstruction, and poor spheroidization behavior, which were attributed to the persistence of surface oxides. These results confirm that oxidation control is a key requirement for fluxless Cu bump reflow. Future work will extend this analysis approach to investigate smaller bump dimensions and further evaluate oxidation behavior and reflow performance in advanced fine-pitch interconnection structures.

Abstract:
With the rapid advancement of artificial intelligence (AI), high-performance computing (HPC), 5G/6G communications, and data center applications, electronic systems are facing increasingly stringent requirements for computational performance, data transmission bandwidth, power consumption, and package miniaturization. Consequently, conventional packaging technologies are becoming inadequate to satisfy the growing demand for high-density heterogeneous integration. Advanced packaging technologies have therefore emerged as a key enabler for improving system performance. Among these technologies, the fan-out multi-chip module (FOMCM) has attracted considerable attention owing to its substrate-free architecture, high I/O density, short interconnection length, superior electrical performance, excellent heat dissipation capability, and high heterogeneous integration capability. As a result, FOMCM has been widely adopted in high-performance computing systems, artificial intelligence processors, and advanced communication devices. Despite these advantages, the FOMCM package consists of multiple constituent materials, including silicon chips, redistribution layers (RDLs), polyimide (PI), molding compounds, and copper interconnects, each possessing distinct material properties and coefficients of thermal expansion (CTEs). During the manufacturing process, the package undergoes multiple thermal cycles involving high-temperature processing, cooling, curing, and molding compound shrinkage. Owing to the mismatch in CTEs among the constituent materials, residual stresses are generated during thermal loading and cooling, leading to package warpage. Furthermore, the viscoelastic behavior and chemical shrinkage of the molding compound, together with package geometry, further aggravate the warpage deformation. Excessive warpage may result in redistribution layer cracking, chip misalignment, micro-bump interconnection failure, and interfacial delamination, thereby significantly reducing manufacturing yield and degrading long-term package reliability. Therefore, accurately characterizing the evolution of warpage throughout the FOMCM manufacturing process and developing an effective numerical analysis methodology capable of predicting warpage deformation at different process stages have become essential research topics for advanced package design, process optimization, and reliability assessment.
This study investigates the process-induced warpage of FOMCM by developing a process simulation framework based on finite element analysis (FEA) combined with the element birth and death (EBD) technique. The proposed framework is capable of simulating package deformation throughout the entire manufacturing process while accounting for the sequential activation of process steps. To improve the computational efficiency of large-scale package simulations, an efficient modeling methodology is further developed to significantly reduce model complexity and simulation time without compromising analysis accuracy. A major challenge in FOMCM modeling arises from the redistribution layer (RDL), which consists of highly dense and intricate copper interconnects. Directly modeling the detailed RDL geometry results in an excessively large finite element model, substantially increasing preprocessing effort, computational cost, and memory consumption. To address this issue, this study proposes an efficient modeling approach that integrates trace mapping (TM) technology, the rule of mixtures (ROM), and FEA. First, the TM technique is employed to map the complex RDL geometries extracted from the electronic computer-aided design (ECAD) model onto a background finite element mesh, thereby eliminating the need to explicitly construct the detailed conductor geometry. Subsequently, the effective orthotropic thermomechanical properties of the RDL are derived using the Rule of Mixtures according to the volume fractions of copper and polymer materials within each finite element. This homogenization approach accurately preserves the thermal-mechanical characteristics of the RDL while substantially reducing the computational burden. Furthermore, an additional mesh simplification strategy is adopted by replacing numerous micro-bump structures with equivalent components, leading to a significant reduction in the number of degrees of freedom of the finite element model. The complete finite element model established using the proposed simplification strategies is illustrated in Fig. 1.
To validate the accuracy of the proposed TM/FEA-based efficient modeling approach, tensile and thermal loading analyses were first conducted. The displacement predictions obtained from the proposed model were compared with those from a detailed finite element model and a conventional isotropic Rule of Mixtures (ROM) model to evaluate the modeling accuracy. After the validation was completed, the proposed model was further applied to simulate the complete FOMCM manufacturing process and predict the process-induced warpage at each fabrication stage. During the process simulation, gravity, geometric nonlinearity, the viscoelastic behavior of the molding compound, and volumetric shrinkage were all taken into consideration to accurately capture the actual deformation behavior throughout the manufacturing process. The predicted warpage at each process stage was subsequently compared with experimental measurements obtained using the Shadow Moiré technique to verify the reliability of the proposed numerical framework. As summarized in Table 1, the simulated warpage agrees well with the experimental results, with the maximum deviation at each manufacturing stage remaining below 14%. Furthermore, the warpage contour comparison shown in Fig. 2 demonstrates excellent agreement between the numerical predictions and Shadow Moiré measurements after the singulation process, with a discrepancy of only 6.7%. These results confirm that the proposed simulation framework can accurately predict the evolution of process-induced warpage throughout the FOMCM manufacturing process.

Abstract:
The development of electronic packaging technologies with excellent heat resistance and high heat dissipation has become a major trend for high-power semiconductor devices. Conventional alumina ceramic direct bonded copper (DBC) substrates can no longer meet the heat dissipation requirements of high-power semiconductors. Aluminum nitride exhibits superior thermal conductivity, excellent electrical insulation, a low dielectric constant, a small coefficient of thermal expansion, and low dielectric loss. AlN ceramic direct bonded aluminum substrates can provide better thermal stability, improved thermal fatigue resistance, and lower specific weight, suitable for highly integrated high-power devices. In this study, an ultrasonic-assisted rapid transient liquid phase bonding process for AlN/Al in air was developed. At a bonding temperature of 520°C and an ultrasonic amplitude of 6.5 μm, the localized high temperature and micro-erosion generated by the Zn filler metal under ultrasonic cavitation enhanced the bonding process. The average shear strength of the AlN/Al joint increased with increasing ultrasonic vibration time. After 30 seconds of reaction bonding, the optimal shear strength of the AlN ceramic/6061 aluminum alloy joint reached 26.76 MPa, with an average shear strength of 21.61 ± 4.50 MPa. Under the cavitation effect induced by ultrasonic vibration, a large amount of aluminum dissolved into the filler metal. During isothermal solidification, the low-melting-point filler alloy phase at the bonding interface was eliminated, resulting in the formation of an aluminum-bonded AlN ceramic substrate with high heat resistance and low interfacial thermal resistance. In the high-temperature bonding strength test conducted at 450°C, the optimal shear strength of the AlN ceramic/aluminum alloy joint reached 4.97 MPa.

Abstract:
With the development of third-generation wide-bandgap semiconductor technology, power electronic equipment is evolving toward higher voltage, higher switching frequency, and higher power density. Due to the limited voltage rating of a single SiC MOSFET, series-connected devices are commonly required in medium- and high-voltage applications to improve the overall blocking capability. However, conventional series-connected schemes usually rely on multiple isolated gate drivers or complex active voltage-balancing control, resulting in complicated driving structures, synchronization difficulties, and uneven dynamic voltage distribution caused by device parameter mismatch. To address these issues, this paper proposes a high-voltage SiC MOSFET single-drive gate cascaded circuit, aiming to achieve reliable triggering and voltage balancing of multiple SiC MOSFETs using only one external gate-driving signal.

Abstract:
The rapid adoption of wide bandgap (WBG) semiconductors such as SiC and GaN has significantly increased the performance requirements of power electronic systems. Applications including electric vehicles (EVs), motor drives, and renewable energy converters require higher operating voltages, higher current density, and elevated operating temperatures. These trends place stringent demands on packaging materials used in power modules. Compared with conventional organic substrates used in low power electronics, ceramic substrates provide superior thermal conductivity, electrical insulation, and mechanical reliability. Ceramic materials such as Al₂O₃, AlN, ZTA, and Si₃N₄ are therefore widely used in power module packaging. In particular, direct bonded copper (DBC) and active metal brazing (AMB) technologies enable thick copper layers to be directly bonded onto ceramic substrates, providing excellent current carrying capability and efficient heat dissipation.
To support the increasing power density of modern power modules, the copper metallization thickness in AMB or DBC substrates is often increased to more than 100 μm. However, when thick copper layers are patterned using conventional chemical etching processes, severe lateral over etching occurs, leading to degraded dimensional accuracy, limited line width and spacing, and increased risk of electrical short circuits. In addition, emerging power module architectures increasingly require the coexistence of thick copper conductors for high current paths and fine line routing structures for signal interconnection or high density circuit layouts. Conventional thick copper patterning techniques are not well suited to simultaneously achieve both requirements on the same ceramic substrate.
To address these challenges, this study proposes a hybrid metallized ceramic substrate architecture that integrates a brazed thick copper conductor layer with a fine line metallization layer formed by sputtering and electroplating. The proposed structure enables precise formation of fine line circuits while maintaining the high thermal conductivity and current handling capability of thick copper metallization.
This hybrid approach provides a practical pathway to integrate high current power routing and high density signal interconnection on the same ceramic platform. Furthermore, the proposed metallization strategy offers a promising foundation for future intelligent power module architectures requiring higher integration density, improved thermal reliability, and more complex signal routing, enabling more compact and highly integrated IPM designs for next generation power electronics systems.

Abstract:
Gallium nitride (GaN) high electron mobility transistors (HEMTs) are attractive for power electronics due to their fast switching speeds and compact chip dimensions, but packaging design faces challenges in minimizing parasitic inductance and ensuring effective thermal management. In this work, we present a discrete packaging approach for horizontal 650 V, 60 A GaN power devices using a ceramic substrate designed for multi-chip integration rather than single-chip packaging. Silver-sintered electrical contacts were fabricated on direct plated ceramic (DPC) substrates through flip-chip bonding and mounted on a copper frame to provide both efficient heat dissipation and reliable electrical connection. Process-induced stress and package warpage were analyzed via simulation and validated through experimental measurements. Discrete packages were fabricated, their static electrical performance characterized, and reliability confirmed through 1000-cycle temperature cycling tests (TCT). The combined results confirm that this multi-chip ceramic substrate packaging technique is feasible and reliable for GaN-based power electronics applications.

Abstract:
With the rapid development of electric vehicles, renewable energy systems, and high-power electronic applications, power modules are increasingly required to operate under higher voltage, higher power density, and elevated temperature conditions. As a result, the substrate plays a critical role in electrical insulation, thermal management, and thermomechanical stability. Conventional ceramic substrates, such as zirconia-toughened alumina (ZTA) and silicon nitride active metal brazing (AMB) substrates, provide good insulation and thermal stability. However, the mismatch in the coefficient of thermal expansion between the copper layers and the ceramic core may induce thermal stress and warpage during thermal processes. In contrast, insulated metal substrates (IMSs) offer advantages in simplified processing, lower cost, and higher structural design flexibility. By using a thin high-thermal-conductivity resin insulation layer and adjusting the copper thickness configuration, IMSs have the potential to improve both heat dissipation and warpage behavior. Therefore, this study investigates the effects of Top/Bottom copper thickness configurations on the electrical, thermal, and thermomechanical performance of IMS substrates for power module applications.

In this study, ZTA, AMB, and various IMS substrates were compared. Commercially available ZTA, AMB, and three baseline IMS configurations were fabricated and experimentally characterized, while four additional extended configurations were established as parametric simulation models. Characterizations included dielectric breakdown voltage testing, steady-state thermal resistance measurement, and dynamic thermal warpage measurement via Shadow Moiré. In addition, SEM/EDX analysis was conducted to observe the filler distribution and elemental composition of the IMS insulation layer. Finite element models, calibrated by experimental results, evaluated the copper configuration's influence on pure-substrate warpage and module-level thermal resistance.

Results show AMB achieved the highest breakdown voltage (9.50 kV), followed by ZTA (8.78 kV) and IMS (4.91 kV). However, normalized by thickness, IMS dielectric strength reached 49.13 kV/mm, outperforming ZTA (27.44 kV/mm) and AMB (29.69 kV/mm), proving the thin resin layer provides superior dielectric capability per unit thickness. For thermal performance, AMB showed the lowest pure-substrate thermal resistance (0.037 K/W), followed by ZTA (0.054 K/W) and IMS (0.059–0.062 K/W). Simulation relative errors were below 6%. Module-level simulations indicated an asymmetric configuration with a 0.9 mm top copper layer reduced single-chip equivalent thermal resistance to 0.412 °C/W, closely matching ZTA (0.414 °C/W).

Dynamic measurements showed thermal-cycle warpage ranges of 284.0 µm for ZTA and 450.0 µm for AMB, whereas the fabricated IMS substrates remained below 10.0 µm, proving exceptional thermomechanical stability. Parametric simulations revealed a U-shaped trend between copper configuration and warpage. A nominally symmetric IMS structure did not exhibit the lowest warpage because the top copper was patterned, reducing its remaining metal volume relative to the bottom copper. An optimized 0.7/0.5 mm copper configuration compensated for this imbalance, minimizing peak warpage at 260 °C to 17.8 µm. Overall, IMS substrates can be optimized via copper configuration to balance thermal management and stability. The thickest-top configuration suits heat-dissipation-prioritized applications, the 0.7/0.5 mm configuration is preferable for low-warpage requirements, and the symmetric structure serves as a balanced configuration.

Keywords: power module, insulated metal substrate, copper thickness configuration, thermal resistance, thermal warpage, dielectric strength, finite element simulation

Abstract:
Gallium nitride high electron mobility transistors (GaN HEMTs) are characterized by fast switching speeds and small chip sizes, presenting a major challenge in achieving low parasitic inductance and high heat dissipation in power electronics packaging. Traditional wire-bonding packaging introduces significant parasitic inductance during high-frequency switching; moreover, its limited thermal path restricts heat dissipation. To overcome these limitations, this work focuses on the development of a discrete GaN device utilizing flip-chip bonding technology. By eliminating bond wires, this approach drastically minimizes loop inductance and large-area bumps for enhanced thermal management, thereby fully high-frequency and high-power potential of GaN devices make possible.
In this paper, an optimized packaging technique is developed for the fabrication of horizontal 650V, 30A GaN power transistors in discrete packages. The electrical contacts and die attachments were evaluated by comparing the performance of wet and dry silver paste assembly processes, and utilizing high-thermal-conductivity pressureless silver on direct plated ceramic (DPC) substrates via flip-chip bonding technology. The Thermal-electrical simulations were also conducted and compared with actual experimental samples. Additionally, the study revealed that both the fabrication process of the silver paste joints and the size of the coated contact area significantly influence the actual thermal resistance.
By systematically analyzing these factors to identify the optimal assembly conditions, the package's thermal resistance was effectively lowered, and the package warpage was successfully controlled and maintained well below the target. The fabricated packages also exhibited excellent electrical performance and robust reliability. Under rigorous 1000-cycle temperature cycling tests (TCT), the packages demonstrated minimal degradation with a thermal resistance variation (ΔRth) and a joint resistance variation (ΔRon).

Abstract:
In recent years, data center power consumption has increased significantly, driving the adoption of 48-V power architectures due to their improved power delivery efficiency and reduced distribution losses [1]. Between 2020 and 2030, data center power consumption is projected to increase by approximately 2.5 times, driven by the rapid expansion of cloud computing and AI workloads. Furthermore, from 2024 to 2030, electricity consumption in data centers is expected to grow at nearly 15% annually, which is more than four times faster than the growth rate of total global electricity consumption [2]. This paper presents the design, implementation, and experimental validation of a 3 kW full-bridge LLC resonant converter utilizing 650 V Silicon Carbide (SiC) MOSFETs on the primary side and silicon MOSFETs for synchronous rectification on the secondary side, targeting high-efficiency AI server power supply unit (PSU) applications. The converter is designed to meet and exceed the 80 PLUS Platinum efficiency standard, achieving a measured peak efficiency of 91.7% at a switching frequency of 240 kHz. The converter employs a full-bridge primary topology formed by two half-bridge stages, each switching a pair of 650 V, 25 mΩ SiC MOSFETs. The resonant tank comprising a 15 µH resonant inductor (Lr), a 27 nF resonant capacitor (Cr), and a transformer with a 15:2:2 turns ratio and a 75 µH magnetizing inductance (Lm) is tuned to a resonant frequency of 250 kHz. The switching frequency operates between 220 kHz and 280 kHz under normal conditions, extending up to 450 kHz during light-load or soft-start transients.
Zero-voltage switching (ZVS) is maintained across the full load range using a 150 ns dead time, leveraging the inherently low output capacitance (Coss) of SiC devices to minimize circulating energy and primary-side conduction losses. On the secondary side, full-wave synchronous rectification is implemented using 80 V silicon MOSFETs in parallel, driven by an IR1161L smart-rectifier controller via isolated Si8271AB gate-driver ICs. Closed-loop output voltage regulation is achieved through the ICE1HS01/G resonant controller, which also provides over-current protection (OCP) at 18 A, brown-out protection with a turn-on threshold at 370 V and shutdown at 340 V, and output voltage feedback for regulation to 50 V across an input range of 380 V to 420 V. Experimental results confirm correct ZVS operation at Vin = 400 V and fs = 250 kHz, with synchronized gate-drive timing and resonant inductor current waveforms consistent with theoretical predictions. The 3 kW full-bridge LLC resonant converter utilizing 650 V SiC MOSFETs achieves a peak efficiency of 91.7% demonstrating its suitability for high-density data center, telecom, and industrial AC/DC SMPS designs requiring galvanic isolation, wide-range ZVS operation, and robust system protection.

Abstract:
Wire bonding remains one of the most prevalent interconnection technologies in advanced semiconductor packaging. In ultrasonic copper (Cu) ball bonding, the bonding quality and pad deformation are dictated by the strongly coupled effects of bonding force, ultrasonic vibration, frictional heating, plastic deformation, and acoustic softening. While previous numerical studies typically model the ultrasonic effect by explicitly applying high-frequency displacements or vibrations to the bonding tool, this approach is often restricted to a limited number of frictional cycles due to the stringent time-step requirements of explicit dynamic analysis. Consequently, reproducing a full-scale bonding process at physical operating frequencies entails tracking thousands of vibration cycles, rendering the computational cost prohibitive and process-level simulations impractical on standard computing resources.
To overcome this computational bottleneck, this study proposes a highly efficient, equivalent thermo-mechanical modeling framework for ultrasonic Cu ball bonding. Rather than explicitly resolving the entire high-frequency vibration history, the ultrasonic effect is decoupled into two analytical inputs: equivalent material softening and equivalent heat generation. The mechanical response of the Cu wire/ball is modified using stage-dependent softening coefficients derived from relative ultrasonic power levels, whereas the thermal contributions are accounted for via frictional and plastic deformation heating. This macro-scale approximation successfully integrates the primary physical mechanisms of ultrasonic bonding into the finite element model without the computational burden of cycle-by-cycle tracking.
Finite element simulations are conducted using ANSYS LS-DYNA. To establish a simplified yet physically interpretable framework, the bonding process is discretized into three distinct stages: impact, static force, and ultrasonic-equivalent. This approach facilitates the dynamic application of stage-specific bonding forces, scrub motions, heat fluxes, and material properties. Furthermore, the mechanical parameters of the Cu wire and aluminum (Al) pad are calibrated via empirical nanoindentation measurements, ensuring that the modeled properties accurately reflect the true behavior of the actual bonding materials. The proposed framework is subsequently utilized to analyze bonding-induced deformation, focusing specifically on the interaction between the Cu ball and Al pad during the ultrasonic-equivalent stage.
Compared to direct vibration modeling, the proposed equivalent approach drastically reduces the computational overhead associated with explicit cycle tracking while preserving the critical thermo-mechanical mechanisms governing deformation. By substituting high-frequency cyclic loading with equivalent thermal and softening inputs, the model presents a highly practical alternative for full-process simulations of ultrasonic Cu ball bonding. Ultimately, this methodology enhances the feasibility of large-scale deformation predictions, supports the rigorous evaluation of Al pad thinning and residual thickness, and establishes a robust numerical foundation for optimizing bonding parameters in advanced semiconductor packaging applications.

Abstract:
Rapid heat spreading and low thermal resistance bonding interfaces are essential for modern advanced packages of high-performance computing chips and high-power electronics. Because of its exceptional thermal conductivity above 2000 W/m∙K, diamond has become a promising material. The heterogeneous integration of diamond with commonly used semiconductors faces tough challenges against achieving low thermal resistance by low-temperature bonding of semiconductors with diamond while maintaining physical integrity after thermal cycling. This study investigates indium-based bonding of diamond with silicon with surface coatings of Ti/Ni/Au and Ti/Cu/Au at low temperature. Thermal annealing is applied to reduce the thermal resistance of the diamond-silicon bonds with a core thermal resistance of 0.0188K/W when 75µm indium preform was applied. It is expected to be lower when smaller gaps exist between two solid surfaces to be bonded and a thinner indium preform is used.

Abstract:
System-in-Package (SiP) technology is widely adopted for portable electronics to achieve high functional integration. To enable cost-effective SiP miniaturization and 3D integration, through-mold interconnect (TMI) technologies—such as laser-drilled vias, vertical wire bonding (VWB), and copper pillars—have emerged as promising solutions. Among these, vertical wires offer a high aspect ratio and fine-pitch capability. However, while vertical wires are extensively used in wafer-level and package-level TMIs, its application in board-level interconnections remains limited. Conventional substrate-to-board solutions, such as solder joints and copper pillars, suffer from limited aspect ratios and high manufacturing complexity. To address these challenges, this work proposes a vertical wire-based substrate-to-board TMI architecture for double-sided molded SiP module applications.

To evaluate the applicability of the proposed vertical wire structure for RF and power SiP applications, both RF transition performance and current-carrying capability were characterized through simulation and measurement. The proposed vertical wires were bonded onto the top layer of a four-layer BT substrate and subsequently underwent molding and solder ball mounting processes to form the VWB module. Each vertical wire was formed using a 2-mil-diameter bonding wire with a length of 300 μm and a pitch of 250 μm.

The VWB modules were assembled onto test EVBs for RF and current-carrying capability measurements. Two distinct test vehicles were developed. The first was an RF characterization vehicle designed to assess high-frequency signal transitions between the VWB module top pad and the EVB top pad. The second was a current-carrying capability test vehicle incorporating a dedicated loopback path routed from the EVB, through the module routing and vertical wire interconnects, and back to another EVB pad for fusing current evaluation.

For RF characterization, the measured insertion loss of the proposed vertical wire structure was approximately 0.003 dB/μm at 60 GHz. The full-wave electromagnetic simulation results were in close agreement with the experimental measurements. The low insertion loss indicates that the proposed vertical wire structure is well suited for high-frequency RF SiP applications.

For current-carrying capability characterization, transient electro-thermal measurement was conducted using a 0.3-s pulsed current ramp-up test starting from 1 A. As the current was ramped up, an open-circuit failure was found at 8 A injection. Non-destructive 3D X-ray microscopy confirmed that the 2-mil vertical wires remained completely intact. Instead, the failure was explicitly located at the module-to-board solder joints. These results indicate that the current-carrying limit of the proposed architecture is governed by the system-level solder interconnections rather than the vertical wire bonds themselves, thereby demonstrating the robustness of the proposed vertical wire structure under high-current operating conditions.

Overall, the proposed architecture combines low RF insertion loss with high current-carrying capability, making it a promising interconnection solution for advanced RF and power SiP applications.

Abstract:
Advanced semiconductor packaging increasingly relies on high-density copper redistribution layers (Cu RDLs) to meet the demands of miniaturization, and fine-grained Cu RDLs offer excellent mechanical and electrical properties at reduced scales. However, they are highly susceptible to surface oxidation, corrosion, and electromigration due to higher surface-area-to-volume ratio and elevated current density.
These problems can degrade the reliability of the interconnects in the advanced packaging technologies. To mitigate these issues, proposing a coating as passivation or capping layers on fine-grained Cu RDLs would be important. Such layers serve as physical and chemical barriers, protecting the copper from environmental and electrochemical degradation by enhancing the overall thermal, chemical, and electrical stability of the RDL structure. Among potential passivation materials, palladium (Pd) has emerged as a promising candidate due to sharing the same face-centered cubic (FCC) crystal structure with a moderate lattice mismatch, which inherently facilitates the formation of a consistent, low-stress, and highly adherent interface. During the annealing, rather than forming detrimental brittle intermetallic compounds (IMCs), the thermal energy drives atomic interdiffusion and the interaction between Pd and Cu atoms at the interface leads to the formation of a stable solid solution or intermetallics (e.g., Cu3Pd or CuPd). This localized alloying process significantly strengthens the metallurgical adhesion and effectively relaxes the residual stresses accumulated during the initial deposition phase. Furthermore, the conformal Pd layer serves as a robust barrier against ambient oxygen. Even under elevated temperatures, the dense Pd coating suppresses the out-diffusion of Cu atoms, thereby preventing the formation of highly resistive copper oxides (CuO or Cu2O) at the surface.
However, capping a highly conformal and uniform Pd coating on fine-grained Cu lines with high aspect ratios would be a major challenge. We often fail to coat the vertical edges and bottom corners of redistribution layer (RDL) lines effectively when using Traditional techniques like thermal evaporation and standard electroplating. In our work, we fabricated fine-grained Cu lines measuring 800 μm in length, 10 μm in width, and 5 μm in thickness on an RDL die featuring a Ti barrier, a Cu seed layer, and precisely patterned photoresist. After electroplating, we removed the surrounding Ti, Cu, and photoresist layers thereby using acetone and appropriate etchants to expose the fine-grained Cu lines. For the passivation layer, we utilized electroless plating to deposit a thin layer of Pd over the exposed fine-grained Cu lines. This method ensures consistent coverage across the top surface, sidewalls, and the bottom corners of the lines. To carefully examine the microstructures, we used a focused ion beam (FIB) and a scanning electron microscope (SEM) which equipped with electron backscattered diffraction (EBSD), to observe the cross-sections. We also used energy-dispersive X-ray spectroscopy (EDS) to analyse the chemical elements on the surface.

Abstract:
Wire bonding remains one of the most widely used interconnection technologies in electronic packaging because of its process maturity, high throughput, and compatibility with various substrate metallizations. In gold wire bonding, the bonding pad acts as the intermediate layer between the wire and the substrate, and its material composition, surface condition, and metallization process directly affect bondability and long-term reliability. Conventional heated substrates are widely used in thermosonic gold wire bonding to provide the thermal energy required for interfacial formation. However, substrate heating generally involves a relatively large heating area, slower thermal response, and potential thermal limitations for temperature-sensitive substrate materials. In this study, blue-laser local heating is proposed as an alternative heat source to conventional substrate heating for 25 μm gold wire bonding. The feasibility of this approach and its influence on bonding reliability are evaluated through theoretical estimation and experimental characterization.

A transient heat transfer and energy balance model was established to estimate the laser power required to heat an Au surface from room temperature to the process temperature recommended for the HB05 wire bonder. A control volume approach was employed to describe the localized heating behavior induced by a blue laser with a wavelength of approximately 450 nm. The model considers the relatively higher optical absorption of Au in the blue wavelength range, the rapid thermal diffusion associated with highly conductive metallic materials, and the balance between localized energy input and conductive heat loss at the microscale bonding region.

To verify the effect of blue-laser-assisted heating on bonding quality, three bonding conditions were compared: room-temperature bonding, conventional heated-substrate bonding, and blue-laser-assisted bonding. The bonded interfaces were evaluated using pull/shear force tests, surface morphology analysis, and scanning electron microscopy. The results show that the room-temperature bonded samples exhibited a more pronounced serrated cross-sectional morphology, indicating less uniform interfacial formation. When the substrate was heated to the platform temperature, the bonded interface became smoother and more continuous. In comparison, the blue-laser-assisted samples exhibited a smaller serrated cross-sectional feature and a more localized thermal effect near the bonding region. These morphological observations are consistent with the mechanical testing results, suggesting that localized blue-laser heating can improve interfacial formation while reducing the overall thermal load on the substrate.

The results demonstrate the potential of blue-laser-assisted local heating as a feasible alternative to conventional heated substrates in gold wire bonding. This approach may provide a useful pathway for selective, low-thermal-load bonding processes in electronic packaging applications, particularly for substrates that are sensitive to global heating.

Abstract:
As high-speed interfaces continue to scale to higher data rates—such as PCIe Gen7 operating up to 128 GHz and DDR5 MRDIMM at 12800 MT/s—maintaining robust signal integrity across printed circuit board (PCB) channels becomes increasingly challenging. Even within the same manufacturing vendor, variations in laminate materials can introduce inconsistent electrical performance and lead to unexpected outlier behavior. This work presents a study of FIO PCIe channel impedance characteristics on an advanced server platform using two high-speed materials, IT-968G and TU883A. The data is obtained using Intel Automated In-Board Characterization (AIBC) and includes main routing, via, and pin field regions, followed by statistical evaluation using process capability metrics (Cp/Cpk).
The results demonstrate that both materials achieve acceptable global process capability in main routing structures, indicating that overall manufacturing control is sufficient to meet baseline high-speed design requirements. However, the IT-968G configuration exhibits sample-dependent outliers within the via and pin-field regions, highlighting that process variation becomes increasingly critical as data rates scale. In contrast, the TU883A implementation shows a more uniform performance distribution across all measured structures, with no evident outlier behavior in the evaluated dataset.
These observations indicate that process variation and distribution shifts have become critical limiting factors for channel reliability. Traditional channel TDR validation performed by validation teams may not adequately capture such sample-dependent effects, highlighting the need for fine-grained statistical analysis and large-scale, data-driven validation to ensure robust performance in high-speed systems.
To address this challenge, an Automated In-Board Characterization (AIBC) methodology is introduced to enable high-volume data collection, automated analysis, and rapid identification of variations across different structures and material configurations. By leveraging large-scale measurement datasets, AIBC provides a scalable approach to detect outliers, correlate structure-specific variations, and support design and manufacturing optimization. This capability helps reduce debug iterations, improve design-to-manufacturing correlation, and enhance overall channel robustness in next-generation high-speed systems.

Abstract:
The rapid advancement of artificial intelligence (AI) and high-performance computing has accelerated the demand for fine-pitch semiconductor packaging with increased I/O density. As interconnection pitches continue to decrease, conventional flux-assisted flip-chip bonding suffers from incomplete flux removal due to the reduced chip-to-substrate gap, resulting in reliability degradation and increased process complexity. Therefore, flux-less bonding technologies capable of suppressing Cu oxidation have become increasingly important for next-generation semiconductor packaging. In this work, a room-temperature plasma surface modification process was developed to realize reliable flux-less flip-chip bonding by simultaneously removing native Cu oxides and suppressing re-oxidation through Cu nitridation. A 40-μm-pitch flip-chip test vehicle was designed and fabricated to evaluate the proposed bonding process. Native oxides on the Cu pads were first removed using Ar/H₂ plasma treatment, followed by N₂ plasma exposure to form a Cu₄N passivation layer without external heating. The overall fabrication process and plasma treatment sequence are illustrated in Fig. 1. The plasma-treated Cu surfaces were characterized using solder dipping experiments, cross-sectional microstructural observations, and X-ray photoelectron spectroscopy (XPS). Under the optimized plasma condition, the treated Cu pads exhibited significantly improved solder wettability together with the formation of a continuous Cu₆Sn₅ intermetallic compound at the solder/Cu interface. XPS analysis further confirmed the appearance of characteristic Cu₄N peaks accompanied by a substantial reduction in Cu oxide-related signals, demonstrating successful room-temperature plasma nitridation. Representative solder wetting behavior and XPS results are presented in Fig. 2. The proposed room-temperature plasma process provides an effective approach for replacing conventional flux-assisted surface preparation while simplifying the flip-chip bonding process. The combination of Cu oxide removal and Cu₄N passivation enabled stable solder interfacial reactions without flux, demonstrating the feasibility of plasma-assisted flux-less bonding for fine-pitch semiconductor packaging. These results suggest that room-temperature plasma nitridation is a promising surface engineering technology for future high-density semiconductor packaging applications.

Abstract:
The rapid development of electronic products has increasingly emphasized multifunctionality, miniaturization, and lightweight design. In recent years, High Bandwidth Package on Package (HBPoP), a potential processor solution, has been proposed for applications in smartphones, tablets, and other consumer electronics. Its primary advantages include high bandwidth and high-performance computing capabilities.
Since package warpage is a key factor in the assembly process, it is essential to investigate HBPoP prior to its practical implementation. During the die bonding process, chips fabricated with a 2 nm process and strip substrates equipped with jig may experience mismatch during the reflow soldering process, leading to bump non-wetting phenomena. This can further affect electrical yield and result in product failure. In practice, customer-specified 2 nm chips and strip substrates from designated suppliers may be used. To improve the bonding yield between the chip and the strip substrate, the jig mounted on the strip substrate becomes a key evaluation factor. This study evaluates these critical factors and validates their effectiveness through warpage measurements, thereby providing an engineering solution.
We will discuss using Shadow moiré technology to analyze Warpage measurements indicate that, at room temperature, the 2 nm chip exhibits a “crying face” (concave) warpage profile. When the temperature reaches 220–245 °C (the lead-free die bonding process temperature), the warpage direction changes to a “smiling face” (convex). In contrast, during the die bonding process, the strip substrate with jig exhibits a “crying face” warpage direction at 220–245 °C. This clearly indicates a mismatch in both warpage direction and magnitude between the chip and the substrate during bonding.
The jig consists of two main components: a cover jig (upper jig) and a board jig (lower jig). This study modifies both the cover jig and the board jig with the objective of altering the warpage direction and magnitude of the substrate in the high-temperature range, thereby achieving better matching between the chip and substrate.
Specifically, the cover jig is investigated by varying the window opening size to study its effect on warpage values. The board jig is redesigned based on the concept of heat conduction (Fourier’s law of heat conduction) to modify the jig and achieve a change in warpage direction. By improving the bonding yield in the die bonding process and reducing process risks such as bump non-wetting—which can affect electrical yield and lead to product failure—this study evaluates key factors and verifies their effectiveness through warpage measurements, providing a practical engineering solution.

Abstract:
This study addresses inefficiencies in manual data processing by integrating multi-site on-premise systems into a unified Azure-based cloud platform, using the “COD Digitalization Optimization Project” as a case study. It focuses on consolidating data from SAP, MES, M365, and peripheral systems into Power BI through Azure cloud technologies to improve data consistency, operational efficiency, and decision-making effectiveness
To address these issues, the proposed architecture utilized Azure Data Factory for automated ETL processes, Azure Blob Storage for scalable data staging, Azure Synapse Analytics for high-performance processing, and Azure Analysis Services for data modeling, and Power BI for real-time visualization. This end-to-end pipeline replaced fragmented manual reporting with a standardized, automated framework.
The implementation demonstrated significant improvements in operational efficiency and data accuracy. Automation reduced processing time, while standardized logic ensured cross-system consistency. Real-time dashboards enabled stakeholders to analyze KPIs effectively, supporting more informed decision-making.
Overall, this research demonstrates that adopting a cloud-based data integration strategy can transform traditional, labor-intensive data management into a scalable, reliable, and efficient analytical ecosystem. It not only provides a single source of truth across the organization but also lays the foundation for future enhancements, including the integration of artificial intelligence and machine learning for predictive analytics and anomaly detection.

Abstract:
The study presents a structured approach for deploying topic‑based AI agents within an enterprise knowledge and KPI management environment, using the integration of Microsoft Copilot Studio, Mfg. KPI Dashboard, and the Alarm & Action Platform as a practical framework. The objective is to enhance the efficiency of KPI analysis, improvement tracking, and cross-site collaboration across multiple manufacturing sites and product divisions.
In conventional operations, KPI monitoring and issue resolution processes are often hindered by fragmented data sources, inconsistent workflows, and limited knowledge reuse. These challenges lead to prolonged response times and reduced transparency. To address these limitations, the proposed framework integrates Power BI for KPI visualization, SharePoint for centralized action and knowledge management, and Copilot Studio for building domain-specific AI agents capable of natural language interaction.
The core methodology defines a six-step agent development process, including topic scoping, knowledge consolidation, agent configuration, knowledge embedding, prompt optimization, and validation. By applying structured prompt engineering principles—such as goal definition, contextual grounding, constraint control, and standardized output formatting, the approach effectively reduces hallucination risks and ensures consistent, high-quality responses.
Implementation results demonstrate substantial improvements in information retrieval efficiency and decision support. AI agents can interpret domain-specific queries, support multilingual interaction, and deliver actionable insights based on internal knowledge bases. Research shows that the use of AI agents can reduce information retrieval time by over 90% in typical operational scenarios.
Overall, this study illustrates that integrating generative AI with enterprise data platforms can significantly improve knowledge accessibility, operational efficiency, and continuous improvement processes. The proposed framework provides a scalable and replicable model for deploying AI-driven assistants, establishing a foundation for future advancements such as multi-agent collaboration and automated workflow integration.

Abstract:
This paper presents a socket lid fixture fabricated using 3D printing and computer numerical control (CNC) machining. The proposed fixture is applicable to the 5G FR2 band, covering frequencies from 24.3 GHz to 40.0 GHz. Measurements show that the fabricated fixture recovers up to 53% of the EIRP degradation introduced by a conventional socket lid at 24.3 GHz for both antenna-in-package (AiP) and antenna-on-package (AoP) devices. The most significant improvement is observed at 24.3 GHz. This work demonstrates the feasibility of the proposed approach for over-the-air (OTA) measurement, failure analysis, and automatic test equipment (ATE) applications.
In recent years, antenna-in-package (AiP) and antenna-on-package (AoP) devices have been connected to the motherboards of mobile devices via board-to-board (B2B) connectors. However, device interconnection has gradually shifted from B2B connectors to surface-mount technology (SMT)-based processes. As a result, device testing, including over-the-air (OTA) measurement, failure analysis, and automatic test equipment (ATE) testing, requires the use of socket-based testing solutions. However, conventional socket lid design cause up to 53% EIRP degradation under the evaluated FR2 OTA test conditions, which is recovered by the proposed fixture.
A conventional socket lid typically adopts a symmetric clamping mechanism consisting of two side-mounted arms with spring assistance to securely hold the device on a central base. This design enables rapid loading and unloading while ensuring stable positioning during operation. However, the conventional socket lid design introduces additional insertion loss and radiation interference, which significantly degrade EIRP performance at 24.3 GHz. To overcome this limitation, the proposed socket lid fixture is designed with reduced lid thickness and minimized side-mounted arm dimensions of 5 mm to suppress radiation interference. The reduced thickness and arm dimensions reduce physical obstruction and electromagnetic interference, thereby improving the radiation efficiency and EIRP performance. This design effectively minimizes RF blockage between the antenna and free space, and this improvement is critical for maintaining reliable OTA performance in 5G FR2 applications.
The proposed socket lid fixture was fabricated using both 3D printing and CNC machining to verify its EIRP performance. 3D printing was employed for rapid prototyping and preliminary design validation, while CNC machining was used to ensure the precision and reliability of the final design. EIRP measurements were performed using AiP and AoP devices operating in the 5G FR2 band. The measurements were in a direct far-field antenna measurement setup to ensure accurate characterization of radiated performance. Based on the EIRP measurement results obtained from AiP and AoP devices, the proposed socket lid fixture recovers EIRP performance by 53% at 24.3 GHz.

Abstract:
Blind spot accidents which pose a major road safety concern usually occur while changing lanes, improper signaling, or turning, especially in case of large vehicles like trucks and commercial transport systems that have big no-zones around them. This can be very critical and dangerous considering passenger vehicles may get camouflaged in these blind spots and cause serious accidents. Traditional blind spot detection techniques that use mirrors or single sensors have a small field of view, a lot of false alarms, and don't work well in different environmental conditions. This paper describes a smart Blind Spot Detection (BSD) system for large vehicles that combines YOLOv8-based deep learning object detection with dual camera side-by-side and panoramic image stitching. Using two cameras we have demonstrated both side-by-side stitching for ORVM cameras and panoramic stitching for rear cameras. A YOLOv8 model that has been trained in vehicle classes analyzes the stitched frame to find and sort threats. Vehicles are the main targets for detection, and pedestrians are the secondary targets. An embedded microcontroller controls the system and sends out visual and audible alerts when it finds something. We have also integrated the basic YOLOv8 model for pedestrian and object detection. The proposed system aims to have a detection rate of over 90% and a response time of less than one second. It is a cost-effective and scalable safety solution that can be installed in heavy vehicles that are already on the road.

Abstract:
With the advancement of semiconductor integration, advanced packages increasingly employ heterogeneous materials, fine-pitch interconnects, and multilayer bonding architectures. In these structures, thermomechanical deformation cannot be interpreted from global package warpage alone, because differences in coefficient of thermal expansion, bending stiffness, and mechanical constraint among the package, solder interconnects, and PCB (printed circuit board) generate complex local deformation fields. This issue is particularly important in BGA (ball grid array) package assemblies, where package-level warpage and local solder joint deformation are strongly coupled. The deformation mismatch between the BGA package and PCB can impose repeated mechanical loading on solder interconnects, especially near the outermost corner balls, where stress concentration and reliability degradation frequently occur. Therefore, for packaging-level reliability assessment, it is necessary to evaluate not only global warpage but also local deformation transfer among the BGA package, solder interconnects, and PCB. DIC (digital image correlation) is a non-contact and non-destructive technique that can visualize and quantify full-field strain mapping [1]. However, Micro-DIC in semiconductor packages faces challenges such as limited field of view, defocus sensitivity, illumination nonuniformity, and image registration errors.
In this study, a Micro-DIC methodology combining image post-processing and image stitching is proposed for thermomechanical deformation analysis of fine-pitch BGA package assemblies [2]. Reliable Micro-DIC requires optical images that preserve stable surface information during deformation [3,4]. However, high-magnification microscope imaging often suffers from vignetting, where image intensity decreases toward the outer region due to lens and illumination conditions. This nonuniform brightness reduces image contrast and degrades DIC correlation quality [5]. To address this issue, a vignetting correction procedure was applied to improve intensity uniformity while preserving pattern information across sequential thermal images. In addition, image stitching was used to construct wide-field panoramic images from multiple high-magnification images, enabling full-field Micro-DIC analysis over the package cross section while maintaining microscale spatial resolution [6]. By combining high-magnification local DIC and stitched wide-field DIC, package deformation was analyzed from a multiscale perspective.
The proposed methodology was applied to BGA package structures under thermal loading. Cross-sectional 2D DIC results showed that the BGA package and PCB exhibited different bending levels under the same thermal condition, indicating that solder interconnects transfer and accommodate deformation mismatch between the two components. Local deformation variation was also observed near the outermost solder interconnects, where the package-edge constraint is partially released. These results suggest that corner solder ball vulnerability is not governed only by global warpage or package geometry, but is also affected by BGA–PCB bending mismatch and local stress concentration at solder interconnects. This study demonstrates that image-post-processing- and stitching-assisted Micro-DIC can provide a practical methodology for packaging-level thermomechanical deformation analysis, linking global warpage with local solder interconnect reliability in fine-pitch semiconductor packages.

Abstract:
As artificial intelligence (AI) applications continue to expand, the datacenter industry is driving increasing demand for higher-bandwidth high-speed interconnects. Consequently, PCIe-based interfaces in devices such as graphics processing units (GPUs), Smart Network Interface Cards (SmartNICs), and computational storage are transitioning from PCIe Gen5 to PCIe Gen6, enabled by the adoption of 4-level pulse amplitude modulation (PAM4) in place of conventional non-return-to-zero (NRZ) signaling. While PAM4 improves bandwidth efficiency, it also reduces the signal-to-noise ratio (SNR), making the channel more vulnerable to noise and signal impairment. Therefore, PCIe receiver marginality validation is critical to ensuring reliable PAM4 high-speed signal transmission with low bit error rate (BER). This paper presents the validation methodology and test results for PCIe Gen6 receiver marginality in the designed HSIO channels.
As shown in Figure1, PCIe Gen6-supported datacenter board with a two-connector HSIO channel topology was used for electrical validation (EV) characterization. In the setup shown in Figure2(a), a bit error ratio tester (BERT) was connected as the link partner to the CPU root port of the HSIO channel through a CEM test fixture as the link partner and evaluate the first-bit-error rate (FBER) of the CPU receiver under the worst-case channel loss condition. In the configuration shown in Figure2(b), the same datacenter board was connected to a PCIe Gen6 end device, and the Gen6 FBER data of the CPU receiver were collected using the Intel® IO Margin Tool (IOMT).
As illustrated in Figure3, Gen6 FBER data was collected from the HSIO channels of four boards with estimated return loss ranging from 11dB to 19dB, excluding the losses contributed by the end device and CPU. The Gen6 FBER results measured using the Intel® IOMT showed a clear correlation, with FBER increasing as channel return loss increases. A similar trend was observed in the measurements obtained using the VendorA and VendorB BERTs. As indicated by the red box in Figure3, the link failed to enumerate on DUT4 when tested with the VendorA BERT, resulting in test failure due to high FBER. Furthermore, DUT8, which exhibited the highest return loss of 19dB, showed an FBER greater than 1e-6 in both VendorA and VendorB BERT measurements. To further extend the channel loss, DUT8 was paired with a PCIe Length/Loss Extender Card (PLEC) and a Gen6 device, increasing the total channel loss from 19dB to 30dB. As shown in Figure4, the Gen6 FBER increased substantially with increasing channel return loss, demonstrating a strong correlation between higher channel loss and degraded receiver margin.
In summary, Gen6 FBER substantially increased as the return loss of HSIO channel increased which reflected the high-speed signal quality degradation in a lossy channel. Designer could assess the quality of the HSIO signal transmission based on the Gen6 FBER test result of the CPU receiver. Future optimization of the loss of the HSIO channel could be done by material selection and board signal layout to reduce the total loss and improve the HSIO signal quality.

Abstract:
To improve edge termination in high power MOSFETs, guard rings (GRs) are widely used. Their performance depends on parameters such as ring number, width (w), spacing (s), depth, and doping concentration. Conventional optimization is simulation intensive, whereas machine learning (ML) enables faster and more efficient GR design optimization with reduced computational cost.
In this study, TCAD was utilized to design and simulate a 6.5kV GR structure. Fig. 1. illustrates the schematic of the GR structure used in this work, and the specific structural parameters are outlined in Table I. For data collection, each combination of s-w, simulations were performed by varying the # of GRs. For each GR, the ion-implantation dose concentration is varied, and each dose is implanted sequentially using three sets of energies, respectively, as illustrated in Table II.
For dataset preparation, the baseline device parameters (Table I) were fixed while key process and structural parameters were varied (Table II). The ion-implantation dose ranged from 5×1012 to 1×1014 cm-2, with three implantation energies (300, 600, and 900keV) selected to match baseline implantation depth while reducing the simulation time. The number of GRs (20-30), along with their width and spacing, was also varied. Breakdown voltage (BV) was evaluated in TCAD using anisotropic impact ionization, incomplete dopant ionization, high field mobility saturation, hole-quasi-Fermi potential, and a coupled Poisson-current continuity solver to ensure accurate device modeling.
RL follows an agent-environment interaction where the agent takes action at in state st, receives a reward rt, and transitions to new state st+1, refining its policy π to maximize cumulative rewards. The state space S = [epi, nDrift, s, w, # GR, D, En1, En2, En3] includes input parameters varying within predefined ranges. Actions involves randomly selecting any state space parameters leading to state transitions that optimize π and impact breakdown voltage (BV). The agent has trained using an improved reward system with non-linear penalty to ensure correct dose selection. The reward function incentivizes higher BV while penalizing suboptimal dose values, ensuring efficient learning and parameter optimization.
The Actor-Critic (AC) agent was evaluated for threshold voltage prediction using the network configuration comprising a three-layer actor betwork (64-64-32 neurons) and a two layer critic network (32-32 neurons) with tanh ans swish activation functions. The agent was trained using the adam optimizer with a learning rate of 1×10-4, batch size of 64, discount factor of 0.99, update frequency of 10, and entropy regularization of 0.001. Initially, a straightforward penalty function incorporated into the reward to discourage unrealistic process parameter selections while maximizing the performance. Fig. 2. Compares the learning behavior of AC agent using different penalty functions.
To guide the agent toward optimal dose selection, a reward penalty based on the deviation of the selected dose from the median of the predefined dose range was introduced. A linear penalty failed to improve learning, replacing it with a non-linear penalty significantly enhanced the training performance, emphasizing the importance of effective reward design as shown in Fig. 2. The RL agent reward using a batch size of 64 increased and eventually converged, while the moving average confirmed the stable learning throughout the training process.
Table IV highlights the results of trained AC agent. For linear or straightforward penalty, the agent maintained a fixed reward while tried few exploration during the training process. Then, for effective learning, non-linear penalty was introduced by increasing the effective value of the reward. This made the learning of the objective very effective, shown in Fig. 2(c), and the predicted input values when simulated using the TCAD resulted in a BV of 7.5kV.

Abstract:
The rapid growth of high-performance electronic systems is driving printed circuit board assemblies (PCBAs) toward larger board sizes, higher layer counts, denser component placement, and more stringent thermo-mechanical reliability requirements. Under this trend, PCBA warpage prediction becomes increasingly important for assembly yield, solder joint reliability, heat-spreader attachment, and system-level structural integrity. Finite element modeling remains the mainstream approach for warpage simulation because it can handle complex geometry, anisotropic materials, process history, and solder viscoplasticity. However, the conventional characterization-and-modeling route faces a growing bottleneck: commercial package components are usually black-box, heterogeneous, and difficult to characterize material-by-material. For large PCBAs containing many component types, repeated sectioning, material testing, structural reconstruction, and detailed meshing become too expensive and time-consuming to support rapid design iteration.
This work explores a response-based alternative for component characterization and modeling. Instead of identifying every internal material and geometry feature of a black-box component, the proposed concept characterizes the component by its measurable thermo-mechanical effect on a known reference PCB. The central idea is to convert a high-dimensional detailed component structure into a low-dimensional equivalent model whose parameters are identified by matching the board-level warpage response. Such a route has the potential to reduce dependence on destructive characterization, protect component-level intellectual property, simplify finite element model construction, and enable scalable warpage-aware design for component-dense PCBAs.
A BGA-PCBA test vehicle is used to evaluate the feasibility of this concept. The sample consists of a 60 mm × 60 mm × 1.2 mm FR4 PCB, a 40 mm × 40 mm BGA component, and a 39 × 39 SAC305 solder-ball array. Shadow moiré measurement is conducted to obtain the temperature-dependent warpage response. A detailed finite element model is then constructed in Abaqus, including reflow history, solder activation, anisotropic board/package materials, and Anand viscoplastic solder behavior. The detailed model reproduces the dominant component-induced warpage mode and serves as a controllable reference for equivalent-model development.
The BGA component is further simplified into a three-layer equivalent model representing the solder-equivalent layer, substrate-equivalent layer, and die/cover-equivalent layer. Fourteen effective thermo-mechanical parameters are considered. To accelerate inverse parameter identification, 1000 equivalent-model simulations are generated by Latin hypercube sampling, and a radial basis function surrogate with automatic relevance determination is trained using 800 samples, with 200 samples used for testing. Bayesian optimization is then applied to identify parameter sets that match the detailed-model warpage response.
The identified equivalent model reproduces the dominant reference-board warpage effect while reducing the model size from 480,880 elements to 25,200 elements and decreasing the single-run simulation time from over 2 hours to within 7 minutes. The surrogate-assisted inverse search further reveals that die/cover-equivalent CTE, substrate thickness, solder-equivalent thickness, and die/cover thickness dominate the matched response. Meanwhile, multiple near-optimal parameter sets and limited cross-PCB transferability indicate that single-board, single-point matching is insufficient for unique and transferable equivalent characterization. These findings demonstrate the promise of response-based equivalent modeling for fast PCBA warpage simulation and also identify the next challenge: incorporating richer full-field responses and multiple reference-board conditions to achieve robust, transferable black-box component models.

Abstract:
Low-temperature Cu sinter bonding is attractive for high-reliability power electronics packaging, but Cu nanoparticle paste performance depends not only on particle size but also on surface state, organic removal behaviour and interparticle connectivity. In one-step bimodal CuNP systems, additive concentration can affect both particle formation and subsequent sintering; however, the link between synthesis regulation and bonding strength is not yet fully clear. This work addresses how a coordination-type organic additive defines a practical processing window for bimodal CuNP pastes under mild nitrogen sintering.
Bimodal CuNPs were prepared by a one-step chemical reduction route. Cu-Cu joints were fabricated by pressure-assisted sintering at approximately 200 °C in nitrogen. Particle morphology and size distribution were evaluated by SEM/TEM, while surface/crystalline states and thermal behaviour were examined by complementary structural and thermal analyses. Bonding performance was assessed using shear testing, fracture-surface observation and cross-sectional SEM. Additive levels are grouped as low, intermediate and high regions to emphasize the process-window trend.
Bonding strength showed a non-monotonic dependence on additive level and paste solid loading. Low or unbalanced additive conditions resulted in heterogeneous densification and connectivity-limited joints. In contrast, an intermediate additive window generated a balanced bimodal particle population and a more continuous interparticle network. Under 200 °C-class nitrogen sintering, the optimized paste achieved a shear strength above 90 MPa and retained approximately 40 MPa under reduced pressure. Cross-sectional observations indicated pressure-dependent densification, while fracture surfaces suggested spatially uniform plastic deformation. Excess additive did not further improve bonding and may partially suppress direct particle-particle contact through increased surface-associated species.

Abstract:

AI infrastructure is evolving from accelerator-level optimization toward scalable AIfactory deployment. Peak silicon performance alone is no longer sufficient; deployment depends on the integration of silicon, advanced packaging, substrates, boards, racks, liquid cooling, power delivery, software, and regional infrastructure. This talk presents a five-year roadmap centered on the validated envelope—a multidomain operating range in which chip-to-facility systems can be manufactured, powered, cooled, monitored, serviced, and replicated at scale. It will address key technology drivers, including chiplets, HBM, optical I/O, power delivery, liquid cooling, mechanical reliability, and fleet telemetry, while proposing validation milestones for silicon suppliers, hyperscalers, foundries, packaging ecosystems, and infrastructure providers. The goal is to enable a “validate once, replicate many times” approach to scalable AI infrastructure.

Abstract:

This presentation discusses the thermal and energy efficiency challenges of next-generation AI infrastructure, including rack-scale AI systems, heterogeneous CPU-GPU architectures, memory hierarchy optimization, and cooling considerations for Agentic AI workloads. The session will explore system-level approaches to improve performance per watt while addressing increasing power density in modern AI datacenters.

Abstract:

Rapidly increasing power density is changing the scale of thermal management—from high-power chips to high-density racks. This talk explores how thermal, flow, and energy considerations must be co-optimized as liquid cooling evolves from a component-level heat removal technique to a system-level thermal architecture.

Abstract:

As rack power densities surge beyond 100 kilowatts (kW), achieving 100% heat capture becomes increasingly essential for thermal management and operational efficiency. Current coldplate designs focus on high-thermal design power components such as CPUs and GPUs, but future architectures demand complete heat removal across all components. Even at 90% heat capture, a 500kW rack leaves 50kW for air cooling, which is a stretch for even the best air-cooled implementations. Enabling 100% heat capture will be critical for supporting next-generation AI infrastructure. Join us to learn how integrated cooling loops and advanced coldplate technologies enable complete heat removal across the entire server.

Abstract:

Advanced packaging is becoming a key enabler of next-generation semiconductor systems, complementing advances in silicon scaling and supporting the growing demands of AI, high-performance computing, and heterogeneous integration. As system complexity increases, innovations in packaging architectures, interconnects, substrate technologies, and materials are playing an increasingly important role in delivering performance, power efficiency, and scalability.

This presentation will explore key trends shaping the advanced packaging landscape, including chiplet-based architectures, advanced memory integration, larger package formats, higher interconnect densities, and the evolution of package substrates to meet future system requirements. It will also discuss the importance of ecosystem collaboration in enabling the next generation of semiconductor innovation.

Abstract:

Scaling AI workloads demands unprecedented bandwidth and power delivery, shifting high-performance computing from monolithic to heterogeneously integrated packaging architectures. This presentation examines how glass core substrates enable ultra-large form factor packaging, while assessing ecosystem readiness and manufacturing pathways to address critical transition challenges.

Abstract:

Failure of a brittle material like glass is caused by a combination of surface damage in combination with tensile stress components. In glasses with excellent surface qualities detection methods of the remaining tiny surface defects fail and one has to rely on statistical failure analysis e.g. with ring-on-ring tests which lead to Weibull statistics for the failure probability [1]. In a real device the stresses are in most cases caused by the mismatch of thermal expansion [2].

Glasses show in most cases a very linear thermal expansion, which does not change over a wide temperature range. Other material classes involved in packaging like silicon single crystals, copper metal and polymer materials show a significant variation of its thermal expansion with temperature. In the present work we report strength measurements and review the temperature dependent thermal expansion of materials involved in advanced packaging and compare it to the data reported in data sheets.

Abstract:

Glass core substrates are emerging as a key technology for next-generation AI and high-performance computing packages, offering advantages in electrical performance, dimensional stability, and interconnect scaling. However, achieving high-volume manufacturing requires overcoming challenges in through-glass via (TGV) integration, fine-line redistribution layer (RDL) patterning, defect control, and yield management.

This presentation discusses critical process control challenges and highlights how advanced inspection, metrology, and lithography solutions enable process optimization and yield improvement throughout the glass packaging workflow. These capabilities are essential for accelerating the industry's transition from glass substrate development to volume production.

Abstract:

The rapid growth of artificial intelligence (AI), high-performance computing (HPC), and advanced networking applications is driving unprecedented demand for semiconductor packages with higher interconnect density, improved signal integrity, and enhanced dimensional stability. As traditional organic substrates approach their technical limits, glass substrates have emerged as a promising platform for next-generation advanced packaging due to their superior dimensional stability, low coefficient of thermal expansion (CTE), smooth surface morphology, and excellent electrical performance. These advantages enable ultra-high-density interconnect architectures with finer line and space (L/S) dimensions required for future package designs.

While glass provides compelling performance benefits, its adoption introduces significant manufacturing challenges. The chemically inert and exceptionally smooth surface of glass makes metallization and adhesion difficult, requiring innovative approaches to establish robust interfaces between glass and copper conductors. Furthermore, as feature dimensions continue to shrink, process tolerances become increasingly narrow, making line width reduction, surface roughness control, and pattern integrity critical factors affecting both electrical performance and manufacturing yield.

To address these requirements, next-generation wet chemical processes have been developed to deliver enhanced interface reliability, improved surface control, and optimized metallization performance. These solutions enable ultra-fine circuitry, support advanced through-glass via (TGV) architectures, and provide a scalable manufacturing pathway suitable for panel-level, high-volume production. Compared with alternative dry-processing approaches, wet chemical technologies offer significant advantages in throughput, process scalability, and cost efficiency.

This talk reviews the critical role of advanced wet chemical technologies in enabling glass substrate adoption for future semiconductor packaging. Key challenges associated with adhesion, metallization, fine-line formation, and long-term reliability are discussed, along with recent developments in chemical process solutions designed to meet the demanding requirements of next-generation AI and HPC packaging platforms.

Abstract:

The rapid expansion of large language models and agentic AI is driving rapidly increasing demand for scalable computing infrastructure. As accelerator clusters grow to support training and inference, data movement, bandwidth density, power delivery, thermal management, and energy efficiency are becoming critical constraints in next-generation AI platform design.

This talk will examine how chiplet architectures, 3.5D packaging, and panel-scale integration can address these challenges. Although wafer-scale approaches have advanced significantly, their economics become increasingly difficult as AI accelerator modules expand beyond nine reticle fields. At these dimensions, wafer utilization declines sharply, the number of modules produced per wafer can fall into the single digits, and both cost and manufacturing capacity become significant concerns. Panel-scale platforms offer an alternative path by supporting larger integration areas, improved utilization, and scalable manufacturing for highly integrated AI systems.

The talk will conclude with a call for coordinated industry action. Standardized equipment, materials, process flows, design rules, and automated manufacturing systems will be essential for panel-scale technologies to achieve reliable, cost-effective high-volume production.

Abstract:

AI compute is no longer scaled by the transistor alone. As accelerator designs push past reticle limits and integrate ever-larger arrays of logic chiplets, high-bandwidth memory stacks, and increasingly co-packaged optics, the package itself has become the performance-defining element of the system. Interposer and substrate area is growing faster than wafer-based integration can economically absorb, and the industry's response is a shift in the fundamental unit of manufacturing: from the 300mm wafer to the large-format panel. Applied Materials is uniquely positioned to enable that transition through a broad panel packaging portfolio spanning lithography, thin film deposition and metrology. In this talk, we will share how Applied is leveraging its panel portfolio, and external partnership to drive core enablement, build-up, and interconnect scaling.

Abstract:

As AI/HPC chips grow in size and complexity, traditional packaging is struggling to keep pace. Innolux is uniquely positioned to bridge this gap by leveraging our profound expertise in TFT-LCD manufacturing to deliver two game-changing solutions: Fan-Out Panel-Level Packaging (FOPLP) and Through-Glass Via (TGV) technology.

Our FOPLP platform represents a strategic transformation, repurposing our existing large-format panel infrastructure and technical know-how into a high-efficiency semiconductor packaging solutions. This transition not only significantly optimizes capital expenditure (CapEx) but also empowers our highly skilled workforce to leverage into advanced semiconductor packaging. Beyond the operational efficiency, our FOPLP flow integrates glass carriers to effectively eliminate warpage—a major issue for large-chip yields—while drastically simplifying handling for complex, large-scale dies and thin interposer.

Complementing this, TGV is emerging as the gold standard for high-end AI packages. Beyond solving assembly-level warpage, TGV’s superior electrical properties offer a massive boost to Signal Integrity (SI). As chip architects face the physical limits of signal transmission, the stability and low-loss performance of glass make TGV the preferred choice for next-generation designs. By combining repurposed manufacturing excellence with high-performance glass-based solutions, Innolux is setting a new benchmark for reliable, scalable, and high-performance AI/HPC packaging.

Abstract:

• AMC overview
• Warpage control solution
• Application

Abstract:

A fundamental and mechanistic understanding on the Cu-Cu direct bonding for hybrid-bonding technology. Particularly the role of native copper oxide on Cu substrates towarding bond formation, the thermodynamic stability of copper oxides, and the kinetics of copper oxide evolutions.

Abstract:
1. INTRODUCTION
The importance of 3D heterogeneous integration has increased significantly as it enables system-level scaling alongside transistor scaling to improve density and performance. Unlike the traditional flip-chip methods that rely on bulky solder bumps, hybrid bonding achieves perfectly planar surface leading to a drastic reduction in interconnect pitch and overall package height. Flip-chip based interconnect technologies are approaching their scaling limitation at approximately 10µm pitch. To support further pitch scaling, hybrid bonding interconnect (HBI) has emerged as a next-generation interconnect technology. HBI offers several advantages, including lower energy per bit and ultra-high interconnect density to increase bandwidth. Face-to-face sub-10 µm pitch hybrid bonding is a key enabling technology for advanced 3D integration with strong potential for future high-volume manufacturing.

2. METHODOLOGY
The test vehicle used in this study measured 10 × 10 × 0.05 mm and consisted of 5 µm Cu bonding pads with a 10 µm pitch configuration. The passivation layers on the chip surfaces were composed of inorganic dielectric materials. A circular Cu pad design was implemented to evaluate placement accuracy challenges associated with fine-pitch chip-to-wafer (C2W) hybrid bonding. To achieve the target placement precision of <2 µm required for a 12-chip stacked module, vision-based alignment, placement offset compensation, and alignment mark calibration were employed to ensure accurate Cu pad registration. The optimized pick-and-place methodology minimized cumulative alignment errors across multiple bonding interfaces. Prior to bonding, sequential surface activation processes were performed to achieve clean and contamination-free bonding interfaces. A design-of-experiment (DOE) study was conducted to evaluate plasma activation power ranging from 200 W to 300 W and post-bond annealing temperatures ranging from 180°C to 300°C. Plasma activation parameters and DI water rinsing conditions were systematically varied to investigate their effects on surface integrity, oxide activation, and overall bonding performance. Contact angle measurements were conducted before and after surface activation to evaluate changes in surface wettability and morphology. To facilitate chip tacking, a bonding tool with a soft rubber tip was utilized to initiate bonding at the chip center, promoting effective bond propagation across the die area. Daisy chain measurements were conducted to evaluate electrical connectivity and interconnect continuity across the stacked chip structures.

3. RESULTS
The study demonstrated that achieving placement precision below 2 µm is essential for successful sub-10 µm pitch chip-to-wafer hybrid bonding with a symmetric pad design. Daisy-chain electrical characterization across 15 locations confirmed robust electrical connectivity in the multi-chip stacked modules. Results revealed a correlation between overlay error and contact resistance, where misalignment decreases the effective contact area between bonded pads. Measured contact resistance values closely matched theoretical predictions, with deviations under 5%. Overall, the findings emphasize that optimized plasma activation, DI water rinsing, overlay accuracy, and bonding tool design are critical for reliable chip stacking and high-quality hybrid bonding interfaces. These process optimizations are vital to enable robust sub-10 µm pitch hybrid bonding and advance 3D integration technologies.

4. NOVELTY and IMPACT
This work advances fine-pitch chip-to-wafer hybrid bonding by demonstrating <2 µm placement accuracy for a symmetric 10 µm-pitch interconnect architecture capable of supporting 12-chip vertical stacking. The study establishes critical process windows for plasma activation, DI water rinsing, and bond initiation control, resulting in an integrated bonding methodology that achieves robust electrical continuity and enables scalable sub-10 µm interconnect integration for high-bandwidth 3D heterogeneous systems. The findings demonstrate the feasibility of reliable sub-10 µm pitch hybrid bonding and provide a strong foundation for its future adoption in high-volume manufacturing environments.

Abstract:
The rapid expansion of generative artificial intelligence (AI) has significantly increased computational demand, thereby intensifying the requirement for energy-efficient data center operation. High Bandwidth Memory (HBM) is regarded as a key device to address this challenge by enabling high-speed data transfer with reduced power consumption. Hybrid bonding, in which copper (Cu) and inorganic dielectrics (e.g., SiO₂, SiN, SiCN, SiON etc.) are directly bonded without the use of solder or adhesives, has attracted considerable attention as a next-generation interconnection technology. This approach enables finer pitch interconnects and higher integration density compared with conventional solder-based methods and is expected to be applied not only in HBM but also in a wide range of advanced semiconductor devices.
However, the integration of hybrid bonding in stacked Cu/inorganic dielectric structures introduces several technical challenges. These include (1) micro-strain induced by thermal history in multi-layered structures, (2) the requirement for precise control of Cu recess depth to ensure stable bonding interfaces, and (3) high sensitivity of bonding surfaces to particle contamination, which adversely affects bonding yield and reliability.
To address these challenges and extend the applicability of hybrid bonding, the use of Bump Support Film (BSF), a film-based embedding dielectric, is investigated. BSF was originally developed for chip scale packaging to protect metal bumps from thermal and mechanical stress. Unlike coating materials, BSF is implemented as a laminated film, providing structural stability and process uniformity. The film consists of a base film with a bump-absorption layer and a suitable-viscosity thermosetting layer that facilitates bump embedding and void reduction during processing. Lamination and thermal curing are performed at 90 °C and 160 °C, respectively.
To evaluate the applicability of BSF to hybrid bonding, Cu bump wafers with a diameter of 2.5 µm, a pitch of 5 µm, and a height of 3 µm were fabricated. Two types of investigations were conducted.
The first focused on material optimization through modification of the binder composition by increasing its glass transition temperature (Tg) from < 70 °C to > 100 °C, in order to suppress surface and bulk haze caused by microphase separation during thermal curing. The second focused on process integration, including BSF lamination on Cu bump dies, thermal curing, Chemical Mechanical Planarization (CMP), surface activation, and hybrid bonding.
Thermal curing behavior at 160 °C revealed that the conventional BSF (binder Tg <70 °C) exhibited localized whitening after 13 min, which expanded across the entire observed area by 30 min. In contrast, the modified BSF (binder Tg >100 °C) showed no observable degradation under identical conditions. Atomic Force Microscopy (AFM) analysis indicated a significant improvement in surface roughness, with an Image Ra value of 3.5 nm for the modified BSF compared with 18.8 nm for the conventional BSF. Shear strength between the modified BSF laminated dies after surface modification. The results showed sufficient value, confirming that the adhesive properties are suitable for practical applications.
Following lamination and curing, residual BSF on Cu bumps was removed via CMP. AFM analysis confirmed that Cu protruded approximately tens of nm above the BSF surface after CMP. Energy dispersive X-ray spectroscopy (EDS) analysis verified the complete removal of BSF residues from Cu surfaces, indicating suitability for subsequent hybrid bonding.
Hybrid bonding of surface-activated Cu/BSF dies was successfully achieved, and cross-sectional scanning electron microscopy observations confirmed bonding of both Cu and BSF layers.
The modified BSF demonstrated improved surface morphology, bonding performance, and process compatibility in hybrid bonding structures. These results suggest that BSF is a promising approach for expanding the applicability of hybrid bonding beyond advanced semiconductor technologies. Future work will involve wafer-level validation and reliability tests.

Abstract:
ABSTRACT
Chip to wafer hybrid bonding combines metal to metal interconnects and dielectric to dielectric bonding in a single step with fine pitch interconnects and higher electrical performance when compared to conventional solder-based packaging technologies. Chip to wafer hybrid bonding (C2W-HB) including multi-chip stacking, is very crucial technology in enabling high performance, and high-density systems for next generation applications such as high bandwidth memory (HBM), artificial intelligence (AI) and advanced computing which requires high data transfer rates and compact form factors. Multichip stacking using C2W-HB, can be achieved by either double sided fabrication (DSF) scheme or inter die gap filling (IDGF) approach. In DSF approach chips are fabricated with bond pads on both sides of the chip before hybrid bonding process, whereas in IDGF process dies are fabricated with bond pads on front side only, and followed by hybrid bodning and inter die gap filling using thick oxide. Among these approaches, C2W-HB stacking using IDGF approach is relatively newer approach, as it requires new integration schemes and process modules when compared to DSF approach. Present study focuses on C2W-HB stacking development using IDGF approach as it overcome the thin chip handling issues during bonding and to maximize the number of chip stacking by reducing final chip thickness when compared to DSF process.

METHODOLOGY
For C2W-HB multi-chip stacking using IDGF approach, this work presents and comparatively analyses two different process integration methodologies based on the sequence of thinning/planarization with respect to inter die gap filling using thick dielectric. The proposed process integration methodologies are as 1) Methodology-1: Thinning and planarization after oxide filling, 2) Methodology-2: Thinning and planarization before and after oxide filling, as shown in Fig 1. Both process integration schemes are relatively newer, non-standard when compared to standard damascene fabrication flows used for back end of the line (BEOL) processes. Hence it requires new modules, materials and metrology methods to be established, but at the same time all these processes and materials should be compatible with standard fabrication protocols. In view of this, present study extensively evaluated and optimized the back grinding and chemical mechanical planarization modules and related materials thoroughly evaluated and optimized for the proposed methodologies. Current development covered optimization tool hardware, proper selection of grinding wheels, polishing pads, polishing slurries and post back grinding and cleaning chemistry. In case of BG grinding wheels, different grit design types are evaluated, whereas for polishing, pads with different hardness types are evaluated. For grinding and polishing slurries, specially formulated slurries have been employed by keeping final objective of minimal edge rounding of silicon die and reasonable selectivity for both silicon and oxide dielectric material. Both flows have their own pros and cons, and need careful selection based on the integration flow availability and target specifications.
RESULTS, NOVELTY AND IMPACT
For both methodologies 1&2, excellent C2W hybrid bonding quality is very critical, as C2W-HB wafers with and without fill are processed through extensive thinning and planarization loads. Empirically it has been observed that any bonding voids in the chips around 5% will cause significant delamination and/or cracking during thinning and polishing, as shown in Fig 2. Bonding void location also plays critical role, and it is more detrimental when the void is present at edge of the chip when compared to inside of the chip. Hence thorough screening of the C2W-HB wafers is necessary to use any bodning voids detection prior to proceeding any further integration processes and it is very critical for methodology-2, as chip thinning occurs before oxide filling. Based on our extensive DOE runs it has been identified that for thinning and planarization, both back grinding and CMP processes are required. Bulk silicon and oxide will happen in back grinding process, and final polishing will happen in CMP process step. Several critical issues such as die thickness variation, edge erosion, oxide-silicon chip topography and contaminations in the trench between dies have been successfully resolved. All these process issues/challenges and their mitigation plans have been summarized in Fig.3, based on the proposed methodologies and obtained results are within the acceptable range for damascene fabrication and subsequent chip stacking.

Abstract:
Fine-pitch solder ball technology has become increasingly prevalent in recent years. In advanced packaging, the trend toward denser and finer-pitch solder balls can induce specific product failures. For instance, in High Bandwidth Package on Package (HBPoP) structures, encapsulating the die and the solder balls—which connect the interposer and substrate—within an epoxy molding compound (EMC) induces a significant risk of solder ball cracking during the molding process. Therefore, this study aims to establish a comprehensive simulation flow to observe the fluid-induced stress on these solder balls. Solder ball stress is evaluated and improved through structural optimization, specifically examining interposer, solder mask opening and ball array. The results indicate structural optimization enhances solder ball stress performance certainly.

This paper utilizes fluid-structure interaction (FSI) technology within computational fluid dynamics (CFD) software to compute the entire progression from EMC fluid flow to solder ball structure stress behavior. This methodology couples the fluid and solid governing equations to comprehensively model the complex, non-Newtonian behavior of the EMC within a computational procedure. It’s effective to evaluate solder ball stress performance induced by fluid.

By accounting for molding process conditions (such as temperature) and EMC material properties (including viscosity and cure kinetics), the model fully evaluates the fluid-induced solder ball stress through both fluid dynamics and solid mechanics, including physical flow and chemical reactions.

Using this established FSI simulation flow, structural optimization is investigated, with a focus on interposer thickness, SM opening width, and ball array configuration.

Simulation results indicate that the maximum fluid-induced stress concentrates at first row of solder balls. The results also reveals that interposer, solder mask opening and ball array pattern significantly influenced the solder ball stress performance. Specifically, thicker interposers possess sufficient structural strength to reduce fluid-induced solder ball stress; while wider S/M opening help mitigate maximum solder ball stress. Furthermore, the hollow-square type (口-type) and flip U-shaped type ball array patterns significantly reduce solder ball stress. Overall, the hollow-square type (口-type) ball array pattern effectively reduces the maximum stress value by dispersing the fluid impact force, regardless of whether the solder balls are located in the first or last row. Compared to the I-type ball array, the 口-type ball array pattern decreases the maximum stress value by 83%. Additionally, thicker interposer and wider S/M opening decrease the maximum stress value by 23% and 5%, respectively. To accommodate higher I/O density devices, implementing the口-type ball array is the optimal approach to mitigate solder ball crack risks and increase I/O density simultaneously.

Abstract:

Driven by booming generative and Agentic AI, global AI market scale is projected to surge tenfold by 2033, yet a critical structural bottleneck emerges: computing performance triples biennially while interconnect bandwidth only rises 1.4 times, rendering traditional copper electrical interconnection incompetent due to low bandwidth, severe signal attenuation and excessive power consumption. The industry thus enters a “fiber replaces copper” transition, evolving through four optical interconnection schemes: pluggable optics, LPO, transitional NPO, and ultimate CPO. By co-packaging switch ASIC and optical engines (PIC & EIC) on shared substrates, CPO shortens electrical traces to millimeter scale, slashing power consumption by over 30% and delivering unmatched bandwidth density and ultra-low latency. Its packaging technologies advance from 2D/2.5D heterogeneous integration to high-end 3D hybrid bonding targeting monolithic EPIC fusion. Covering upstream optical materials, midstream silicon photonics and advanced packaging, and downstream AI supercomputing, cloud data centers and HPC clusters, CPO will see accelerated mass production from late 2026. From an investment perspective, primary and secondary market institutions have fully deployed the whole industrial chain, as CPO fundamentally reconstructs AI network node hardware architecture and underpins upper-layer AI tracks such as world models, presenting long-term trillion-dollar industrial and investment value

Abstract:
Evaluating the deformation behavior of semiconductor chips and molded resin packages during assembly processes and device operation is essential for optimizing packaging structures and improving overall reliability. Mechanical deformation induced by thermal or operational loading can lead to stress concentration, interconnect degradation, and long-term reliability issues. Therefore, obtaining experimental evidence of real deformation behavior is highly valuable not only for understanding packaging mechanics but also for advancing simulation models and verification methodologies. However, conventional measurement instruments—such as laser displacement sensors and general-purpose interferometers—are limited to point-wise or post-deformation measurements and cannot capture full-field deformation distributions in real time. This limitation has hindered the detailed understanding of transient deformation phenomena that occur during actual device operation.
To address this challenge, we developed a real-time full-field deformation measurement system based on laser speckle interferometry to observe the deformation behavior of chips and packages during assembly and device operation. Laser speckle interferometry offers high spatial and temporal resolution and enables non-contact measurement of displacement distributions on rough surfaces. When laser light illuminates a rough surface, the scattered light forms a speckle pattern consisting of bright and dark spots. By splitting a single laser beam using a half mirror, one beam is directed toward a reference surface while the other illuminates the measurement target. The reflected beams are then superimposed to generate a new speckle pattern. By comparing speckle patterns obtained before and after deformation, interference fringes are produced, from which displacement distributions can be extracted. The developed system consists of a He–Ne laser, a CMOS camera for capturing speckle patterns, a reference surface, and a piezo actuator that precisely controls the position of the reference surface.
Using this system, we conducted real-time measurements of the out-of-plane deformation of a molded resin package during the operation of a USB memory device. The deformation of both the memory package and the controller package was measured while several hundred megabytes of data were written to the device. During the writing process, the surface temperature of the package increased to approximately 50–60 °C, causing measurable out-of-plane deformation. These results demonstrate the applicability and effectiveness of the proposed measurement method for capturing dynamic deformation phenomena that cannot be observed using conventional instruments.
In addition, we introduce an application of the proposed system for measuring the out-of-plane deformation of chips under conditions that simulate the flip-chip assembly process. As chips continue to become thinner, deformation during flip-chip bonding has become a growing concern, as it may lead to mechanical and electrical reliability issues. Therefore, measuring and evaluating chip deformation during the flip-chip assembly process is of significant importance. Real-time deformation monitoring during assembly has the potential to contribute to process optimization, improved bonding quality, and enhanced reliability assessment. Overall, the proposed laser speckle interferometry–based system provides a powerful and versatile tool for real-time, full-field deformation measurement, offering significant potential for advancing semiconductor packaging research.

Abstract:
As advanced packaging technologies continue to evolve, one of the most critical challenges lies in ensuring interfacial reliability. Cutting-edge architectures such as 2.5D integration, silicon bridge interposers, and 3D stacking inherently introduce numerous heterogeneous interfaces, which often act as mechanical weak points where delamination can initiate. Such delamination can lead to severe degradation or even catastrophic failure in package performance. Double Cantilever Beam (DCB) and Four-Point Bending (FPB) tests are widely employed to evaluate the adhesion energy of specific interfaces of interest. Various surface treatments and material engineering techniques have been developed to enhance interfacial fracture energy, and the effects of these approaches are typically verified through DCB and FPB testing. These tests are typically conducted under the assumption of a constant phase angle, valid only for homogeneous materials. For instance, the DCB configuration represents a pure Mode I (0°) condition, while the FPB configuration corresponds to approximately 43°. Accordingly, the measured adhesion energy reflects a fixed ratio of Mode I and Mode II fracture components. However, at nano-interfaces, even the extreme thinness of the film, along with elastic modulus and thickness mismatches in adjacent layers such as adhesion or epoxy layers, can significantly shift the actual phase angle during crack propagation. Moreover, variations in the phase angle can alter the most favorable crack kinking direction. When the interfacial adhesion energy is sufficiently high to suppress crack propagation along the interface, the crack may deflect or kink into one of the adjacent nanofilms. To accurately predict this behavior, the elastic properties and thicknesses of both the nanofilms and the surrounding adhesion layers must be considered. To address this issue, a two-step FEA simulation submodeling approach combined with a J-integral sweep method was employed. In conventional DCB and FPB configurations, the silicon beams typically have a thickness of approximately 775 µm, with specimen dimensions of 40 mm in length and 8 mm in width. However, the region of interest where crack propagation and phase angle variation occur exists at the nanometer scale. Therefore, a multiscale (mm–µm–nm) global model was constructed, incorporating locally refined meshes to accurately capture the nanofilm interfaces. In the first submodeling step, a local model around the crack tip was extracted from the global model to obtain the boundary displacements required for subsequent analysis. This was necessary to perform a J-integral sweep, in which a virtual crack was introduced at the interface and rotated over a range of directions from −75° to +75° in 15° increments. The J-integral was computed for each orientation to determine the direction that maximized the energy release rate, which was then identified as the predicted crack kinking direction. However, the nm-scale region directly imported from the global model was found to be too small to maintain stable meshing near the crack tip. To overcome this issue, a scaled-up submodel was constructed. The original submodel extracted from the global model had a characteristic length scale of 10^(-6) (in mm units), which led to severe mesh instability near the crack tip. In the refined submodel, the dimensional scale was adjusted to 10^0 by redefining the base unit from millimeters to nanometers, thereby achieving stable mesh quality while preserving geometric fidelity. The boundary conditions were then mapped from the original submodel by applying a scaling factor of 10^6. This scaling approach enabled virtual crack extension and J-integral sweep analyses to compute the maximum strain energy release rate, from which the crack kinking angle was determined. Using this framework, a comprehensive parametric study was conducted to identify the key factors influencing phase angle and crack kinking direction, particularly the effects of the elastic properties and thicknesses of the nanofilms and adhesion layers. Finally, a machine learning model was developed to establish a functional relationship that enables rapid prediction of phase angle variation and crack kinking direction. The trained model produces a master surface correlating these parameters with the elastic properties and thicknesses of the adhesion layer, allowing users to directly estimate interfacial fracture behavior from material design inputs. In conclusion, the proposed two-step submodeling framework offers a universal method for predicting interfacial crack kinking direction. Beyond DCB and FPB tests, this approach applies to systems with thin-film scale mismatches, providing engineers a practical tool to evaluate fracture mode mixity in interfacial reliability design.

Abstract:
In recent years, with the rapid advancement of artificial intelligence (AI) technology, the semiconductor testing and inspection industry is experiencing new growth opportunities. It is anticipated that by 2025, the demand for AI servers, high-performance computing (HPC), and application-specific integrated circuits (AI ASICs) will increase significantly, further driving the upgrade of probe card and packaging testing technologies. By utilizing the contact between the probes of the probe card and specific solder pads on the wafer, electrical characteristics of the circuits can be measured, allowing for the assessment of chip yield and the immediate detection of defective chips. In this study, numerical and experimental approaches were employed to analyze the probing mark formation on the aluminum (Al) pad of a silicon (Si) wafer. The test vehicle, a 6-inch Si wafer with PVD Al coating, is shown in Fig. 1(a). The thicknesses of the PVD Al coating and Si wafer are 1.4 μm and 10 μm, respectively, as illustrated in Fig. 1(b). Microchips with dimensions of 0.04 × 0.04 mm² were prepared from the Si wafer for subsequent single probing tests using a Wire-Type needle.

Fig. 1(a) 6-inch Si wafer with PVD Al coating; (b) Detailed dimensions of Si wafer and Al pad.

A finite element (FE) model was developed to simulate the contact phenomenon and mechanical response of a wire-type probe needle with a round radius (RR) tip and an Al pad, as illustrated in Figure 2. The mechanical properties of the wire needle and the Si die were assumed to exhibit linear elastic behavior, with Young’s modulus values of 270 GPa and 170 GPa, respectively. The Al pad was modeled as an elasto-plastic material to investigate the probing mark formation behavior, with its Young’s modulus and yield stress set to 70 GPa and 160 MPa, respectively.

Fig. 2 FEM modeling of vertical wire probe needle and Al pad/Si wafer structure.

The single probing test was performed using a customized fixture and an MTS Acumen electrodynamic test system. The test speed was set to 0.5 μm/s to apply an external overdrive (OD) displacement, simulating actual wafer probing conditions. Following the experiment, the surface profile of the aluminum pad under various probe stroke settings was observed. The resulting probe mark was measured using a Keyence VK-X3000 3D laser confocal microscope, as shown in Fig. 3.
A three-dimensional finite element method (FEM) simulation was performed using the commercial software Abaqus. Figure 4(a) illustrates the established simulation setup, where a spherical probe tip is positioned to indent the aluminum (Al) pad, simulating the actual contact boundary conditions during the test. Upon applying the specified external overdrive (OD) displacement, the resulting displacement distribution on the Al pad was obtained. As shown in the displacement magnitude contour in Figure 4(b), the maximum displacement is concentrated at the center of the contact zone, aligning with the spherical profile of the probe tip. Figure 5 presents a comparison of the probe mark width and depth between the experimental data and the FEM simulation results. The comparison reveals that the FEM simulation successfully captures the overall trend of the deformation, particularly the increase in depth b as the overdrive displacement escalates. Furthermore, the close agreement in depth at the higher overdrive (OD 200) demonstrates that the proposed FEM model serves as a reliable tool for predicting the mechanical response and pad damage during the wafer probing process.

Fig. 3 Measurement of Probe mark by laser confocal microscope Keyence 3D VK-X3000.

Fig. 4 FEM simulation setup (a) and the resulting displacement contour of the probe mark on the Al pad (b) under overdrive (OD) conditions

Fig. 5 Comparison of probe mark width a and depth b between (b) experimental data and (c) FEM simulation results, based on the definition shown in (a).

Abstract:
High-warpage packaging products present significant challenges during the singulation process because the initial deformation, local support condition, and stress-release path continuously evolve as cutting proceeds. As the package strip is progressively separated, the constraint condition becomes nonuniform, and bending stress may be redistributed to the remaining uncut regions. In practical manufacturing, an improper cutting sequence may induce local stress concentration, package displacement, unstable vacuum suction, and potential die fly-off. Therefore, this study investigates the effects of cutting sequence design and vacuum suction behavior on the stress distribution of high-warpage packaging products.
A finite element model was established to analyze the deformation and cutting-induced stress of a warped strip substrate. The model included the strip substrate, compound region, glass component, and rubber support, with material properties assigned according to the package structure. Three initial warpage heights, 3 mm, 4 mm, and 5 mm, were considered to represent different process conditions. The vacuum suction mechanism was simplified using the pressure difference between atmospheric pressure and the vacuum chamber pressure. This pressure difference generates a downward suction force on the substrate and changes the contact condition, deformation behavior, and stress distribution during cutting. The simulation results were then used to compare the maximum stress variation among different cutting paths.
Four cutting sequence methods were evaluated. Method 1 cuts from the outside toward the inside and was used as the reference case. Method 2 considers the vacuum chamber arrangement and avoids early damage to the central vacuum region. Method 3 starts from the two side-center regions to maintain a larger effective suction area during cutting. Method 4 begins from the maximum-stress region to release bending stress at an earlier stage. The results show that the cutting sequence has a strong influence on the maximum cutting stress. Under larger warpage conditions, Method 1 tends to generate higher stress concentration because the early cutting steps do not effectively release the bending stress. For the 5 mm warpage case, Method 1 produced the highest stress among the compared paths, whereas Method 4 substantially reduced the peak stress by cutting the high-stress region first. However, Method 4 may require a more complex cutting path and could reduce production efficiency. In comparison, Method 3 shows better overall potential because it lowers the maximum stress while maintaining a practical cutting path and a larger effective suction area.
The results indicate that cutting sequence design is a critical factor in the singulation of high-warpage packages. A proper cutting strategy can reduce local stress concentration, improve vacuum suction stability, and lower the risk of package displacement or die fly-off. Future work will incorporate residual stress effects, double-sided warpage models, and practical cutting sequence design rules for manufacturing applications.

Abstract:
This study explores how different glass interposer materials affect the reliability of solder joints in 2.5D semiconductor packaging, using finite element analysis (FEA) simulations carried out in Ansys. As the electronics industry pushes toward increasingly compact and high-performance designs, 2.5D packaging has emerged as a promising integration strategy, but the choice of interposer material plays an important role in how well solder joints hold up over time.
Four glass interposer materials were put to the test: borosilicate glass, fused silica glass, Gorilla glass, and ceramic glass. Each material expands and contracts at a different rate when heated or cooled a property known as the coefficient of thermal expansion (CTE) and this difference creates mechanical stress at the solder joint level. The simulations followed standard industry JEDEC thermal cycling conditions, sweeping between −40°C and +125°C, while tracking von Mises stress and equivalent plastic strain deformation in SAC305 (Sn-3.0Ag-0.5Cu) solder interconnects.
The results showed Borosilicate glass produced the highest plastic strain deformation at 0.067 µm, followed by fused silica glass at 0.041 µm, Gorilla glass at 0.025 µm, and ceramic glass at just 0.015 µm. At first glance, ceramic glass appears to be the winner, but appearances can be deceiving. Its low deformation is not a sign of good compatibility with the solder system; rather, it stems from the material's exceptional stiffness, which simply prevents it from bending. Underneath that rigidity lies a substantial CTE mismatch with both SAC305 solder and silicon, meaning that under real-world prolonged thermal cycling, ceramic glass is actually at greater risk of driving solder fatigue and cracking, a danger that the simulation alone cannot fully reveal without a dedicated fatigue life model.
Borosilicate glass, on the other hand, shows a CTE of 3.3 ppm/°C that sits very close to that of silicon at 2.8 ppm/°C making it a far more compatible and industrially practical choice for 2.5D interposer applications, despite its higher simulated strain values. This finding drives home a broader point: plastic strain magnitude alone is not a reliable indicator of real-world solder joint performance. Future work incorporating established fatigue life prediction approaches, such as the Darveaux energy-based model or the Coffin-Manson strain-based model, would give a much more complete picture of how each interposer material holds up across the full product lifetime.

Abstract:
BACKGROUND
As advanced packaging technologies continue to evolve toward high-density heterogeneous integration, chiplet-based architectures, and vertical interconnection, hybrid bonding has emerged as a key enabling technology for energy-efficient AI hardware and high-performance computing (HPC) systems. In these multi-layer structures, interfacial adhesion reliability is a critical concern; local delamination at sub-micron bonded interfaces can directly affect mechanical integrity, electrical continuity, and long-term package reliability. The double cantilever beam (DCB) test is the standard experimental method widely utilized to evaluate Mode-I interfacial fracture behavior. However, the high accuracy and reproducibility of the measured adhesion energy are strongly sensitive to the configuration of the loading tabs design and its associated experimental uncertainties.
OBJECTIVE
This study proposes a tolerance-aware, robust design methodology for DCB loading tabs to guarantee high-fidelity, Mode-I dominant fracture evaluation of hybrid-bonded interfaces. Conventional loading tab designs are typically established under idealized alignment and symmetric loading conditions. In practical laboratory testing, however, imperfections such as tab-positioning offsets, dimensional tolerances during tab fabrication, angular misalignments of the loading axis, and nonuniform bonding layers between the tab and specimen are inevitable. These physical variations can introduce unintended Mode-II (shear) and Mode-III (tearing) components into the interface. This mode contamination results in mixed-mode fracture conditions, including significant errors in the extracted apparent Mode-I fracture energy release rate (GI). Therefore, a robust design guideline is required to minimize mode mixity under realistic experiment variations.
METHODS
A systematic parametric finite element analysis (FEA) framework is established to evaluate the sensitivity of fracture-mode partitioning to key tab design parameters. The investigated geometric variables include tab thickness, tab length, bonding area, loading-hole position, and upper-lower tab structural symmetry. To capture realistic testing environments, quantified fabrication tolerances and assembly misalignments are intentionally introduced into the simulation models as structural perturbations. Mode-decomposed energy release rates (GI, GII, and GIII) are meticulously evaluated along the three-dimensional crack front using fracture mechanics node-splitting techniques. Through this extensive case study, design factors that are most vulnerable to mode contamination are isolated, and their allowable manufacturing tolerance thresholds are rigorously quantified.
RESULTS AND SIGNIFICANCE
The parametric simulation framework successfully yields a comprehensive, simulation-based design window for robust DCB loading tabs tailored for advanced packaging interfaces. The numerical results elucidate the exact mechanisms by which experimentally feasible variations in tab assembly alter the fracture-mode composition along the crack front. The analysis highlights critical design criteria that are missing from conventional standard recommendations, particularly when addressing thin hybrid-bonded layers characterized by sharp material property mismatches. By establishing a direct correlation between geometric optimization and experimental uncertainty, this work provides a practical foundation to suppress mode contamination and improve the repeatability of DCB-based interfacial characterization. The established guidelines offer an essential pre-experimental verification framework, contributing to the development of highly reliable fracture characterization standards for next-generation electronic packages.
ACKNOWLEDGEMENTS
This research was supported by the Ministry of Trade, Industry and Energy (MOTIE), Republic of Korea (RS-2024-00418263), and the Korea Institute for Advancement of Technology (KIAT) (RS-2023-KI002797)

Abstract:
Increasing power delivery requirements in AI and HPC processors drive demand for integrated Die Side Capacitors (DSCs) within CPU and GPU packages. Current DSC encapsulation approaches present limitations in standoff height reduction, resin bleed out (RBO) mitigation, and throughput scalability for advanced substrates including FCBGA 2.5/3.0 and CoWoS architectures.

This study demonstrates a UV-curable jetable adhesive system optimized for DSC underfill & encapsulation applications in high-density BGA configurations. The formulation addresses concurrent requirements for reduced package Z-height, RBO elimination, and volume manufacturing throughput. Adhesive rheology enables capillary underfilling through sub-100μm gap heights while maintaining dispensing precision via jet valve systems.

The UV-curable material achieves complete cure within <30 seconds at 365nm wavelength, enabling inline processing integration. Cured encapsulant thickness from <100 µm with controlled fillet geometry, minimizing package keep-out zones. Viscosity characteristics provide optimal flow balance between void-free underfill and controlled dispensing boundaries.
Mechanical properties post-cure include glass transition temperature of <-40 °C and stable low young´s modulus in two digits range to avoid any kind of tensions.

Reliability qualification includes JEDEC MSL1 preconditioning (85°C/85% RH, 168 hours), temperature cycling (-40°C to +125°C, 1000 cycles), and unbiased highly accelerated stress testing (130°C/85% RH, 96 hours). Reflow compatibility verified through 3x 260°C peak temperature exposure without delamination or cracking. Cross-sectional analysis confirms maintained adhesion and structural integrity across all test conditions.
Manufacturing implementation utilizes existing jet dispensing platforms with standard UV-cure systems.

The developed UV-curable underfill system enables DSC integration in space-constrained package architectures through controlled material deposition and rapid cure processing. Elimination of RBO combined with reliable high-temperature performance supports next-generation processor packaging requirements where thermal and electrical performance drive continued miniaturization trends.
Implementation across FCBGA and advanced CoWoS substrates demonstrates applicability to current and emerging package technologies requiring enhanced power delivery integration.

Abstract:
We demonstrate an ultrahigh-speed drilling technique for TGV fabrication using single-shot femtosecond Bessel pulses in GHz-burst mode. By optimizing key irradiation parameters such as the number of intra-pulses and pulse duration, we successfully produced crack-free through-holes with a diameter of approximately 1 µm in 1.1-mm-thick borosilicate glass. This corresponds to an ultrahigh aspect ratio of approximately 1000. In addition, the hole diameters at the entrance, middle, and exit were nearly identical, indicating taper-free structures and excellent uniformity.
The proposed method also achieves outstanding processing efficiency, with a fabrication speed exceeding 3,000 holes per second. Since each hole is formed within less than 1 ns, further improvements in throughput are expected by optimizing scanning strategies, potentially enabling processing speeds above 10,000 holes per second.
Furthermore, post-processing with NaOH-based chemical etching allows precise control of the hole diameter while maintaining structural integrity. This hybrid approach enhances flexibility in design and fabrication.

Abstract:
In this study, an exceptional combination of an ultimate tensile strength exceeding 400 MPa and a ductility surpassing 5% has been successfully achieved in nanotwinned copper-graphene (nt-Cu/Gr) foils. These free-standing foils were fabricated by leveraging a direct-current (DC) co-electrodeposition approach, which enabled the synchronous assembly of Gr nanosheets within a high-density nanotwin Cu matrix. The target electrolytic films were deposited onto a temporary titanium (Ti) substrate and subsequently peeled off to yield intact foils for tensile testing and microstructural analysis. In addition to the enhanced strength-ductility synergy, the co-deposited foils exhibited a remarkable electrical conductivity over 92% IACS. Microstructural investigations demonstrated that the dual-reinforcement configuration-comprising highly oriented coherent twin boundaries and well-dispersed Gr networks-interacted synergistically to impede dislocation slip and postpone localized necking during deformation. This design concept opens a new avenue for engineering highly reliable, high-performance conductors required in advanced microelectronic packaging.

Abstract:
INTRODUCTION
Recently, printed electronics technology has been expanded to enable the production of three-dimensional (3D) electronic circuits in addition to two-dimensional (2D) ones. Among these, in-mold electronics (IME) have received significant attention as a promising approach for creating large-area, 3D electronic systems, especially for practical applications such as automotive interiors and medical devices. IME involves printing 2D electronic circuits with stretchable conductive pastes onto thermoplastic resin films, then thermally forming them into 3D structures.
Despite its potential, IME faces critical challenges as a packaging method for advanced electronic devices. One major issue is the reduction in the conductivity of stretchable printed wires during forming, primarily due to mechanical strain induced by stretching. Previous work demonstrated that the electrical conductivity of printed wires formulated with a molecularly designed binder can be enhanced during vacuum forming due to the development of a strain-induced conductive network.
Building on this phenomenon, the present study aims to elucidate the effect of binder chemistry on the development of electrical conductivity during forming. Designing the binder chemistry for electrically conductive pastes is essential to achieving next-generation, flexible, and 3D electronic systems via IME processes.
METHOD
Silver (Ag) flakes with an average particle diameter of 3-10 µm (AgC-A, Fukuda Foil & Powder Co., Ltd., Kyoto, Japan) were incorporated into polyhydroxyurethane (PHU, Dainichi Seika Kogyo Co., Ltd., Tokyo, Japan) at an 80 wt% concentration. This work used 6 types of PHUs with modified hydroxyl-group content and framework structures of the hard and soft segments to prepare electrically conductive pastes, as shown in Table 1. Then, a 6 wt% isocyanate-based cross-linker was added to the mixture, and the mixture was thoroughly mixed to obtain conductive pastes for printing.
The printed materials were formed into 5-mm-wide, 120-µm-thick wires. The wires were fabricated using a conductive paste prepared on a glycol-modified polyethylene terephthalate sheet measuring 200 mm × 200 mm × 0.5 mm. The sheet was placed in a vacuum forming machine and heated to 90-120 °C. Vacuum forming was then performed using a 3D-printed mold. The electrical resistance of the wires was measured during forming with copper (Cu) electrodes attached to the wires and a digital multimeter. The apparent electrical resistivity was evaluated based on the length after forming.
RESULTS AND DISCUSSION
The electrical resistivity of the wire after forming varied with binder chemistry, as shown in Fig. 1. From the viewpoint of hydroxyl group content (comparing T6, T3, and T10), increasing the content reduces the electrical resistivity of the formed wires. In addition, the molecular structure of the hard and soft segments strongly influences their electrical resistivity. The hydrogenation of aromatic units in the hard segment can reduce the electrical resistivity after formation, thereby obtaining a highly conductive 3D wiring. While the mechanism for determining the wires' electrical resistivity remains unclear, modifying the molecular structure critically affects dynamic percolation behavior, thereby controlling the wires' electrical resistivity after formation.
Using highly conductive 3D wiring, a prototype capacitive touch sensor was successfully fabricated, as shown in Fig. 2.
CONCLUSIONS
The electrical resistivity of 3D-formed wires prepared by vacuum forming can be improved by controlling dynamic percolation behavior during forming. Binder chemistry is a critical material factor that affects the kinetics of dynamic percolation.

Abstract:
Three-dimensional integrated circuits (3D ICs) are regarded as one
of the most promising approaches to overcome the physical limitations
of Moore’s law. As chip integration evolves from 2D to 3D
architectures, stacking not only significantly reduces signal
transmission time but also decreases energy consumption owing to the
shortened interconnect length.
Currently, most bonding technologies still rely on SnPb or Pb-free
SnAgCu solders. However, as the transistor density per unit area
continues to increase, the pitch between adjacent joints becomes
smaller. This scaling raises the risk of solder bump bridging. Moreover,
when chip-to-chip spacing is extremely narrow, underfill application
becomes challenging. Compounding these issues, the electrical
resistivity of solder and solder-induced intermetallic compounds is
nearly an order of magnitude higher than that of pure copper, which is
detrimental to advanced packaging for high-performance devices.
Conventional Cu-to-Cu direct bonding typically requires temperatures
above 400 °C and bonding times exceeding 60 minutes. This
prolonged high-temperature processes can damage sensitive devices,
and induce wafer warpage, misalignment, and thermal stress due to
mismatched thermal expansion coefficients. Therefore, reducing the
thermal budget of Cu–Cu bonding is highly desirable for reliable
integration of next-generation systems.
In this study, we employed direct-current electroplating with
controlled chloride ion concentrations to develop fine-grained copper
(FG-Cu) films with a strong (111) texture. Chloride ions selectively
adsorb onto (100) and (110) surfaces, effectively suppressing their
growth and allowing the (111) plane to dominate. EBSD analysis
revealed that FG-Cu fabricated with 50 ~ 100 ppm Cl⁻ exhibited grain
sizes of 170 ~ 200 nm, while higher concentrations (125 ~ 150 ppm)
produced larger grains of 240 ~ 260 nm, indicating a transition beyond
the fine-grain regime. Notably, FG-Cu maintained thermal stability,
showing negligible grain growth after four weeks of ambient storage,
and exhibited only limited coarsening even after annealing up to 200
°C for one hour. Significant grain growth (>800%) was observed at
280 °C, which serves as the benchmark bonding temperature in this
work.
The (111) fraction was also strongly correlated with Cl⁻
concentration, increasing from 16.8% at 50 ppm to a maximum of
52.1% at 125 ppm. Previous studies have reported that bonding
interfaces with identical crystalline orientations densify more slowly
than those with random orientations. Guided by this, we compared
three bonding configurations (50 ppm–50 ppm, 50 ppm–100 ppm, and
50 ppm-125 ppm). Thermal compression bonding was performed at
22 MPa, 280 °C, for 1 hour. FIB images showed that 50 ppm–50 ppm
samples displayed zig-zag interfaces with limited cross-interface
growth. In contrast, 50 ppm–100 ppm samples exhibited extensive
cross-interface grain growth and larger average grain size, leading to
reduced resistivity. However, 50 ppm-125 ppm samples suffered from
grain size different or orientations effect that hindered interfacial grain
penetration.
In summary, this work demonstrates that FG-Cu with a controlled
crystallographic texture can facilitate cross-interface grain growth,
effectively eliminate bonding interfaces, enhance mechanical strength,
and reduce resistivity. These findings provide a new pathway for
developing reliable Cu–Cu bonding technology for advanced 3D IC
packaging.

Abstract:
Recent advances in artificial intelligence (AI) and data-centric computing have significantly increased the demand for high-performance semiconductor systems, particularly for data center applications. To meet these requirements, advanced packaging technologies such as 2.5D/3D integration using through-silicon vias (TSVs) and silicon interposers have been widely adopted to realize high-density and low-latency interconnections between logic and memory components. In parallel, scaling toward panel-level packaging has attracted increasing attention due to its potential for higher productivity and cost reduction.
However, as device dimensions continue to expand and wafer thickness decreases, new challenges have emerged, including wafer warpage, mechanical instability, and process non-uniformity. In particular, stress induced during thinning and subsequent handling processes plays a critical role in determining wafer integrity, as silicon wafers become increasingly fragile at reduced thicknesses. Therefore, effective stress management and robust temporary bonding solutions are essential for enabling reliable thin-wafer processing.
In this study, a wafer support structure based on a silicon carrier is investigated from the viewpoint of stress control and warpage suppression in thinning processes. Since the silicon carrier shares identical material properties with the device wafer, stress generation caused by material mismatch can be significantly reduced, which is advantageous for large-area applications. However, due to the low optical transmittance of silicon in the visible and near-infrared regions, conventional UV and IR laser-based debonding techniques are not applicable. To address this limitation, a CO₂ laser-based debonding process utilizing localized thermal energy was applied and its feasibility was evaluated.
In addition, to enhance process scalability toward panel-level applications, a film-type temporary bonding material was introduced. Compared to liquid-type materials, film-type materials offer superior control of thickness uniformity and improved contamination management, which are particularly important for large-area processing.
As a result, stable debonding of silicon carriers using a CO₂ laser was successfully demonstrated. Furthermore, the film-type temporary bonding material contributed to improved surface flatness and process stability under large-area conditions.
The novelty of this work lies in the integrated demonstration of stress-controlled silicon carrier support, CO₂ laser debonding for optically opaque substrates, and film-type temporary bonding materials, providing a unified process concept bridging wafer-level thinning to panel-scale packaging.
These results suggest that the proposed process is a promising platform for scalable and reliable thin-wafer processing in next-generation panel-level packaging.

Abstract:
This study investigates the effect of low-k dielectric liners, liner thickness, and filling material on the thermo-mechanical reliability of Through-Silicon Vias (TSVs) using Finite Element Analysis (FEA) simulations to evaluate the Von Mises stress and TSV protrusion under thermal loading conditions. The results show that TSV reliability strongly depends on the co-optimization of liner thickness, low-k liner material and filling material. A 0.5 µm liner provided improved stress performance, while CNT-filled TSVs exhibited the lowest protrusion and a 41.3% stress reduction compared with the reference structure. These findings provide design guidelines for reliable 3D integration.

Abstract:
The adoption of wide bandgap semiconductors such as silicon carbide (SiC) in power modules is increasing to improve conversion efficiency and thermal performance. Because SiC devices operate at high temperatures, chip-to-substrate joints must provide both high thermal conductivity and high mechanical reliability. Fine silver (Ag) sintering has attracted attention as an alternative to conventional Sn-based soldering; however, interfacial delamination can occur due to shrinkage during sintering and thermomechanical stress arising from CTE mismatch. In our previous study, high-strength Ag-sintered joints were achieved by Zn/Ag plating, but the effect of shear strain was not fully alleviated. In this study, we investigated whether solder plating on the bonding surface could further improve interfacial reliability.
　SiC chips with Au-plated bonding surfaces were bonded to C1100 copper substrates whose bonding surfaces were electrodeposited with either pure Sn or an Au–20 wt% Sn alloy. Fine Ag particle paste was screen printed on the plated substrates, and the assemblies were heated in N2 to form Ag-sintered joints. Joint quality was evaluated by scanning acoustic tomography (SAT), and the interfacial morphology and elemental distribution were analyzed by SEM/EDS.
　Ag sintering on the Sn-plated copper resulted in delamination across the entire interface. Fracture surface analysis showed Ag–Sn intermetallic compounds on the SiC side and Cu–Sn intermetallic compounds on the copper side. In contrast, Ag sintering on copper plated with Au–20 wt% Sn achieved full-area bonding, as confirmed by SAT. After 50 thermal cycles between −40 and 150 °C, no delamination was observed by SAT, and cross-sectional observations showed that crack propagation was substantially suppressed compared with the Sn-plated sample. Elemental mapping at the Ag/substrate interface revealed a mixed intermetallic layer containing Au, Ag, Cu, and Sn.
　These results indicate that pre-plating the copper substrate with a thin Au–20 wt% Sn layer prior to Ag sintering effectively suppresses interfacial delamination and improves thermal cycling reliability. The mixed Au–Ag–Cu–Sn intermetallic layer likely contributes to crack suppression by accommodating sintering shrinkage and thermomechanical strain. Further investigation of the mechanical properties of this interfacial layer and optimization of plating composition and thickness will be necessary to enhance joint reliability.

Abstract:

The transition toward sustainable mobility electronics requires a fundamental shift in how electronic systems are designed, manufactured, and managed across their entire lifecycle. Electronics—particularly semiconductors and printed circuit boards (PCBs)—represent a major contributor to the product carbon footprint (PCF) of modern vehicles, making them a key focus area for decarbonization efforts. At the same time, increasing regulatory pressure, ambitious OEM climate targets, and growing e-waste volumes are accelerating the need for scalable and economically viable solutions.

A holistic approach is required, combining lifecycle-oriented strategies with targeted innovations in materials and processes. Circular economy principles play a central role, implemented through comprehensive strategies addressing product creation, use, and post-use phases. Measures such as material reduction, design optimization, reuse, repair, and remanufacturing are particularly effective at the system level, where higher recovery value and functional reuse can be realized. However, due to the complexity and low material content of electronic components, recycling alone is insufficient; instead, significant CO₂ reduction must be achieved through energy-efficient production, optimized material selection, and supply chain alignment.
Emerging PCB technologies provide concrete levers to reduce both e-waste and carbon emissions. New recyclable laminate materials enable closed-loop or cascaded reuse of non-metallic fractions, while bio-based PCB substrates derived from renewable resources offer significant reductions in embodied carbon—up to approximately 35% compared to conventional FR 4—without compromising performance or reliability. Further improvements are enabled by additive manufacturing approaches, such as inkjet-based copper deposition, which produce conductive structures only where needed. Compared to conventional subtractive processes, these technologies significantly reduce copper consumption, water usage, and energy demand, contributing to a substantial overall reduction in environmental impact.
Close collaboration across the supply chain and alignment with evolving standards are essential to scale these solutions and meet future climate and regulatory requirements.

Abstract:
A fuel cell is an energy conversion device that can directly and continuously convert chemical energy in a fuel into electrical energy. When hydrogen is used as the fuel for such a device, water will be the only product of the power conversion process. As there are no carbon dioxide emissions or air pollutants, hydrogen fuel cells can become an eco-friendly energy solution toward mitigating the increasing global energy consumption and environmental pollution caused by fossil-fuel energy usage.
The basic physical architecture of a fuel cell is an electrolyte layer sandwiched between an anode and a cathode. Because a fuel cell contains fewer moving parts, a fuel cell generates less noise during operation. Based on the types of electrolyte used in the cells, fuel cells can be classified as Proton Exchange Membrane Fuel Cell (PEMFC), Alkaline Fuel Cell (AFC), Phosphoric Acid Fuel Cell (PAFC), Molten Carbonate Fuel Cell (MCFC), Solid Oxide Fuel Cell (SOFC), and Direct Methanol Fuel Cell (DMFC). Among those six types of fuel cells, PEMFC is the most widely used and investigated due to its relatively low operating temperature (60–180 °C), simple reagents, compact systems, and the commercial availability of components.
For a PEMFC, the active part of the fuel cell, membrane electrode assembly (MEA), contains a solid proton-exchange membrane sandwiched between the cathode and anode catalyst layers (CLs). Typically, CLs are prepared from a mixture of electrically conductive support, catalyst particles, and a proton-conducting ionomer. The MEA, along with the gas diffusion layer (GDL), can create the triple phase boundary (TPB) for desired electrochemical reactions to occur. Currently, most commonly used ionomers, such as Nanfion®, are copolymers consisting of perfluorinated segments with sulfonic acid groups.
Due to its ease of synthesis and good environmental stability, polyaniline (PANI) has become one of the electronic polymers that attract the research interest of many scientists and engineers. With the advance in recent technological development, polyaniline has been extensively exploited for use in organic electronics, actuators, separation membranes and microelectromechanical systems (MEMS). Polyaniline can be synthesized by oxidative chemical polymerization in an acidic aqueous medium with pH < ~2. With a further treatment by fuming sulfuric acid, sulfonated polyaniline has been prepared for use in antibiofouling applications.
In this study, a series of sulfonated polyaniline polymers were synthesized. Three monomers, aniline, 2-methoxyaniline and 2-ethylaniline, were used to prepare fluorine-free ionomers for applications in fuel cell operation. Under similar conditions, experimental results showed that, while the fuel cell using Nanfion® as the ionomer gave a maximum power density of 499 mW/cm2, the maximum power density for the fuel cell using sulfonated poly(aniline), poly(2-methoxyaniline) and poly(2-ethylaniline) was 664 mW/cm2, 220 mW/cm2, and 209 mW/cm2, respectively, indicating that sulfonated poly(aniline) can be further investigated for use as a fluorine-free ionomer.

Abstract:
The printed circuit board (PCB) industry is a critical manufacturing foundation for semiconductors, advanced packaging, high-speed communication, and AI-related electronic systems. While extensive studies have addressed PCB materials, processes, interconnection technologies, and reliability, long-term empirical evidence on the competitiveness and manufacturing capability of PCB-related firms remains limited. This study integrates a series of empirical analyses of the Japanese and Taiwanese PCB industries and examines the determinants of profitability, technology investment, macroeconomic exposure, and firm-specific capability. The research was developed with valuable cooperation and industry insights from the Japan Electronics Packaging and Circuits Association (JPCA) and the Taiwan Printed Circuit Association (TPCA).

A firm-level panel dataset was constructed for 42 listed PCB-related companies in Japan and Taiwan, covering 23 years from 2000 to 2023. The sample was classified into PCB manufacturers and material/equipment suppliers. Fixed-effects models were applied using operating profit margin and return on assets as profitability measures. Explanatory variables included sales scale, R&D intensity, capital investment intensity, financial leverage, cash holdings, M&A activity, the interaction between R&D intensity and cash holdings, and GDP growth rates. In addition, firm-specific effects estimated from the fixed-effects models were compared with market valuation measured by the price-to-book ratio (PBR). PBR was further decomposed into profitability-related components based on ROE and residual components not explained by ROE.

The results show three main findings. First, Japanese PCB manufacturers exhibited relatively low profitability and productivity compared with Taiwanese PCB manufacturers, despite active capital investment, whereas Japanese material and equipment suppliers showed higher profitability and a stronger tendency toward upfront investment. Capital investment was positively associated with profitability in most categories, while M&A activity did not show a statistically significant contribution. Second, R&D intensity had a statistically significant negative relationship with profitability, reflecting the accounting treatment of R&D as an expense. However, for Japanese PCB manufacturers, the interaction between R&D intensity and cash holdings was positive and significant, suggesting that R&D investment may contribute to profitability when supported by sufficient financial strength. Third, world GDP growth was positively associated with the profitability of Japanese PCB manufacturers, while neither world nor Chinese GDP growth showed significant effects for Taiwanese PCB manufacturers, implying that Taiwanese firms may secure profitability through geographically diversified operations beyond China.

Furthermore, firm-specific effects were positively associated with PBR and with the ROE-adjusted residual component of PBR for Japanese PCB manufacturers. This suggests that persistent, unobserved firm-specific capabilities, including manufacturing know-how, human capital, technological accumulation, and organizational capability, may be partly reflected in market valuation. This study provides rare long-term empirical evidence on Japan-Taiwan PCB competitiveness and offers implications for technology investment, supply-chain resilience, and capability building in the advanced packaging and AI electronics era.

Keywords: Printed Circuit Board, Panel Data Analysis, Fixed-Effects Model, Japan–Taiwan Comparison, Manufacturing Capability, R&D Investment

Abstract:
The rapid growth of artificial intelligence (AI) computing is driving substantial increases in data center platform power, with CPUs and XPUs moving from several hundred watts toward multi-kilowatt-class operation. As processor current continues to rise, printed circuit board (PCB) power-delivery networks must support higher current density while controlling IR drop, conductor power loss, thermal rise, manufacturability, and cost. Conventional approaches, including increased copper thickness and additional power layers, are increasingly constrained by PCB thickness, stack-up complexity, process capability, and system cost. Consequently, improving the effective electrical and thermal transport capability of copper conductors within existing PCB design envelopes has become a critical requirement for next-generation AI server power-delivery optimization. Previous work showed that an advanced copper foil (ADCF) with optimized surface roughness can reduce direct-current resistance compared with conventional reverse treated foil (RTF) at room temperature. However, AI server boards typically operate under elevated thermal conditions during sustained high-power workloads. PCB temperatures can exceed 40°C, and localized high-current regions near processor ball-grid-array power delivery structures may approach 80°C. Since copper resistance increases with temperature, elevated operating conditions can further amplify IR drop and conductor power loss. Temperature-dependent characterization is therefore necessary to evaluate practical conductor performance for high-power AI systems. This paper compares the electrical and thermal transport behavior of ADCF and conventional RTF from 25°C to 80°C using controlled experimental methods. A six-layer PCB resistance test vehicle with dedicated inner-layer power planes was fabricated using 2 oz copper foils. Kelvin resistance measurements were conducted in a programmable thermal chamber by an independent third-party laboratory. Chamber relative humidity was stabilized at 45%, and measurements were taken only after eight thermal sensors mounted on the top and bottom surfaces of the test vehicle confirmed thermal equilibrium at each target condition. Four temperature points—25°C, 40°C, 60°C, and 80°C—were selected to capture the approximately linear temperature-dependent resistance behavior of copper across the relevant operating range. The Kelvin measurement structure and ΔL extraction method were used to minimize contact resistance, cable resistance, and other parasitic effects, enabling accurate comparison of conductor resistance. In addition, transient plane source (TPS) measurements were performed on bare copper foil samples to evaluate thermal conductivity, and cross-sectional analysis was used to quantify total copper thickness, bulk copper thickness, and roughness-region thickness. The results show that ADCF consistently provides lower resistance than conventional RTF across the full temperature range. Using the theoretical 2 oz copper resistance of 128.38 μΩ at 25°C as the reference and applying a copper temperature coefficient of resistance of approximately 0.0039 °C⁻¹, the estimated theoretical resistance values at 40°C, 60°C, and 80°C are 135.89 μΩ, 145.91 μΩ, and 155.93 μΩ, respectively. Relative to conventional RTF, ADCF reduces conductor resistance by approximately 8.7% to 9.0% from 25°C to 80°C while maintaining electrical conductivity close to theoretical copper. TPS results further show that ADCF achieves a thermal conductivity of 349.5 W/m·K, compared with 322.4 W/m·K for conventional RTF at 25°C, corresponding to an approximately 8.4% improvement. Wiedemann–Franz analysis shows that ADCF and conventional RTF exhibit similar Lorenz numbers, indicating that both foils follow the same fundamental electron transport mechanism and that the observed improvement is primarily attributed to conductor geometry rather than intrinsic copper material differences. Cross-sectional measurements support this interpretation: although both foils have a similar overall 2 oz copper thickness of approximately 70 μm, ADCF contains approximately 8 μm more bulk copper and approximately 8 μm less roughness than conventional RTF. The larger effective bulk copper region provides a more efficient current and heat transport path, explaining the measured reduction in resistance and improvement in thermal conductivity. These findings demonstrate that copper foil surface engineering provides a practical and scalable approach to improve PCB power-delivery efficiency without adding copper layers or increasing board thickness. For next-generation AI servers, ADCF offers a promising material solution to reduce IR drop, lower conductor power loss, and improve thermal transport in high-current PCB power planes.

Abstract:
We will report diamond microchannel heatsink-based thermal solutions for future generations of semiconductor industry. Laser machining was applied to fabricate diamond microchannels with or without micropillars. Water cooling was applied with heat sources being applied to the baseplate of a MCHS. Water flow rate, temperature, and heat inputs are recorded to measure the heat transfer coefficient of different designs of MCHS.

Abstract:
This work presents a novel approach to 3D photonics chip packaging utilizing Through-Silicon Optical Tunable Interconnects (TSOTIs). Embedding vertical optical pathways directly through silicon substrates for photonics engine and integrated photo detectors on package substrate, this architecture enablesscalable 3D integration of photonic circuits with precise alignment and less insertion losses