Sessions Index

Bio:

Frank earned his Ph.D. from Carnegie Mellon University in Pittsburgh, Pennsylvania. He is currently a Vice President at TSMC Technology Inc. in San Jose, California, where he leads the Custom Design Methodology group. His work focuses on advancing analog/RF design automation and migration for cutting-edge nodes, as well as pioneering 3D COUPE silicon photonics design and analysis methodologies. Prior to his role at TSMC, Frank served as Vice President at Synopsys in Mountain View, California. During his tenure there, he significantly contributed to a diverse array of products, including IR/EM analysis, RC extraction, advanced delay calculation, static timing analysis, timing optimization, advanced placement and routing, physical synthesis, cell characterization, and both SPICE and fast SPICE circuit simulation.

Abstract:

As artificial intelligence workloads scale exponentially, energy efficiency has emerged as a critical bottleneck in sustaining performance growth. This keynote explores how TSMC’s advanced semiconductor technologies are reshaping the energy-performance landscape for AI. We will highlight the latest innovations across process nodes, 3D integration, and advanced packaging—including CoWoS®, InFO®, and the COUPE architecture—that are purpose-built to reduce energy per operation while supporting massive compute density. The talk will delve into how TSMC’s technology platforms enable AI accelerators, GPUs, and edge AI chips to achieve unprecedented power efficiency, addressing both datacenter and edge deployment challenges. By bridging silicon scaling and system-level optimization, TSMC is empowering its ecosystem to build sustainable AI infrastructure for the future.

 

Bio:

Dr. Babak Sabi is VP of Technology at AWS/Annapurna Lab. Babak joined AWS in 2024 after 40 years in Intel. Babak was Senior Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly, and test process technology development. During Babak’s tenure in ATTD 2.5D and 3D Advanced Packages were developed and ramp to high Volume Manufacturing. Additionally ATTD team made many advancement in Substrate and Test Technology.
Prior to leading ATTD, Babak oversaw Intel’s Corporate Quality Network from 2002 to 2009 where he led product reliability, customer satisfaction and quality business practices.
Babak joined Intel in 1984 after receiving Babak his Ph.D. in solid state electronics from Ohio State University in 1984.

Abstract:

 

Bio:

Jatin leads the Data Center (Xeon) Customer and Systems Engineering team within Intel’s Platform Engineering Group. He is responsible for overseeing and driving all aspects of front-line customer engineering, including managing customer requirements, resolving customer issues, ensuring customer readiness and acceleration, enabling industry and ecosystem partnerships, and fostering joint technology innovations.
Jatin began his career at Intel in 1995 as a chipset validation engineer and has since led various validation activities, including Pre-Silicon Systems, functional validation, IO/electrical validation, power/performance, customer enabling, Circuit Marginality Validation, and tester debug.
With extensive experience across mobile, micro-server, cable modem, and data center segments, Jatin is passionate about developing the next generation of leaders, building high-performing organizations, and driving innovation and efficiencies. He holds a Master's degree in Computer Architecture and an MBA in Engineering Management, and has multiple publications in parallel processing.

Abstract:

Abstract: As data centers rapidly evolve to meet the increasing demands of AI and high-performance computing, architectural innovation is more critical than ever. This presentation addresses the complex challenges of modern data center design—from node-level integration to full-scale infrastructure orchestration. It highlights Intel’s innovation pillars, including advancements in memory technologies, high-speed interconnects, power delivery, thermal management, and software-defined infrastructure. Through a co-design approach across hardware and software, Intel showcases scalable solutions that enhance performance, efficiency, and reliability. Real-world applications—from healthcare to agriculture—demonstrate the transformative impact of these technologies. The session underscores the importance of industry collaboration and open standards, inviting ecosystem partners to join Intel in shaping the future of data center and AI infrastructure.

 

 

Bio:

Abstract:

Inference tasks vary widely in complexity, data size, latency requirements, and parallelism, and each workload type interacts differently with CPU capabilities. Understanding this relationship allows for more effective hardware selection and optimization strategies tailored to specific use cases.
Key Learning Areas
-AI Model Architecture
-Types of Inference Workloads
-Quantization: Balancing Accuracy and Efficiency
-Data Throughput and Bandwidth
-Benchmarking Inference Performance
-Frameworks and Libraries Impact Performance

 

Bio:

Jay Wu is a platform application engineer at Intel's Data Center Group, specializing in thermal and mechanical development for datacenter products. He holds a Master's Degree in Mechanical Engineering from National Taiwan University.

Abstract:

As memory capacity and bandwidth demands continue to rise, system designs are pushing toward higher memory density—particularly in dual-socket server platforms. This session will explore the thermal design challenges and considerations involved in supporting a 2-socket, 32-DIMM configuration on the latest Intel® Xeon® platform within a standard 19-inch rack chassis. In such configurations, DIMM pitch is constrained to 0.25"–0.27", significantly increasing the complexity of memory cooling. We will present thermal evaluation results based on Intel-developed CPU and DDR5 Thermal Test Vehicles (TTVs), which simulate real-world heat profiles and airflow interactions.

 

Bio:

Thonas Su is a Tech Lead at Intel with over 15 years of experience in customer technical support within the server industry. He specializes in signal integrity simulation, enabling customers to perform risk analysis through simulation on Intel server products. His role also includes delivering technical training and providing ongoing support to customers. Thonas holds a Master’s degree from National Yang Ming Chiao Tung University (formerly NCTU) and is currently focused on PCI Express 6.0 and the upcoming 7.0 standards.

Abstract:

The dimensions of the Intel next platform has experienced an increase compared to the preceding ones, primarily due to the augmentation in pin count to increase the signal to ｄnoise ratio in both PCI Express 6.0 and DDR5. This alteration creates difficulties in arranging two processors, each of them has a 16 DDR5 channels, on a standard 19-inch rack. In response to this issue, Intel has embarked on a strategic initiative aimed at facilitating the accommodation of this challenge, which involves a proposal to reduce the distance between DDR5 connectors (a.k.a. DIMM pitch) as well as the processor’s keep out zone. To increase the DDR routing space underneath the DIMM connector’s pin-field area after shrinking the DIMM to DIMMM pitch, VIPPO (Via in Pad Plated Over) PCB (Printed Circuit Board) technology is used. These technologies significantly enhance signal quality when embracing the next generation MCRDIMM (Multiplexer Combined Ranks DIMM).

 

Bio:

Bryant Tsai is a customer system engineer at Intel Platform Engineering Group. Bryant has been working in the industry for 17 years, he started his career in Inventect from 2008 to 2014, and HPE from 2014-2021. In the same year, Bryant joined Intel as a Power Delivery engineer and responsible for power delivery and power integrity design of customer enabling.

Abstract:

The exponential growth in AI workload deployment has led scenarios where an 8-GPU server can consume up to 10kW, and the entire rack may consume more than 100kW, emphasizing the critical importance of power efficiency. This session presents a detailed power loss analysis across key components of power distribution within AI servers and at the rack scale and proposes future optimization directions.

 

Bio:

Ryan Chang is an experienced engineer in signal integrity and hardware design. He began his career at Wistron Corporation, where he worked from 2006 to 2018, gaining extensive experience in system development and engineering. From 2018 to 2021, he continued to build his expertise at Hewlett Packard Enterprise, contributing to high-performance computing and enterprise solutions. In 2021, Ryan joined Intel Corporation as a Signal Integrity Engineer, where he currently focuses on high-speed interface design and signal integrity analysis for next-generation computing platforms.

Abstract:

In recent years, with the continuous increase in speeds for high-speed interfaces such as PCIe in data centers, cables as enablers of high-speed interconnects have played an increasingly important role in long reach transmission channels. Raw cables are a key factor in cable assemblies and are the focus of this research. This study considers numerous factors related to the electrical characterizations of raw cables, including the testing process and methodology [1], the selection and comparison of fixture de-embedding algorithms, the extraction and fitting of simulation models, and the electrical specifications for test fixtures. Based on these considerations, a raw cable database was established, and the electrical characteristic trends and impacts of raw cables were statistically analyzed under multi-sample conditions. These standardized methods, processes, insights, and corresponding simulation and measurement examples provide detailed and comprehensive research on raw cable electrical characteristics, enabling raw cables to serve as important enablers for PCIe 5.0 and beyond.

 

Bio:

Dr. Daniel Ng is a AMD fellow working on enabling advance package technology for AMD products. He has around 20 years of experience in various capacity in the packaging world from substrate to advanced assembly technology development. He currently leads a team to drive OSAT technology development.

Abstract:

Advanced packaging architectures are fundamental building blocks to the explosive growth of AI and HPC. In order to meet the demands of current and future AI and HPC applications, evolution in packaging technology is essential to keep pace with the demand. In addition, emphasis on the innovations and optimization of AI hardwares beyond the package will also be discussed. Product performance improvements through the various advanced packaging architectures used at AMD's range of products will be discussed highlighting the importance and benefits of continuous technology breakthrough. Lastly, new technology evolution to further advance AI and HPC applications will also be discussed.

 

Bio:

Bora Baloglu is currently the Business Development Director for Advanced Packaging at Intel Foundry, overseeing both Asia and Europe regions. He has been with Intel for the past three years. Prior to joining Intel, he spent about eleven years at Amkor Technology, where he worked in the Research and Development Department, focusing on wafer-level and panel-level packaging technologies and also in Wafer Level Business Units. During his time at Amkor, he also completed a three-year expatriate assignment in Portugal, working on the development of the Panel-Level Fan-Out platform. Bora holds over 60 issued and pending patents in semiconductor packaging field. He earned his Master’s and Ph.D. degrees from Lehigh University in Bethlehem, Pennsylvania, completing his studies in 2011.

Abstract:

Advanced packaging has become a key technology in boosting the computing performance of silicon chips, especially as traditional transistor scaling becomes increasingly difficult and expensive, particularly for high-power demanding applications like AI and Machine Learning. Primarily the heterogeneous integration and 2.5D packaging architectures have become essential, enabling greater performance and functionality by integrating multiple components within a single package. This presentation will highlight Intel’s latest advancements in packaging technologies, including EMIB (Embedded Multi-Die Interconnect Bridge), 2.5D-equivalent solution, and It will also examine the opportunities and challenges in developing the next generation of advanced packaging architectures.

 

Bio:

Venkata Mokkapati is currently Director, Business Development & Application Engineering at AT&S AG based in Austria. Venkata has more than 18 years of experience in Semiconductor industry and is a certified ICP engineer from Delft University of Technology from where he also holds a PhD. Prior to joining the industry in 2018, Venkata has spent 12 years in academics in various universities/Institutes across Europe and Asia. Venkata also has experience in establishing and running a sole trading company on graphene and other 2D materials. Venkata has authored and co-authored more than 40 peer-review journals/conference proceedings/patents. He is also a recipient of EC-FP7 Marie Curie Co-fund fellowship.

Abstract:

Advanced Packaging (AP) is further evolving as several amendments are needed with increasing technical, architectural/functional and market demands. IC substrates play an important role in interconnecting Silicon with organic world and have to follow the packaging trends. This talk focuses on the current trends, new technologies, requirements and solutions that IC substrates can offer to meet the industry demands. Large Form factors, Embedded components and UHD (Ultra High Density) substrates will be discussed in detail.

 

Bio:

Christian joined Atotech in 2010 after completing his PhD in chemistry. In 2013, he became Head of R&D for electrolytic copper plating, focusing on advanced metallization processes across various equipment platforms. Since 2020, he has served as Global Product Director and General Manager for Semiconductor, Final finishing and Functional Electronics Coatings, leading global innovation and strategy in surface finishing technologies.

Abstract:

1) Roadmap and future requirements
2) Technical features and
3) Performance highlights
4) Applications and use cases

 

Bio:

Kuldip Johal has been with Atotech for over 37 years. During this period, he has held several positions, including R&D Management, GM Product Director, North America Managing Director, and Global OEM/Pathfinding Senior Director. He is currently the MSD CTO/VP of Business Development, where he is responsible for developing the divisional-advanced packaging technology strategy, and for working with key industry influencers and supply chain enablers. He fosters a collaborative approach across business units (BUs) and regions to accelerate business growth.

Abstract:

This talk focuses on the evolution of advanced packaging and its continous drive for "more than moore"

1) Introduction artifical inteleigance changing the digital world.
2)Interconnect technologies from Silicon to PCB
3)Key technology challenges impacting IC substrate and PCB.
4) Adoption of SC manufacturing approaches and Supply chain collaborations.

5) Summary

 

Bio:

Abstract:

 

Bio:

Dr Devan Iyer joined GEA in March 2024 as a Chief Strategist for Advanced Electronic Packaging . Dr Iyer has more than 35 years of experience in component and systems design & packaging technology , assembly & test manufacturing and Business unit leadership . He has served as Senior Vice President of Business units at Amkor Technology and Corporate Vice President at Texas Instruments. He has also worked for Infineon Technologies & General Electric.
As R&D Director, he also led industry consortia in advanced pack aging at Institute of Microelectronics in Singapore and at the Packaging Research Center at Georgia Tech in electronic packaging designs and technology. Dr Iyer has more than 250 technical publications and 35 patents to his credit.

Abstract:

 

Bio:

Dr. Raja Swaminathan is the Corporate Vice President of Heterogeneous Integration Technologies at AMD, spearheading the development of AMD's advanced packaging and heterogeneous integration roadmap. He also leads the Optics technology development at AMD, driving innovation in high-speed optical interconnects and photonics integration.

With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan's expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple's Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators.

Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to his name, he was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology. He also shares his insights on life and leadership, drawing lessons from the semiconductor industry, on his LinkedIn profile.

Abstract:

Chiplet architectures are becoming foundational to the continued economic and power-efficient scaling of AI hardware and edge computing. As Moore’s Law slows, the convergence of system integration and advanced packaging has emerged as a critical enabler at the intersection of technology and architecture. This keynote will explore how heterogeneous integration—spanning 2.5D and 3D hybrid bonded architectures—is driving AMD’s industry-leading roadmap to optimize power, performance, area, and cost (PPAC). Beyond packaging, the talk will highlight the broader system-level innovations required to integrate diverse chiplets into cohesive, high-performance modules. Topics will include chiplets for AI, system integration challenges, interconnect strategies, and solutions for large-scale chiplet-based systems.

 

Bio:

Dr. CP Hung, IEEE Fellow, is currently Vice President of Corporate R&D, at ASE Group, responsible for next-generation product development featuring integrated technologies, as well as a broad range of advanced chip, package, test, and system integrating solutions for multiple ASE and USI Sites.

He holds 354 patents encompassing IC packaging structure, process, substrate and characterization technology. He has published over 142 conference and journal papers.

Abstract:

By exploring the data center and AI landscape, heterogeneous integration (HI) through advanced packages is propelling pivotal complex integration in various structures, with optimizing stress, thermal and electrical limits for dynamic challenges on compute bandwidth, energy efficiency and smaller form factors, thus, highlighting required collective collaboration.

 

Bio:

Dennis ( Tiang-Ho) born in Taiwan , has been working in PCB industry from 1987. Dennis has been with Kinsus since 2005. He spends most of his time in the R&D department and is currently a Senior Director at the Advanced Product R&D team. Dennis has also authored more than 15 books on PCB and publishes regularly on PCB magazines.

Abstract:

The talk briefly describes some of the advanced packaging technology platforms like CoWoS with focus on high performance compute for AI applications. The talks covers salient aspects of large substrates with needs and challenges centered around power delivery, low loss , low warpage and high volume manufacturing. Material selection and their properties will also be discussed during this talk. Some of the innovative materials & processes to meet the demands and challenges will also be highlighted.

 

Bio:

Ander leads an international team dedicated to advancing PCBA processes, fostering continuous innovation and improving manufacturing efficiency. He oversees comprehensive Design for Excellence (DfX) evaluations, ensuring new product designs meet the highest standards of manufacturability, quality, and reliability. Ander manages in-depth process & material failure analyses to identify and address potential product issues, driving improved long-term performance and reliability. He also directs efforts in developing Co-package technology, achieving significant advancements in assembly integration and optical testing capabilities.

Abstract:

With the rapid development of AI computational capabilities, the increasing size and quantity of ASIC and GPU chips have posed significant challenges to SMT packaging processes. This has escalated the complexity in chip design and process integration, introducing substantial challenges to the overall packaging workflow.

Current issues in the production and application of large Ball Grid Arrays primarily revolve around the following aspects: a) Soldering Defects - The increased risk of warpage-induced soldering failures in Large Form Factor components, such as Head-in-Pillow (HIP) effects, solder joint opens, and solder bridging b) Radiation Dosage: HBM and other radiation-sensitive components impose restrictions on X-ray inspection time and frequency. 2.5D or 3D High Performance Computing (HPC) components and product designs require high-intensity X-ray sources that can penetrate through their layers to inspect solder joints and TIM. c) Thermal Conductivity: Warpage effects during High Power Component assembly introduce a gap in the interface between the component and the cold plate, decreasing the effectiveness of metal TIM2 (compressible TIMs).

These challenges highlight the need to develop innovative strategies in advanced packaging technologies and inspection methodologies, as well as refine process controls to mitigate issues related to warpage, radiation sensitivity, and thermal efficiency in next-generation AI-enabled devices. To address these challenges, this study focuses on improvements from three perspectives: Material Selection-  By using low-CTE substrates along with reinforced PCB strength, symmetrical PCB designs, and balanced copper distribution, the goal is to mitigate the impact of warpage. SMT Process Optimization- Techniques such as specific reflow fixtures, corner supports for Large Form Factor components, low-temperature solder paste, and tailored reflow profiles effectively reduce thermal deformation during soldering. Inspection and Analysis Techniques-  Thermal deformation measurement and warpage analysis are employed to evaluate dynamic deformation trends of both PCBs and components across reflow temperature profiles. Additionally, CT-X-ray techniques enable multi-layer depth analysis of solder joints, providing comprehensive 3D insights into defects like solder joint opens and HIP issues.

 

Bio:

Prof. Chih Chen is currently the chair professor in Dept. of Materials Science and Engineering, National Yang Ming Chiao Tung University (NYCU).
Chih Chen received his Ph.D. degrees in Materials Science of University of California at Los Angeles (UCLA) in 1999 in Prof. King-Ning Tu’s group. He joined NYCU Taiwan in 2000 and served as the Chairman of Department of Materials Science and Engineering in NYCU from Feb. 2017 to Jan. 2023. Professor Chen discovered electrodeposition of (111)-oriented nanotwinned Cu, and reported it in Science 336, 1007-1010 (2012), and transferred the technology to Chemleaders, Inc, Taiwan for mass production in 2016. Therefore, he received the 2016 National Innovation Award, 2016 Materials Innovation Award, Materials Research Society, Taiwan, 2017 Outstanding Technology Transfer Award on Electroplating and Application of High (111)-oriented Nanotwinned Cu, 2018 & 2023 Outstanding Researcher Award from National Science & Technology Council Taiwan, TMS 2018 Research to Practice Award from The Minerals, Metals & Materials Society (TMS, USA). He was recognized as fellow of International Association of Advanced Materials (IAAM) in 2020 and Fellow of The Materials Research Society-Taiwan (MRS-T) in 2022.
His current research interests are low-temperature Cu-to-Cu direct bonding, high strength nanotwinned Cu lines and films for 3D IC integration, reliabilities of flip-chip solder joints and microbumps for microelectronics packaging, including electromigration, thermomigration, and metallurgical reactions. He published 200+ journal papers and he holds 35+ Taiwan and US patents. He wrote a book with Prof. King-Ning Tu and Prof. H.M. Chen on Electronic Packaging Science and Technology, which has been published by Wiley in 2021.

Abstract:

As the dimensions of Cu hybrid joints continue to shrink, the bonding process faces significant challenges. One major issue is the limited thermal expansion of Cu pads within dielectric vias, as most of the Cu volume adheres to the via sidewalls. This restriction narrows the bonding process window. Fine-grained Cu (FG-Cu) offers a promising solution to this limitation.

In this presentation, we will discuss the electrodeposition of FG-Cu into SiO₂ vias and analyze the resulting grain size distribution. In-situ heating atomic force microscopy (AFM) was employed to measure the thermal expansion behavior of FG-Cu pads embedded in SiO₂ vias. The results reveal that FG-Cu exhibits excellent thermal expansion capability, attributed to its high creep rate at relatively low temperatures.

Furthermore, bonding between FG-Cu pads and FG-Cu films will be demonstrated, showing that NC-Cu effectively reduces interfacial void formation. Finally, the thermal stability and oxidation behavior of FG-Cu will also be addressed.

 

 

Bio:
Masao Tomikawa joined Toray Industries, Inc. after earning a master's degree from the University of Tokyo. Studied at the University of Akron in the United States from 1992 to 1994. In 2007, he was certified as a research fellow at Toray Industries, Inc., and then became a director of Toray Industries, Inc. in 2020 and a senior fellow at Toray Industries, Inc. in 2024. During this time, he obtained a doctor degree from the Tokyo Institute of Technology in 2011 and became a fellow of the Society of Polymer Science in 2019. His specialties are polymer synthesis, physical properties, and photosensitive design. Awards 1991: Society of Polymer Science Technology Award 2009: Chemical Technology Award, Chemical Society of Japan 2015: National Invention Award, Japan Institute of Invention and Innovation 2018: Best Paper Award Pan Pacific Microelectronics Symposium 2020: Achievement Award, Photopolymer Society of Japan 2020: Minister of Education, Culture, Sports, Science and Technology Award.

Abstract:
Hybrid bonding technology is attracting attention as a next-generation high-density mounting technology. This technology has already been used to improve the performance of CMOS image sensors by bonding wafers together using inorganic insulating films such as copper and copper, and SiO2 and SiO2. (1) Further development is being considered for use in three-dimensional stacking of semiconductor chips of different functions and sizes. In such applications, it is considered to bond chips onto wafers, and in addition to being able to do so at low temperatures and with low warpage, tolerance to fine foreign matter is important.
We have created a process using flexible resin with hybrid bonding technology that is resistant to nano scale particles, and have demonstrated that a yield of nearly 100% can be obtained even when bonding blade-diced chips and have not been adequately controlled for fine particles. Furthermore, bonding is possible at low temperatures of less than 250°C, and warpage is about one-third smaller than in the SiO2-SiO2 process, so we believe that this technology is suitable for hybrid bonding of chips and wafers or chips and interposers (2).
It has been reported that in hybrid bonds, polar groups generated by plasma activation during the annealing process after SiO2-SiO2 bonding undergo chemical reactions, generating water and creating voids (3). In polyimide materials, polar components are also generated by plasma activation, which creates chemical bonds, and water may be generated in the same way as in SiO2. Organic materials have higher gas permeability than inorganic materials, and it is thought that organic materials can eliminate the generated water vapor. Quantifying this characteristic is important in discussing device reliability. In this study, we investigated the generation and movement of water during the hybrid bonding process.
A polyimide material (PI-1), which can be cured at a low temperature process below 250 °C, was used as the dielectric layer for the hybrid bonding lamination process. The insulation reliability of this material was confirmed by bias-highly accelerated stress testing (B-HAST) with 1 μm L&S (4).
Based on previous studies, it is estimated that hydrophilization occurs in polyimide materials as well as conventional inorganic materials during the surface activation process by plasma treatment, and chemical bonds are formed between polymers and polymers and between polymers and SiO2 during the TCB and post-annealing processes, generating water. PI-1 was surface-activated by plasma treatment, and the hydrophilicity of the surface was confirmed by X-ray photoelectron spectroscopy (XPS) and surface free energy (SFE) analysis. This suggests that water is generated by chemical bond formation during the bonding and annealing processes. Assuming that the thickness of the active layer is 5 nm from the surface, it can be estimated that a maximum of about 1.2 ng/cm² of H₂O is generated. To determine whether this water can be removed to the outside, the amount of water vapor permeated through the PI-1 film was measured using the following method.
The amount of water vapor permeating the PI-1 film was measured using a differential pressure steady-state method at temperatures of 25, 70, 110, and 150°C respectively. The water permeability coefficient of PI-1 under each obtained condition was in good agreement with the Arrhenius equation, as theoretically predicted [5]. Using this approximation, the water vapor permeability coefficient at process temperatures of 200°C to 250°C was estimated. According to these results, the vapor pressure of the evaporated H₂O generated at the PI-1 interface during annealing at 250 °C for 1 hour is calculated to be 3.98 MPa. Assuming that the PI-1 film thickness is 5 µm and the chip size is 6 mm × 6 mm, the amount of water permeation is roughly estimated to be more than 1 µg, which is nearly 1000 times the amount of water generated above. This means that all of the H₂O generated at the bonding interface may permeate out of the film. In addition, when considering the amount of water generated, it is necessary to consider the water absorption and imidization rate of the polyimide film. The amount of H₂O absorbed by the film and the amount of H₂O generated by the imidization reaction of the polyimide precursor during curing were also estimated. Then, the temperature and time conditions required for the permeation and release of H₂O from the film were examined. The results are reported in this full paper

 

Bio:
Yi-Chen Chung is a Ph.D. student at National Yang Ming Chiao Tung University under the supervision of Prof. Chih Chen. His research focuses on advanced packaging technologies, with an emphasis on Cu/SiO₂ hybrid bonding and Cu-Cu bonding for 3D integration. He has collaborated with the Industrial Technology Research Institute (ITRI) on interconnect reliability and metrology development. In this presentation, he will discuss the thermal deformation behavior of fine-pitch Cu/SiO₂ hybrid bonding structures, characterized using variable temperature atomic force microscopy (VT-AFM). His work highlights the critical role of CMP-induced topography in ensuring thermal-mechanical reliability for next-generation 3D IC packaging.

Abstract:
As the demand for ultra-high-density 3D integration and chiplet-based system architectures continues to escalate, hybrid bonding has emerged as a key enabler for fine-pitch vertical interconnects. Copper (Cu) and silicon dioxide (SiO₂) are commonly used materials in these bonding structures due to their excellent electrical and mechanical properties. However, the inherent mismatch in their coefficients of thermal expansion (CTE) poses significant challenges in maintaining interfacial planarity and structural reliability under thermal stress. Moreover, when Cu interconnects are fabricated using damascene processes and embedded within dielectric matrices, precise control over surface topography—particularly dishing—is critical for ensuring robust bonding performance.
In this study, we present a comprehensive evaluation of thermal expansion behavior in fine-pitch Cu/SiO₂ hybrid bonding structures fabricated through a damascene process. The test samples consisted of 2 µm Cu pads with a 4 µm pitch, planarized using an optimized chemical mechanical planarization (CMP) process to control Cu dishing depth to less than 5 nm. Such strict dishing control is necessary to satisfy bonding surface requirements.
To investigate the thermal deformation characteristics of these structures, we employed variable temperature atomic force microscopy (VT-AFM), a nanoscale metrology tool capable of measuring surface expansion with sub-nanometer resolution under elevated temperatures. Each sample was subjected to two thermal cycles from room temperature to 200 °C and then cooled down to room temperature, simulating thermal loading conditions typically encountered during hybrid bonding and subsequent packaging processing steps.
VT-AFM measurements revealed that the damascene-embedded Cu pads exhibited a repeatable out-of-plane expansion of approximately 2–3 nm during each thermal cycle. Importantly, the degree and uniformity of expansion were closely correlated with local CMP outcomes: Cu pads with smoother and more uniform surfaces showed stable and symmetric expansion behavior, while those with slight dishing non-uniformities developed localized bulging or asymmetric deformation. These effects are primarily attributed to the CTE mismatch between Cu and SiO₂, which introduces differential stress at the interface—especially in regions where surface planarity is compromised.
The results highlight the importance of not only achieving sub-5 nm dishing control during CMP but also validating the thermal-mechanical behavior of the Cu/SiO₂ system using temperature-resolved surface metrology. Our findings show that even minor variations in surface topography can translate into measurable thermally induced distortion, which may influence bonding alignment accuracy and long-term reliability in 3D packaging applications.
This work demonstrates a systematic approach for assessing fine-pitch hybrid bonding readiness by combining advanced planarization control and VT-AFM-based thermal analysis. The integration of these techniques provides a powerful methodology to both ensure and validate the structural integrity of Cu/SiO₂ hybrid bonding interfaces. These insights will be critical for the development of next-generation 3D IC packaging platforms where ultra-fine pitch and sub-nanometer flatness are essential.

 

Bio:
Joonho You is currently the CEO of Nexensor Inc. He studied optical metrolgoy at KAIST (Korea Advanced Institute of Science and Technology) and has over 20 years of experience in research, development, and commercialization in this field. His research interests include interferometry technology, thin-film measurement technology, shape measurement techniques using pattern projection methods such as deflectometry and Moiré, and fiber optic-based thickness sensors. He is the member of The Korean Microelectronics And Package Society and Korean and Optical Society of Korea

Abstract:
This study introduces a hybrid metrology technique that integrates Phase Shifting Interferometry (PSI), a well-established optical measurement method, with Active Probe-based Atomic Force Microscopy (AP-AFM). PSI is widely used for precise characterization of surface features such as roughness, step heights, and refractive index distributions in both research and industrial semiconductor applications. The technique offers several key benefits, including nanometer-level vertical resolution, high throughput, non-contact operation, and full-field imaging, making it an essential tool in wafer-scale process control. Notably, it plays a central role in Chemical Mechanical Polishing (CMP) quality assessment, where surface defects such as dishing and erosion must be rigorously monitored.

However, while PSI excels in many respects, its measurement performance can be significantly degraded by a range of error sources. These include phase-shift inaccuracies due to mechanical or environmental instabilities, susceptibility to external vibrations, non-linearity in detector response, parasitic reflections within the optical path, digital quantization noise, laser frequency instability, and fluctuations in illumination intensity. These error mechanisms become particularly problematic when inspecting topographies involving spatially varying refractive indices or complex multilayer structures, which are increasingly common in advanced semiconductor packaging and interconnect schemes.

To address these fundamental limitations, we propose a synergistic approach that combines PSI with Atomic Force Microscopy. Specifically, we adopt an AFM architecture based on integrated active probes (APs), which circumvent the need for conventional Optical Beam Deflection (OBD) systems. The OBD approach, while effective in many standalone AFM systems, introduces bulky optics that make co-integration with PSI impractical, particularly in constrained wafer metrology environments. In contrast, the AP-AFM technology developed by nano analytik GmbH utilizes MEMS-based cantilevers equipped with integrated piezoresistive sensors for displacement readout and built-in actuation capabilities. This design dramatically reduces system complexity and size, enabling seamless integration with optical metrology setups.

The active probes feature highly durable tip materials such as gallium nitride (GaN) and diamond, ensuring long operational lifetimes and the ability to sustain atomic-resolution imaging over extensive usage. These properties are critical for semiconductor process control, where both high resolution and probe robustness are necessary to minimize downtime and ensure consistency in measurement performance. Importantly, AFM's imaging fidelity is unaffected by optical refractive index variations in the sample, making it a powerful complement to PSI for heterogeneous material systems.

This integrated metrology platform effectively combines the fast, wide-area scanning capabilities of PSI with the ultra-high-resolution, localized measurement power of AFM. It provides a unique pathway to real-time, traceable inspection workflows capable of resolving nanometer-scale surface features across large fields of view. This dual-modality system opens new possibilities in semiconductor fabrication, including advanced CMP process tuning, defect localization and classification, and 3D interconnect metrology. Furthermore, the approach has potential applicability in other precision manufacturing sectors where both speed and atomic-scale accuracy are simultaneously required. By leveraging the complementary strengths of optical and mechanical measurement techniques, the proposed hybrid system represents a significant advancement in next-generation metrology for nanotechnology and beyond.

 

Bio:
Heng-Ching Mie is a PhD student from Mizuno Lab at the Semiconductor Academy, National Cheng Kung University. His research focuses on advanced packaging, interfacial adhesion, Through-Glass Via (TGV) reliability, and hybrid bonding. The lab collaborates with industry partners to develop innovative solutions for next-generation heterogeneous integration.

Abstract:
SiO2 is widely used as a dielectric layer in the heterojunction process due to its excellent compatibility with silicon-based semiconductor and insulating properties. However, the significant mismatch in the coefficient of thermal expansion (CTE) and mechanical strength with copper give rise to several reliability issues such as wafer flatness issue and interface reliability during Cu/SiO2 hybrid bonding process [1, 2]. With the ongoing trend toward device miniaturization and higher operating temperature the mentioned issue became more critical [3]. When the processing temperature is concerned, SiO2 further demonstrates its disadvantage.
In this study, we investigated Cu/dielectric hybrid bonding using polyimide (PI) as the dielectric layer, employing various surface treatments, including citric acid and O₂ plasma treatments, to enhance bonding performance. The effects of surface treatments were investigated through comprehensive surface characterization, including surface morphology analysis via atomic force microscopy (AFM) and contact angle measurements. Chemical composition analysis are done by X-ray photoelectron spectroscopy (XPS) investigating. Final mechanical property is accessed through shear strength testing with the DAGE SERIES 4000PXY system.
The study demonstrates that the shear strength of PI/PI interfaces is primarily governed by surface roughness. When high-energy O₂ plasma interacts with the PI surface, ion bombardment induces significant changes in surface topography, thereby increasing the effective contact area. However, excessive roughness leads to the formation of interfacial voids, which severely deteriorate the bonding strength. Notably, at comparable levels of surface roughness, samples treated with 50 W plasma exhibit higher shear strength, attributed to enhanced surface hydrophilicity. This is supported by both XPS spectra and contact angle measurements: the 50 W treated samples display a greater degree of hydrophilicity compared to those treated at 30 W. Specifically, the 50 W treatment results in an increased concentration of carbonyl oxygen species, and a corresponding reduction in contact angle when measured with deionized water.
Regarding citric acid treatment, although citric acid has no significant effect on chemical composition of PI as others suggested, the removal of copper oxide, which will severely effect the bonding strength, have found to be very effective. After citric acid treatment, XPS spectrum show that Cu-O bond has nearly disappeared and a near 98% of Cu is presented on the surface, giving a suitable condition for Cu-Cu direct bonding.
Under optimized bonding conditions (225 °C, 44.4 MPa), a shear strength of approximately 19 MPa was achieved for pure PI/PI bonding with appropriate O₂ plasma treatment. Under the same bonding conditions, Cu pillar embeded samples treated with O₂ plasma and citric acid achieved a shear strength of approximately 20 MPa. Demonstrating the effectiveness of surface treatment strategies in enhancing the reliability of Cu/PI hybrid bonding.

 

Bio:
Chih-Chi Tsai is a Ph.D. student in the Department of Materials Science and Engineering at National Yang Ming Chiao Tung University, Taiwan. She is a member of the Advanced Packaging Laboratory, supervised by Prof. Chih Chen. Her research focuses on co-electrodeposition processes, including electromigration and grain growth mechanisms in electroplated materials.

Abstract:
As the development of advanced semiconductor packaging continues to push the boundaries of device miniaturization and integration density, the selection of interconnect materials with high electrical conductivity, mechanical strength, and thermal reliability becomes increasingly critical. Nanotwinned copper (NT-Cu) has emerged as a promising interconnect candidate due to its high twin boundary density, superior electromigration resistance, and enhanced thermal stability. In particular, the presence of coherent twin boundaries in highly <111>-oriented NT-Cu structures is known to significantly retard grain boundary diffusion while maintaining low resistivity. However, thermal annealing during backend processing may lead to undesired grain growth and twin coarsening, which deteriorate the beneficial nanostructure and reduce long-term device reliability.
To address these challenges, this study explores the influence of various transition metal dopants on the annealing behavior of electroplated NT-Cu films. Specifically, iron (Fe), cobalt (Co), nickel (Ni), and manganese (Mn) were selected as dopants due to their differing atomic radii and diffusivity in Cu matrices. All dopants were introduced into the plating bath at a concentration of 0.05 M. The electrolyte was prepared using copper sulfate pentahydrate (CuSO₄·5H₂O, 0.5 M), sulfuric acid (H₂SO₄, 100 g/L), hydrochloric acid (HCl, 30 ppm), and a commercial organic additive (108C, 45 mL/L). The co-electroplating processes were carried out at room temperature using direct current (DC) with a current density of 6 ASD for 300 seconds. A Ti diffusion barrier and 200 nm Cu seed layer were first deposited on 4-inch silicon wafers to ensure good adhesion and uniform nucleation.
Following deposition, thermal annealing was performed in a quartz tube furnace under high vacuum (10⁻³ Torr). Three annealing conditions were investigated: (1) 230°C for 3 hours, (2) 300°C for 1 hour, and (3) 350°C for 1 hour. The evolution of grain morphology and twin density was examined using focused ion beam (FIB), scanning electron microscopy (SEM), and electron backscattered diffraction (EBSD). Our goal was to assess how each dopant influences grain growth kinetics, twin formation, and microstructural stability at elevated temperatures relevant to Cu-Cu bonding and fine-pitch hybrid interconnects.
The results indicate distinct behaviors among the different dopants. Fe, Co, and Ni additions all promoted noticeable grain growth even at the lower annealing temperature of 230°C. At 300°C and 350°C, these doped films exhibited large, coarse grains with diminished twin boundaries, implying a loss of the desired nanostructure. These changes were attributed to enhanced atomic mobility facilitated by the dopants, which accelerated recrystallization and grain boundary migration. In contrast, Mn-doped Cu films maintained a relatively stable fine-grained structure under the same conditions. Even after annealing at 350°C, Mn addition suppressed abnormal grain growth and preserved a portion of the twin boundary network, suggesting an inhibitory effect on grain boundary movement and dislocation activity.
This study has demonstrated that different transition metal dopants significantly influence the annealing behavior and grain growth kinetics of electroplated NT-Cu films. Building on these findings, future work will aim to harness dopant-induced microstructural effects to enhance Cu–Cu bonding quality. In particular, we plan to investigate whether grain growth across the bonding interface can be achieved through low-temperature annealing, thereby improving interfacial strength and reliability. To this end, three key directions will be pursued: (1) optimizing annealing parameters at reduced temperatures to promote grain boundary migration across Cu–Cu interfaces; (2) correlating interfacial microstructure with bonding strength through mechanical testing and cross-sectional analysis; and (3) exploring novel additives or process modifications to enable robust bonding under tighter thermal budgets. Through these efforts, we aim to develop a more reliable low-temperature Cu–Cu bonding strategy that supports the demands of next-generation fine-pitch interconnects and advanced packaging technologies.

 

Bio:
From: Department of Materials Science and Engineering, NYCU Advisor: Prof. Chih Chen Research direction: Cu/SiCN hybrid bonding

Abstract:
The growth of artificial intelligence (AI) and 5G networks drives the need for finer interconnect pitch at both wafer and die levels. Hybrid bonding stands out as a key technology to meet this demand, enabling high performance, greater efficiency, and reliable signal transmission for advanced semiconductor integration. Hybrid bonding involves the direct bonding of dielectric pads followed by annealing of Cu vias. The recess of copper and dielectric pads needs to be well-controlled. The roughness of both copper pads and dielectric pads are crucial for the bonding process. To meet the bonding requirements in morphology and surface roughness, we adopted chemical mechanical planarization (CMP) as the surface planarization method.

One of the focuses of this study is to optimize the CMP process by tuning the relative removal rates of the Cu, barrier, and bonding dielectric layer. By adjusting the slurry pH, we were able to control the selectivity between these materials. In addition, dilution of the slurry concentration is employed to more specifically control the polishing rate. Achieving a well-balanced removal rate among these materials is essential to minimize recess depth and ensure uniform planarization across the bonding interface.

Currently, Cu/SiO2 hybrid bonding is the most widely adopted and well-researched technology. However, we selected silicon carbon nitride (SiCN) as the bonding dielectric due to its superior properties, including higher bonding strength, void suppression capability, and effectiveness as a copper diffusion barrier. Additionally, nanotwinned copper (NT-Cu) was used as the metal pad material owing to the high surface diffusivity, low oxidation rate, and high strength compared to conventional Cu. Most of all, the higher coefficient of thermal expansion (CTE) can tolerate slightly larger recess depths without compromising bonding quality.
The thermal expansion behavior of copper pads embedded within dielectric vias plays a crucial role in achieving bonding integrity during the thermal annealing process. Both in-situ and ex-situ heating atomic force microscopy (AFM) measurements were performed to characterize the surface profiles to examinate the coefficient of thermal expansion.
This study provides a more comprehensive understanding with direct evidence of the Cu/SiCN hybrid bonding mechanism.

 

Bio:

M.S., Chemical Engineering, National Tsing Hua University
Ph.D., Materials Science, National Chiao Tung University

Abstract:

Types and Applications of Advanced Packaging Materials
 - Key materials: Substrates, RDL dielectric materials, molding films, underfills, and thermal interface materials (TIMs)
 - Functional and technical requirements evolving with heterogeneous integration and high-frequency, high-speed applications
The Role of Substrate Technologies in Advanced Packaging
 - Applications of high-density substrates in CoWoS, InFO, FOPLP platforms
 - Challenges in fine-pitch design, substrate thinning, multilayer structuring, and panel-level scaling
Technical Challenges and Innovation Opportunities in Molding Films
 - Key issues: Flow control, stress management, and long-term reliability
 - Innovation directions: Low-temperature curing, filler dispersion, and ultra-thin film design
Key Entry Points and Strategies for Material Localization
 - Current dependency status of Taiwan’s material supply chain
 - Potential entry points and opportunities for local suppliers
 - Strategic pathways to build a resilient domestic supply chain through partnerships and innovation

 

Bio:
Shubhayan Mukherjee is a senior Ph.D. candidate at the Department of Materials Science and Engineering, National Cheng Kung University (NCKU), Taiwan. His research centers on understanding the fundamental mechanisms governing phase stability, lattice deformation, and defect evolution in intermetallic compounds and metallic systems under electric fields. Using in-situ synchrotron-based techniques such as SR-XRD and SR-XND, he investigates early-stage structural instabilities driven by electric current, aiming to decouple thermal and field-induced effects at the atomic scale. His work spans FCC metals like Cu and Au, as well as intermetallic phases, contributing to a deeper physical understanding of electromigration and current-induced plasticity beyond conventional reliability studies.

Abstract:
In advanced packaging platforms designed for AI acceleration, high-frequency computing, and high-power PCB systems, the structural integrity of metallic interconnects under extreme current density is a critical reliability concern. Subtle lattice-level instabilities can emerge long before visible failure, demanding advanced characterization tools for early detection. Electromigration (EM) in Cu, Ag, Au, and Al interconnects has been extensively studied. Classical work by Huntington and Grone first established the mechanism, showing that momentum transfer from conducting electrons drives directional atomic diffusion and void formation [1]. Blech later demonstrated that such mass transport induces stress accumulation in thin films [2], while Conrad and co-workers found that electric current pulses can reduce flow stress and alter dislocation behavior, providing evidence of electroplastic (EP) effects [3,4]. More recently, Liu et al. employed synchrotron radiation-based characterization to probe current-induced lattice deformation in Cu and Al interconnects, revealing strain evolution prior to morphological failure [5,6]. However, the onset of irreversible lattice deformation in Au interconnects under comparable electrical stress remains largely unexplored. Owing to its exceptional conductivity and corrosion resistance, Au is widely used in high-density PCBs and wire bonding and is increasingly deployed in fine-pitch substrates and embedded power modules for high-performance computing systems, making its structural stability under high current density a pressing concern for next-generation packaging technologies.
We conducted in-situ synchrotron radiation-based X-ray diffraction (SR-XRD) measurements on pre-annealed FCC Au strips (3 μm × 16 μm × 2 cm) to investigate their structural response under electric current stressing (ECS). Experiments were performed at beamline TLS BL17B1 (NSRRC), where samples were subjected to electric current densities ranging from 4.2 × 105 A/cm2 to 1.25 × 106 A/cm2 for 30 min. Diffraction peak tracking during stressing enabled high-resolution monitoring of lattice parameter evolution. For comparison, control heating experiments up to 190 °C, as observed during ECS due to the Joule heating effect, were carried out at both TLS BL17B1 and BL01C2 under identical thermal profiles but without current.
A distinct threshold was identified near ~1.04 × 106 A/cm2, beyond which the (111) reflection exhibited irreversible lattice expansion as shown in Fig. 1. In contrast, thermal-only experiments revealed no such peak shifts, confirming that the observed lattice deformation originated from the electron wind force rather than Joule heating. The d-spacing increase was crystallographically anisotropic, indicating directional stress accumulation along specific lattice planes. Furthermore, the d-spacing shift persisted even after post-stressing thermal recovery, a condition representative of high-cycle thermal loading in AI and server environments, indicating irreversible lattice distortion instead of purely elastic strain.
These results are consistent with our previous studies on Cu and Al, where a critical lattice strain (~0.008) correlated with the onset of electromigration-induced plasticity [6]. However, unlike Cu, which demonstrated twinning and slip deformation under elevated current density [5], the Au strips showed no evidence of phase transformation or surface hillocking throughout the measurement period. This highlights the distinct structural response of Au interconnects under high current stress.
By effectively decoupling thermal and electric field effects, the present methodology establishes a direct route to quantify early-stage lattice instability in metallic conductors. These findings support a generalized framework in which current-induced lattice strain, rather than observable damage, enables early-stage identification of sub-critical deformation in FCC metals, providing valuable insight for the design of thermally and electrically robust interconnect materials in next-generation AI, HPC, and 3D-IC packaging systems.

 

Bio:
Ph. D Program of Mechanical and Aeronautical Engineering, Feng Chia University, Taichung, Taiwan

Abstract:
Substrate materials play a critical role in influencing the warpage behavior, thermal performance, electrical characteristics, and overall reliability of power modules [1–6]. Among these factors, warpage is particularly critical, as it directly impacts alignment accuracy, manufacturing yield, and long-term reliability [7–10]. Among the various ceramic substrates, active metal brazed (AMB) types are widely employed in high-power packaging applications due to their excellent reliability and bonding strength. However, the annealed copper (Cu) layers (ACLs) in AMB substrates are susceptible to significant plastic deformation, primarily due to recrystallization that occurs during high-temperature bonding. This process leads to grain growth and increased slip activity, resulting in reduced yield strength and enhanced ductility [11–12].
While previous studies have examined various structural and thermal effects, the influence of ACLs plasticity in AMB ceramic substrates on the process-induced warpage of power modules remains underexplored [13–16]. To address this gap, this study investigates the plastic deformation effect of ACLs in AMB substrate on the warpage behavior of a three-phase, full-bridge silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module during manufacturing, using nonlinear numerical modeling and experimental validation. A three-dimensional (3D) process modeling methodology is developed to accurately characterize the process-induced warpage. This approach incorporates ANSYS element birth–death technique and a nonlinear finite element analysis (FEA) model, explicitly accounting for the nonlinear plastic deformation of the ACLs and geometric nonlinearities. Furthermore, the effect of vacuum suction during the wire bonding process is included. The effectiveness of the proposed process modeling methodology is confirmed through in-line warpage measurements taken at key process steps. At last, comparative analysis is conducted to evaluate differences in warpage behavior with and without ACLs plasticity modeling.
The three-phase, full-bridge SiC MOSFET power module under investigation is shown in Figure 1, and the corresponding FEA model used for process modeling is presented in Figure 2. The stress–strain curves applied to the ACLs are illustrated in Figure 3 [16]. The measured and simulated warpage values before and after the die bonding process, after wire bonding, and after heat sink attachment are shown in Figures 4(a) and 4(b), respectively. It should be noted that all results, except those after heat sink attachment, represent the warpage distribution across the AMB substrates. Once the heat sink is attached to the AMB substrate, the measured and simulated warpage data reflect the combined deformation across both the heat sink and the AMB substrate. It is evident that the simulated warpage results closely match the experimental data, both in trend and in magnitude, demonstrating the validity of the proposed process modeling methodology.
Figure 5 exhibits the measured and simulated warpages of the AMB substrate with and without the plasticity effect during the die bonding (i.e., Steps 0–3) and wire bonding (i.e., Steps 3–6) processes. As noted earlier, the warpage results after heat sink attachment are not included in this figure due to the difficulty in isolating the warpage contributions of the AMB substrate and the heat sink. The simulation results reveal a noticeable difference in warpage behavior depending on whether the plasticity of the ACLs is considered. Incorporating the plasticity effect of the ACLs turns out to significantly improve prediction accuracy, underscoring the importance of accounting for their post-annealing mechanical response in reliable warpage modeling.

 

Bio:
Masahiro Inoue is an associate professor at the Graduate School of Science and Technology, Gunma University, Japan. His current research focuses on characterizing and applying novel electrically and thermally conductive pastes. He also develops novel human/machine interfaces using stretchable wiring technology.

Abstract:
INTRODUCTION
Flexible hybrid electronics (FHE) are expected to be a valuable technology for realizing advanced electronic devices in the Internet of Things (IoT) society. The research and development of advanced FHE devices have expanded the concept of “flexibility” to include stretchability beyond conventional bendability. The constituent elements, such as substrates, wires, and electrodes, must exhibit extensive stretchability to achieve stretchable devices; therefore, material development and reliability assessment for stretchable electric circuits are essential to establishing the electronics packaging technology for FHE devices.
Among the packaging techniques for preparing stretchable wires and electrodes, printing methods using elastomer-based electrically conductive pastes have several advantages from the viewpoint of High-mix, low-volume production with low cost. However, the wires and electrodes exhibit severe problems with electrical reliability when they undergo mechanical deformation. Because the conduction paths in the wires and electrodes printed with the conductive pastes are formed in a network of fillers, conducting contacts between fillers are easily deformed to increase their electrical resistivity. Thus, improving electrical reliability is a crucial issue for the widespread adoption of this fabrication process.
Since the problems in the electrical reliability of the wires are caused by their deformation, this work focuses on analyzing the electrical behavior of the stretchable wires during a uniaxial cyclic tensile test to improve the stability of electrical conductivity. In this work, the material design of conductive pastes for printing on substrates with extremely low hardness is discussed. One of the proposed design concepts aims to stabilize electrical conductivity by controlling viscoelasticity in the wires.
MATERIALS AND METHODS
Silver flakes and micro-particles (Fukuda Metal Foil & Powder Co., Ltd., Kyoto, Japan) were mixed with polyhydroxyurethane (Dainichiseika Color & Chemicals Mfg. Co., Ltd., Tokyo, Japan) at up to 80 wt% to prepare pastes for printing stretchable wires. The wire samples, with dimensions of 5 mm × 40 mm × 30 μm, were printed on polyurethane-based substrates with an Asker hardness (C) of 15. After printing, the specimens were cured at 100 °C for 1200 s.
A uniaxial cyclic tensile test with 10 % strain amplitude of the wire samples was performed for 100 cycles at a strain rate of 2.5 × 10-1 or 2.5 × 10-3 s-1. Subsequently, a stress relaxation test was conducted after the cyclic tensions. Variation in the electrical resistivity of the wires was simultaneously measured during the tensile test.　After the tensile test, the samples were post-annealed at 100 °C. Subsequently, the electrical resistivity of the post-annealed samples was measured.
RESULTS
The sample printed on a 15-hardness substrate exhibited a specific electrical behavior when an appropriate level of viscoelasticity was imparted to the wire sample. The electrical resistivity initially increased and decreased in the first loading step. However, increased electrical resistivity was suppressed in the subsequent unloading step. Furthermore, the electrical resistivity decreased, approaching a constant range as the number of cycles increased.
The electrical behavior observed in the sample printed on the 15-hardness substrate suggests that the sample's viscous relaxation plays a crucial role in suppressing the increased electrical resistivity during the unloading steps. The mechanism of this electrical behavior remains unclear. However, this suggests that the conducting filler network (conduction paths) in stretchable wires can be stabilized by mechanical deformation under specific conditions, thereby improving their electrical reliability. Based on the experimental results, stretchable wires that exhibit little variation in electrical resistivity have been successfully developed.

 

Bio:
1. Major in Chemical Engineering & Materials Science at Yuan Ze University. 2. Research expertise: mmWave antenna, 3D electromagnetic simulation. 3. Y. H. Chang, Y. C. Chiang, C. C. Huang, C. C. Huang, C. H. Chou, and C. E. Ho, Comparative Study between Single and Array Antenna Characteristic with Different Surface Finishes, Proceeding of the 19th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2024), Taipei, pp. 299–302, Oct. 23–24, 2024.

Abstract:
Millimeter-wave (mmWave) antennas are now being widely used in automotive radar system, low earth orbit (LEO) satellites, and wireless data center due to their capability for higher bandwidth, lower latency, and better spatial resolution. Several critical factors must be taken into account in the mmWave antennas design, which includes signal characteristic, lightweight, low-cost fabrication and so on. The microstrip structure, consisting of two parallel conducting layers separated by a dielectric substrate with the upper conductor patterned on the substrate surface for radiation, can appropriately meet the above requirements, therefore promoting its widespread adoption in mmWave antenna design. However, a portion of Cu traces in the microstrip structure are inevitably exposed to the ambient environment during operation and the Cu constituent easily reacts with atmospheric oxygen.

In high-frequency signal transmission, electromagnetic losses may cause temperature rise, which further accelerates the Cu oxidation process, leading to the formation of cuprous oxide (Cu2O) and copper oxide (CuO) layers over the Cu surface. In this study, the XPS depth profiling of the microstrip Cu traces revealed noticeable oxidation after annealing at 150 °C for 24 h and 48 h under 1 atm. The predominant oxide formed was identified as Cu2O, with oxide layer thicknesses exceeding approximately 200 nm and 1000 nm after 24 h and 48 h of aging, respectively, based on the Cu 2p and O 1s signals. The 2D radiation patterns (77 GHz) of a mmWave antenna after annealing at 150 oC for 0 h (initial), 24 h, and 48 h. Obviously, the gain value of mmWave antenna gradually decreased from 10.1 dBi (0 h), to 8.8 dBi (24 h), and then to 7.7 dBi (48 h) in the yz-plane. The degrdation in the antenna’s gain value can be attributed to its lower bulk conductivity (10⁻²–10⁻³ S/m) than Cu (5.87 × 107 S/m). Our preliminarily results revealed that the Cu oxidation is an important factor of antenna performance, and an appropriate surface finish coating might be required in order to enhance the thermal/transmission reliability of mmWave antennas.

 

Bio:
Professor Nogita graduated as an Engineer in Japan in 1990 and worked in the nuclear power industry with Hitachi Ltd. He was awarded a PhD from Kyushu University in 1997. He migrated to Australia in 1999 after accepting a position at the University of Queensland, where he became the founding director of the Nihon Superior Centre for the Manufacture of Electronic Materials (NS CMEM) in 2012 as well as project manager of the University of Queensland – Kyushu University Oceania project (UQ-KU project) at the School of Mechanical and Mining Engineering. He is also an invited Professor at Kyushu University and a Research Adviser at the University of Malaysia Perlis. His research is in three major areas, namely lead-free solders and interconnect materials, energy materials such as hydrogen-storage alloys, and structural and coating alloy development. He holds 20 international patents and has authored over 250 refereed scientific papers. He is a deputy chair for the Electronic Packaging and Interconnection Materials (EPIM) Committee (since 2022), and Leading organiser (2019 and 2023) and Co-organiser of the “Emerging interconnect and Pb-free materials for advanced packaging technology” symposium at TMS in the USA, from 2015 to the current date. He is the recipient of the TMS Research to Industrial Practice Award in 2021.

Abstract:
This paper provides an overview of how advanced characterisation approaches, such as Synchrotron X-ray radiation facilities and state-of-the-art electron microscopy, can be used to optimise and develop Pb-free solder alloys and associated intermetallics that form between the solder alloys and substrates of electronic interconnects. The following two practical/experimental advanced approaches will be discussed, along with their use in international collaborative projects, (1) Synchrotron X-ray imaging at the SPring-8 synchrotron, and (2) State-of-the-art electron microscopy at The University of Queensland and Kyushu University.

 

Bio:
Department of Materials Science and Engineering, National Chung Hsing University, Taichung 402, Taiwan

Abstract:
Direct Cu-to-Cu bonding applied in 3D IC packaging exhibits many advantages, such as higher I/O density, better thermal dissipation and faster signal transportation. It also contributes to low electrical resistance and low insertion loss as well, which are beneficial to electrical performance for packages. This study applies ensemble learning, which is one of the machine learning techniques, to develop a predictive model for bonding strength. By integrating experimental data such as oxide layer thickness and constitutional phases, the modeldeveloped enables accurate prediction of shear strength of Cu-to-Cu joints under various oxidation conditions, and can be further utilized for rapid screening of process parameters and evaluation of joint reliability.To provide high-quality experimental data and enhance the generalizability of the model, oxide layer data generated from various processing methods, including thermal annealing and vacuum ultraviolet (VUV) exposure, were incorporated into the training set. The measurement of oxide thicknesses and also phase identification were performed using coulometric reduction.

Keywords: Cu-to-Cu direct bonding, pre-treatment, machine learning

 

Bio:
Educational background： National Kaohsiung University of Science and Technology. The Master's Degree in Mechanical and Automation Engineering National Kaohsiung University of Science and Technology. The Doctoral Program in Engineering Technology at the College of Engineering(Not graduated) Experience: Advanced Semiconductor Engineering, Inc. Process Engineer of the Engineering Department Advanced Semiconductor Engineering, Inc. CRD Group Equipment Development Divison Project Engineer

Abstract:
The IC packaging is widely applied in semiconductor electronic CoWoS and automotive electronic products. Microwave plasma must be used to treat the surfaces of chips and substrates in advanced packaging. FCBGA products require plasma cleaning either before W/B or before molding. The main goal is to improve the adhesion between the substrate and the Die, and to have a uniform cleaning capability while ensuring good bonding reliability between the substrate and wire bond.

To enhance the reliability of CoWoS products following plasma treatment, it can improve the W/B adhesion. The copper wire can be soldered to the surface of the substrate and Die, and improve hydrophilic properties. In the semiconductor packaging with RF and MW Plasma, RF Plasma is a direct contact method that generates the heat in products and easily causes burning issues. However, MW Plasma is a non-contact method which is more suitable for processing substrates that W/B products already had applied.

The main purpose is to improve the existing issue of the Plasma which is not adhering to the substrate. We had used the Taguchi design of experiments method (L18). The material is FCBGA 95x240 mm substrate. We use water droplet angle data to confirm the cleaning effect!
Change the product from a 5-layers stacked position to a 10-layers mode, and confirm it through relevant experiments, including the spacing between the 5-layers shelves. Preliminary tests show that the reduced spacing can still achieve a cleaning effect. It can pass Cpk process capability and quality control inspection. The target characteristic of the Taguchi method is to achieve a contact angle of 20±5 degrees for water droplets, and to arrange the relevant factors to investigate the effect of Plasma on the surfaces of products at 5 layers and 10 layers.

This research has found that the low vacuum can result in better cleaning effects and welding capabilities. For the different parameters combined with vacuum, the cleaning capability of 10-layer boards is the same as that of 5-layer boards. It can meet the target value of 20±5 degrees and achieve a capability of Cpk>1.67. By using the Taguchi method orthogonal table L18 (21x37) to configure parameter combinations, it bases on the orthogonal table design and perform the drop angle measurement on the production line. To confirm its cleaning capability range <37 degrees, the optimal parameters for the 10-layer boards rack design by the experimental design can significantly improve UPH and Cpk to above 1.67!

Key words: Microwave High Frequency Plasma, Plasma Cleaning, Taguchi Design Experimental Method, Nominal-The-Best, NTB

 

Bio:
“Kuo-Hua Heish is a senior quality technical professional and working for electronic and telecommunication companies for more than 20 years. He is widely regarded as the go-to source on process integration, development, failure analysis and customer engagement for any technical and quality improvements. Additionally, Kuo-Hua is very keen on new material survey and application tests, especially in Heterogeneous Integration for product reliability improvements. With his quality and process improvement experiences, now is leading a process development team in WNC for advanced manufacturing process development and settlement. He is also willing to share, being a tutor for the industry-academia collaboration, invited to speak to organizations and universities in Taiwan.

Abstract:
The traditional underfill process typically requires defluxing/cleaning process to remove flux residues, ensuring the reliability of subsequent packaging. However, with the increasing awareness of environmental protection and the growing demand for process simplification, no-clean underfill technology has become an important focus in the industry. This technology eliminates the needs for chemical and water cleaning associate to energy consumption, which not only enhances production efficiency and reduces manufacturing costs but also significantly lessens environmental impact. The core of no-clean underfill technology lies in low residue fluxing process optimization, allowing for minimal or negligible flux residue during the reflow process, thereby eliminating the need for post-reflow cleaning while maintaining the mechanical strength and reliability required by conventional underfill processes.
In this study, two types of ultra-low residue flux materials were evaluated combining with normal underfill adhesives and flux compatible claimed underfill. The ultra-low residue flux was applied to the packaged components through a dipping process, followed by bottom fill technology for adhesive filling without any flux cleaning. Subsequently, multi-reflows and thermal cycling tests were conducted to assess such non-clean underfill process and material reliability. The results indicate that combining ultra-low residue fluxes with traditional underfill adhesives, or pairing them with flux compatible underfill adhesive, all successfully achieve a no-clean underfill process and pass 3X multi-reflow and 3000 cycles of thermal cycling testing.

 

Bio:
Danny Chang is a semiconductor process graduate student at National Yang Ming Chiao Tung University and an equipment engineer at GlobalWafers. With a background in materials science and dual master's degrees in semiconductor processing and business management, he has hands-on experience in wafer polishing systems, defense manufacturing projects, and product development. Danny combines engineering expertise with strong project execution skills, making him a versatile contributor in high-tech industries.

Abstract:
This study investigates the influence of pre-heating treatment on the electromigration (EM) reliability of flip-chip micro bump, with the objective of improving the lifetime of interconnects in advanced semiconductor packaging. Electromigration is a critical reliability concern in microelectronic micro bump, as the migration of metal atoms under high current densities can lead to void formation, resistance increase, and eventual interconnect failure. This research explores whether thermal pre-treatment, which promotes intermetallic compound (IMC) formation, can enhance the resistance to electromigration-induced degradation.
The experimental methodology involved preparing several flip-chip micro bump test samples under different thermal and electrical stress conditions. The pre-heating treatment was carried out at 210°C for either 5 or 15 minutes, and the electromigration stress was applied at 0.75 A and 150°C. Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDS) were used to analyze the microstructural and compositional changes in the micro bump post-testing.
Five key sample groups were analyzed:
1. Sample (1): No pre-heating or EM applied. This served as the baseline for material composition.
2. Sample (2): Pre-heated at 210°C for 15 minutes without EM. This group allowed for the observation of IMC growth (primarily Cu₆Sn₅) due to thermal treatment alone.
3. Sample (3): No pre-heating, subjected to EM at 0.75 A and 150°C. This sample failed after approximately 480 hours, showing a 16.2% increase in resistance.
4. Sample (4): Pre-heated at 210°C for 5 minutes and then exposed to EM under identical conditions. This sample exhibited extended EM life (approximately 720 hours) and a lower resistance increase of 11.3%.
5. Sample (5): Pre-heated at 210°C for 15 minutes followed by EM. This sample failed more rapidly (240 hours) with a resistance change of only 2.8%, suggesting that excessive IMC formation may introduce brittleness or stress concentrations that negate the benefits of pre-treatment.
The results demonstrate that moderate pre-heating (5 minutes at 210°C) can effectively enhance the EM performance of micro bump by forming a stable IMC layer that inhibits atom migration. However, overexposure to thermal treatment (15 minutes) may result in excessive IMC formation, which can degrade mechanical integrity and reduce EM lifetime. Therefore, optimizing pre-heating parameters is crucial for achieving reliable interconnects in flip-chip packaging.
This study contributes valuable insights into the materials engineering of micro bump in advanced packaging applications and supports the hypothesis that controlled thermal treatment prior to EM exposure can be a viable method to enhance reliability. Further research should explore the mechanical stress profiles and microstructural evolution in more detail to refine the pre-conditioning strategies for mass production environments

 

Bio:
T. Y. Ouyang received a Ph.D. degree in physics from National Taiwan University, Taiwan, in 2015. He was a postdoctoral fellow with the Center for Condensed Matter Sciences (CCMS), Taiwan, from 2016 to 2018. He is currently a senior engineer at the Industrial Technology Research Institute (ITRI).

Abstract:
A scalable via array substrate is manufactured and enables the provision of small-volume, large-variety production packaging producibility evaluation. This scalable via array substrate is comprised of pre-fabricated redistribution layers and customized redistribution layers. The pre-fabricated redistribution layers have consisted of four-metal levels of copper RDLs, and 180 µm height through mold vias. Dual active switch dies were embedded in the through mold vias, which act as a bridge to program and modulate the signal transmission between integrated heterogeneous chips (Bluetooth, flash memory, and microcontroller unit). With the integration of various functionality chips, we can define the routing interconnection traces using simplified 2P1M customized redistribution layers, reducing the complexity of layout design. A scalable via array substrate provides a cost-effective packaging architecture and is expected to be a promising solution for high-performance system-in-package. The pre-fabricated redistribution layers guarantee a stable manufacturing yield, shortening 50% the time-to-market and reducing the production cost.

 

Bio:
1. Name : Nam Son Park 2. Title : Professor 3. Affiliation : Tech University of korea Prof. Nam son Park is a Research Professor at Tech University of Korea (TUK) in the Semiconductor Package–PCB Center. With over 30 years of industry experience, he specializes in semiconductor packaging and advanced substrate processing. Prof. Park holds a master’s degree in Precision Mechanical Engineering from Hanyang University and is pursuing a Ph.D. in Advanced Materials Engineering at TUK. He has contributed extensively to international conferences like ISMP, ICSE, and AIS/I3S, covering topics such as plasma processing, microvia etching, and flip-chip packaging. His research focuses on next-gen packaging substrates, including glass and 2.1D substrates, and ultra-fine line/space patterning.

Abstract:
INTRODUCTION
Conventional CO₂ laser drilling combined with wet desmear processes has limitations in forming fine-pitch microvias, particularly in advanced microcircuit applications. Although ultraviolet (UV) laser drilling can produce smaller via diameters, its use is limited for build-up films (BUF) protected by polyethylene terephthalate (PET). Direct plasma exposure of the BUF can cause filler protrusion and increase surface roughness. This, in turn, necessitates thicker seed layers in the semi-additive process (SAP) and ultimately hinders the realization of fine circuit patterns.

EXPERIMENTAL METHODS
To address these limitations, we sputter-deposited 50–200 nm-thick copper (Cu) and nickel–chromium (Ni–Cr) thin films onto the BUF surface prior to nanosecond UV laser drilling. These metallization layers served as protective coatings for the BUF during the subsequent plasma desmear process. After laser drilling, a plasma desmear was performed to remove residual smear and assess the surface integrity. A 3D laser microscope was used to analyze debris and via morphology, particularly around the via openings in a 200 nm-thick sacrificial metal barrier layer (SMBL). In addition, focused ion beam scanning electron microscopy (FIB-SEM) was used to examine the quality of the microvias fabricated in the BUF under various UV laser drilling parameters.

RESULTS AND DISCUSSION
Microvias with diameters below 10 μm were successfully formed without increasing the surface roughness of the BUF, demonstrating the effectiveness of the SMBL coating. The results indicate that a metal layer thickness of at least 100 nm is sufficient to protect the BUF during both UV laser drilling and the subsequent plasma desmear. Optimized plasma desmear conditions were established to effectively eliminate residual smear while minimizing via enlargement. Surface profilometry and FIB-SEM analyses confirmed the structural integrity and precise dimensional control of the microvias, validating the feasibility of this approach for high-density interconnect applications.

CONCLUSION
This study proposes a practical method for microvia fabrication in SAP-based advanced packaging. Integrating sputtered thin Cu and Ni–Cr sacrificial metal barrier layers with UV laser drilling and plasma desmear processes enables the fabrication of sub-10 μm microvias with low surface roughness and high reliability. The proposed method effectively overcomes the limitations of conventional CO₂ laser drilling and wet desmear processes, offering a promising solution for next-generation fine-pitch interconnection technologies.

 

Bio:
Student at the Microsystem Packaging Laboratory, Sungkyunkwan University

Abstract:
Carbon nano Tubes are known for their exceptional thermal conductivity. Given this outstanding property, there have been many tries to apply CNTs in other materials where thermal management and mechanical strength are paramount.
However, directly mixing CNTs into solder materials presents a significant challenge due to the density mismatch between CNTs and the solder.
To overcome this issue, we employed a method that involves coating CNTs with Cu. Through the three steps of Cu decorating, we can mitigate the density difference and successfully mix the Sn-decorated MWCNTs into the solder. This approach enhances the thermal properties of the composite solder.
Reflow process is a high-temperature process that utilizes thermal energy and causes warpage and thermal damage problems. In order to overcome this problem, such as laser assisted bonding, several alternative temperature processes have been studied. One of these alternative soldering process, is Intense Pulsed Light soldering, which enables large area soldering with short process time of several microseconds. Since lead-free solder was found to be harmful to the environment and human body, many lead-free solders have been studied. Among those lead-free solders, the Sn-3.0Ag-0.5Cu solder alloy composition has been commonly used, because of its excellent mechanical properties and reliability. In this study, because of the properties of MWCNT that can prevent the propagation of cracks in the solder, Sn-MWCNT and SAC 305 composite materials were synthesized to enhance drop and thermal reliability. Experiment condition of IPL soldering was different pulse widths (2.75, 3.0, 3.25 ms) and pulse number. The shear strength was analyzed through a ball shear test, and the drop impact test was performed by JESD22-B110 standard. The coated Sn-MWCNTs were measured via TEM. The microstructure and fracture surface of the solder were observed using a scanning electron microscope. Long-term reliability of solder joints was evaluated through a high storage temperature test, and it was confirmed that the shear strength decreased over time due to the influence of IMCs growth and coarsening, and the decrease of shear strength value was measured to be the lowest at 0.1% Sn-MWCNT content. In addition, The evaluation of resistance before and after the drop impact test was compared, and the difference in density according to the Sn-MWCNT content was measured. In the case of thermal conductivity, the junction temperature was compared through an IR camera, and it was confirmed that the highest thermal conductivity was achieved in the case of 0.1% Sn-MWCNT particle content.
.

 

Bio:
Jie-Ming Li is a master’s student in the Department of Mechanical and Electro-mechanical Engineering at National Sun Yat-sen University. Since 2024, he has been a member of the MOEMS Laboratory under the supervision of Associate Professor Mei-Ling Wu. His research focuses on thermal deformation behavior and finite element modeling in semiconductor packaging. Specifically, he investigates warpage and stress distribution in QFN lead frames under thermal loading, using three-dimensional thermo-mechanical coupling simulations in ANSYS to analyze the effects of sawing lane geometry and provide design optimization strategies.

Abstract:
With growing demands for packaging reliability, QFN packages often encounter warpage issues during thermal processes. This study investigates the deformation behavior of a 17.1 mm × 16.4 mm QFN lead frame under heating, focusing on the impact of varying sawing-line widths. A three-dimensional thermo-mechanical model, incorporating material and thermal parameters, was implemented within the ANSYS platform to replicate the heating-induced deformation of the QFN lead frame. The simulation applied a temperature ramp from 25°C to 200°C under a 1 Block strip configuration with different sawing widths (0.3 / 0.7 / 0.9 mm). Results show that increased sawing-line width reduces peak deformation near the region due to enhanced local stress relief, while deformation trends remain symmetrical. These findings highlight the role of geometric design in managing thermal warpage and suggest that optimizing sawing-line width is an effective cutting approach to improve structural stability in QFN packaging.

 

Bio:
Shih-Yun Tu is a Bachelor of Science (B.S.) candidate in the Department of Mechanical and Electro-Mechanical Engineering at National Sun Yat-sen University. She is an IEEE Student Member in 2025. Since joining the MOEMS Laboratory in 2024, she has been engaged in research related to microelectronic packaging, simulation mechanics, and dynamic material response. Her current research focuses on analyzing micromechanical vibrations and wafer-edge stress behavior during post-CMP cleaning. Through a combined experimental and simulation-based approach, she investigates the influence of vibration and structural support on wafer surface stress distribution and cleaning quality. Using finite element analysis and vibration measurement, she developed optimized wafer support structures to minimize surface defects and enhance wafer cleaning yield and uniformity. In 2024, she participated in an industry-academia collaboration project with Taiwan Semiconductor Manufacturing Company (TSMC), under the guidance of Professor Mei-Ling Wu.

Abstract:
Based on the Chemical Mechanical Polishing (CMP) process, dynamic properties of wafer cleaning stage are studied, then simulations and analysis are made to improve cleaning capacity of the stage. The improvement of the stress distribution in the wafer could be an important factor, and an increase in the stability of the machine may be contributed to the analysis of vibration characteristics and the optimization of the support parameters. The reinforced wafer support structure was developed to obtain higher structure rigidity and to minimize stress non-uniformity and surface defects due to vibration. It stabilizes the downforce of the cleaning grinding wheel, resulting in uniform clean of particulate contaminants on a wafer. And, consequently, it promotes for enhanced quality of wafer cleaning and yield and facilitates better adhesion between photoresist and pattern accuracy in photolithography processes while it prevents problems such as electromigration between the metal layers and dielectric breakdown. This work goes further to compare the mechanical disturbance behavior between pre-CMP and post-CMP cleaning and to study the vibration phenomenon of stick-slip between the polishing pad and wafer substrate. The influence of these oscillations on the wafer final surface quality is analyzed extensively.

 

Bio:
Chien-Hao Liu (S’12–M’15) received the BS and MS degrees in mechanical engineering from National Taiwan University, Taipei, Taiwan, in 2005 and 2007, respectively. Then, he received his MS and Ph.D. in electrical engineering from the University of Wisconsin–Madison (UW-Madison), Madison, WI, USA, in 2013 and 2014, respectively. He was a research assistant with the Electrical and Computer Engineering Department at UW-Madison from 2011 to 2014. From 2014 to 2015, he was a research associate with the Electrical and Computer Engineering Department at UW-Madison. He is currently an associate professor with the Mechanical Engineering Department at National Taiwan University. His research interests include RF/microwave circuits, antennas, frequency-selective surfaces, acoustic metamaterials.

Abstract:
In this research, we propose a graphene-based composite material for providing high EMC/EMI shielding and superior heat dissipation for IC protection applications. In contrast to most composite EMC shielding materials such as CNTs, graphite, and metal nanoparticles, the presented composite has relatively uniform distributions of graphene inclusions, resulting in high shielding effeteness (SE) in the standard required frequency band ranging from 100 MHz to 3 GHz for IC applications [1]-[2]. In addition, it demonstrates sufficient SE with 10 dB over the range from 8 GHz to 12 GHz for X-band absorptions and military applications. Some samples have been fabricated via the mixing and annealing process, and their effective permittivity and SE are experimentally extracted via waveguide measurements. The composite is integrated with several bare die with RF oscillating signals and its EMC shieling capability is characterized via the self-built EMC scanning probe stations. In addition, the thermal conductivity of the composite is experimentally examined with the well-known 3-omenga methods and the measured values are larger than most packaging materials by order of 10-fold to 100-fold. It is demonstrated that the proposed composite integrated with bare IC can provide efficient EMC/EMI shielding in the desired RF frequency bands and good heat dissipation without degrading the performance. The research results are expected to be beneficial for the IC packaging and the next generation of high-power hetero-integrated IC.

 

Bio:
Dr. Ching-Feng Yu is an Assistant Professor in the Department of Mechanical Engineering at National United University, specializing in advanced electronic packaging and 3D heterogeneous integration technologies. He received his Ph.D. in Power Mechanical Engineering from National Tsing Hua University in 2014, focusing on the mechanical behavior and electromigration resistance of intermetallic compounds. Prior to his academic position, Dr. Yu accumulated over six years of R&D and engineering experience at institutions such as the Industrial Technology Research Institute (ITRI), AU Optronics, and the National Chung-Shan Institute of Science and Technology. His professional work spans heterogeneous chip packaging, automotive display modules, and thermal structural design for defense applications. His research interests include low-warpage packaging, deep learning for advanced packaging inspection, microscale structure modeling, and quantum-based materials simulation. He has authored more than 20 SCI journal papers and 25 conference papers, and has received awards including the ITRI Outstanding Research Award and multiple Best Paper recognitions at the IMPACT International Conference. Dr. Yu is also actively involved in national research projects and academic review committees, demonstrating strong capabilities in cross-disciplinary collaboration and technology innovation.

Abstract:
In high-performance computing and artificial-intelligence applications, organic redistribution-layer (RDL) interposers are rapidly gaining traction because they offer fine pitch, low IR drop and better cost scalability than silicon bridges. Yet fabricating more than a few metal-polyimide layers with the conventional semi-additive process (SAP) is difficult. Each additional layer demands a >300 °C polyimide cure, and the accumulated coefficient-of-thermal-expansion mismatch can push panel-size glass carriers into millimetre-level warpage, degrading lithography alignment and yield [1].
Recent studies have introduced the Hyper-RDL (HRDL) architecture to address this bottleneck. HRDL forms one-metal two-polymer sub-modules on separate carriers, then joins them through low-temperature metal-polymer hybrid bonding. Bonding at 180 to 250 °C and 2 MPa preserves both Cu-Cu and PI-PI interfaces and delivers an average shear strength of about 48 kgf/cm-2 while keeping resistance drift below 1.5 % after 1000 thermal cycles [2]. By eliminating most hard-cure steps, a four-layer HRDL stack has been shown to shrink glass-substrate warpage from roughly 2.8 mm to 0.13 mm, a twenty-fold reduction compared with SAP [2]. Panel-level trials on 12-inch glass further cut deflection from more than 2500 µm to under 500 µm after four layers, confirming that low-temperature bonding can control distortion on large formats [1,3].
Although HRDL greatly mitigates process-induced warpage, published flows still complete die placement, epoxy-mold encapsulation and wafer thinning after the RDL stack is finished. These downstream steps re-heat the substrate or remove mechanical support, re-introducing stress and partially eroding the flatness benefits earned at the RDL stage. A manufacturing sequence that can maintain low stress through the entire module build-up is therefore essential.
The present work proposes an enhanced HRDL-inspired process that re-orders the key operations, as illustrated in Fig. 1. Fine-pitch RDL and through-mold vias are first patterned on separate carriers. Active dies are then mounted, over-molded and back-thinned to the target z-height while the structure remains fully supported. After applying a polyimide passivation to seal exposed copper, the upper and lower RDL modules are aligned and joined by Cu / PI hybrid bonding at sub-250 °C. The carrier is subsequently laser-debonded, and solder balls are attached to form the final ball-grid array. By locking in dimensional stability before bonding, the new flow limits final package deflection to below 100 µm on 300 mm glass while sustaining 2 µm line-space and 6 µm through capability. This sequence therefore offers a robust path to ultra-flat, high-layer-count RDL interposers that outperform both SAP and baseline HRDL in warpage control, mechanical strength and electrical reliability.

 

Bio:
Chao-Kai Hsu is a seasoned professional with extensive experience in the field of wafer-level packaging. He joined the Industrial Technology Research Institute (ITRI) in Taiwan in 2004 and has since been dedicated to driving technological innovation and achieving key breakthroughs. From 2004 to 2005, Hsu worked in the Microelectromechanical Systems (MEMS) department, where he contributed to the development and validation of splitter technology for optical coupling. This foundational experience strengthened his expertise in optical integration and set the stage for his future technical pursuits. From 2005 to 2021, he transitioned to the 3D Integrated Circuit (3DIC) department, focusing on wafer molding, wafer thinning, and the development of flexible light source technologies. His contributions were instrumental in advancing 3DIC packaging technologies and applications. In 2021, Hsu joined the Heterogeneous Chip Integration and Assembly department, where he specializes in 3D Fan-Out Wafer-Level Packaging (3D-FOWLP)—a cutting-edge technology that enables high-density heterogeneous integration. This has since become one of his primary areas of expertise. Hsu currently serves as a researcher at the Electronics and Optoelectronics System Research Laboratories (EOSRL) of ITRI. With his deep technical knowledge, hands-on experience, and unwavering commitment to innovation, he continues to drive progress in the semiconductor packaging industry and actively shares his insights to inspire future developments.

Abstract:
To meet the rising demand for high-performance, multifunctional electronic systems, this study proposes an innovative dual fan-out module 3D packaging architecture for large-size, low-warpage, high-density multi-chip heterogeneous integration. Traditional fan-out packages face severe warpage due to interactions between multilayer RDLs and molding compounds—especially in 3D stacked or large-format designs.
Our solution integrates carrier preparation, RDL and copper pillar processes, high-density chip packaging, wafer molding and thinning, polymer coating, passivation, and precision bonding of dual fan-out modules. Experiments conducted on silicon, ABF molded, and RDL TMV molded wafers demonstrated that warpage in 100 mm RDL TMV wafers was reduced from 0.52 mm to 0.04 mm after bonding. The module bond strength reached 118.6 kgf, exceeding the industry threshold of 9.3 kgf. A fine 20 µm chip-to-chip gap was achieved, with no delamination or voids observed after 10 reflow cycles. SEM, SAT, and X-ray analyses confirmed excellent structural integrity.
This dual fan-out 3D packaging platform offers high reliability, fine-pitch scalability, and excellent adaptability, making it a strong candidate for next-generation SiP applications in AIoT, HPC, and edge computing.

 

Bio:
My name is Lin Po Yuan. I completed my undergraduate studies at Southern Taiwan University of Science and Technology, and I am currently pursuing my graduate degree at National Sun Yat-sen University, majoring in Advanced Semiconductor Packaging and Testing. My hobbies include working out and watching movies.

Abstract:
Abstract
In modern power electronics and semiconductor packaging, silver paste has emerged as a critical material due to its exceptional electrical and thermal conductivity. This material is widely utilized to form reliable interconnects and die-attach layers, with stencil printing followed by sintering being a prevalent deposition technique. However, a frequent challenge in this process is the “dog-ear” effect, characterized by edge bulging or excessive accumulation of paste around printed features. This undesired morphology can lead to non-uniform bonding interfaces, degraded thermal contact, and compromised long-term reliability, particularly in fine-pitch or high-power applications where precision is paramount. Such defects are especially problematic in advanced microelectronics, where even minor irregularities can significantly impact device performance and durability under operational stresses.
This study aims to systematically investigate and optimize the silver paste stencil printing process to mitigate or eliminate the dog-ear effect through a combination of experimental measurements and advanced fluid dynamics simulation. A stainless-steel stencil with an aperture size of 5.9 mm × 4.9 mm and a thickness of 80 μm serves as the experimental platform. Key printing parameters, including squeegee angle (65°), printing speed (10–20 mm/s), separation speed (1–2 mm/s), and squeegee pressure (4–6 kg), are systematically varied to assess their impact on paste deposition quality and edge morphology. These parameters are critical in determining the flow behavior and final printed structure of the shear-thinning silver paste, which exhibits complex rheological properties that influence its behavior during printing.
To enhance understanding of the underlying mechanisms, ANSYS FLUENT is employed to simulate the internal flow of the silver paste, incorporating its rheological properties such as viscosity curves, yield stress, and shear-thinning behavior. This simulation approach enables a detailed modeling of the deposition behavior, providing insights into how paste flow dynamics contribute to the dog-ear effect under varying conditions. The simulated paste profiles are experimentally validated using a high-precision surface profile scanner (VR5200), allowing for a quantitative comparison between simulation predictions and real-world outcomes. This validation step ensures the reliability of the computational model and its applicability to practical scenarios, bridging the gap between theoretical analysis and industrial application.
By correlating experimental data with simulation results, this research identifies the key factors driving the dog-ear phenomenon, including the interplay between printing speed, separation dynamics, squeegee pressure, and the paste’s viscoelastic properties. Based on these findings, optimal printing conditions are proposed to achieve uniform edge profiles and enhance overall printing reliability. These insights offer practical guidance for industry practitioners, particularly in optimizing die-attach and packaging processes for high-performance power electronics. The study’s outcomes are expected to contribute to improved manufacturing yields, reduced defect rates, and the development of robust semiconductor devices, addressing the growing demands of advanced electronic applications in fields such as renewable energy, electric vehicles, and 5G technology.

 

Bio:
Hello everyone, my name is Yeh Bao-Lin. I graduated from the Department of Automation Engineering at National Formosa University and am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. I’m passionate about semiconductor packaging technologies, and in my free time, I enjoy playing baseball.

Abstract:
In high-power semiconductor module packaging, silver (Ag) sintering has emerged as a promising die-attach technology due to its excellent thermal and electrical conductivity, as well as its ability to withstand high operating temperatures. As packaging structures evolve toward higher integration and enhanced thermal management, incorporating a Die Top System (DTS) on the die has become an effective approach to improve both heat dissipation and mechanical robustness. This study aims to systematically investigate the reliability differences between single-step and double-step sintering processes when applied to DTS-integrated structures, focusing on the bonding quality and long-term performance to provide a process guideline for advanced packaging design.
Silver paste is applied using stencil printing, with stencil apertures measuring 4.9 × 5.9 mm and a thickness of 80 μm. After printing, the paste height and shape are measured using a VR-5200 surface profiler to verify uniform deposition and edge quality. Both single and double sintering processes are carried out under a bonding pressure of 20 MPa. The experimental parameters include three sintering temperatures (230°C, 260°C, and 280°C) and two sintering durations (2 minutes and 5 minutes). In the double-step sintering process, the die is first attached and sintered, followed by the placement of the DTS and a second sintering under the same conditions. This design allows for a comparative analysis of the microstructural and bonding performance changes before and after DTS integration, enabling a deeper understanding of how sintering sequence influences joint evolution.
To evaluate the structural integrity and reliability of the bonded layers, multiple experimental tests are planned. Scanning Acoustic Tomography (SAT) will be used to detect interfacial delamination, while the Dage 4000+ system will be used to perform die shear and peeling tests. The microstructure of the sintered layer will be examined using Scanning Electron Microscopy (SEM), and porosity will be quantified based on cross-sectional SEM images using ImageJ software. In addition, Thermal Cycling Tests (TCT) lasting 500 and 1000 hours will be conducted to simulate long-term thermal fatigue conditions. After TCT, all evaluations will be repeated to observe changes in reliability and material degradation.
The objective of this study is to investigate the effects of the DTS structure and different sintering sequences on the microstructure and mechanical stability of the die-attach layer, and to further identify the most suitable process parameters. In the future, we hope that the experimental results will provide concrete references for the packaging design of high-reliability power modules. In addition to improving the bonding strength and thermal performance of the die-attach layer, the findings from this study may also be applicable to other fields such as automotive electronics, renewable energy systems, and high-power electronic devices.

 

Bio:
my name is Tsung-Chieh Wu . I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. My research focuses on the application of High Glass Transition Temperature Epoxy Resin in Power Module Packaging. I am currently interning at the R&D department of ASE Group.

Abstract:
In recent years, the demand for high-reliability and thermally robust power module packaging has surged, driven by the rapid development of electric vehicles, renewable energy systems, and high-power industrial electronics. Traditional epoxy molding compounds (EMCs) often suffer from warpage, delamination, and thermal degradation when subjected to elevated temperatures or harsh operating environments, primarily due to their limited glass transition temperature (Tg) and insufficient thermal conductivity. To address these challenges, this study investigates the use of high-Tg epoxy resins as molding materials in advanced power module packaging.

In the initial phase, five epoxy molding compounds with different glass transition temperatures were selected for comparative evaluation based on their datasheet properties, including thermal stability and low coefficient of thermal expansion (CTE). These materials were molded onto standardized power module test vehicles utilizing a single-side cooling configuration. Experimental procedures include thermal cycling (−40 °C to 150 °C) and high-temperature storage (e.g., 200 °C for 1000 hours), with all test conditions intentionally designed to exceed the requirements defined in the AQG 324 automotive reliability standard. Post-test characterizations, including cross-section analysis (CSA), scanning acoustic tomography (SAT), and scanning electron microscopy (SEM), were employed to evaluate internal voids, delamination, and crack propagation.

Additionally, a series of thermal and mechanical analyses were performed to assess each material’s intrinsic properties. Thermomechanical analysis (TMA) and differential scanning calorimetry (DSC) were conducted to confirm their thermal expansion characteristics and accurately determine Tg. Dynamic mechanical analysis (DMA) was used to evaluate the viscoelastic behavior of the EMCs under temperature-dependent mechanical stress, providing additional insight into modulus performance near and beyond Tg. Thermogravimetric analysis (TGA) was performed to assess decomposition behavior under continuous heating, and a rheometer was employed to study the flow behavior and viscosity of the uncured epoxies during molding, ensuring suitability for void-free encapsulation. The combination of these analyses allows for a comprehensive understanding of material behavior across both thermal and mechanical reliability domains.

Experimental results demonstrated that high-Tg epoxy resins consistently exhibited superior stability and reliability under thermal stress conditions. They showed enhanced interfacial adhesion and reduced CTE mismatch, which effectively minimized internal defects such as delamination and microcracking. Thermal aging tests confirmed their structural integrity after prolonged high-temperature exposure. The materials also maintained encapsulation performance through extended thermal cycling, validating their applicability in harsh environments such as automotive under-hood systems and industrial power inverters. These findings provide practical guidance for the selection and qualification of robust EMC materials in next-generation power module packaging, especially for applications requiring extended service life under extreme thermal conditions.

 

Bio:
Hello, my name is Tsung-Han Li, a second-year master’s student at the Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-sen University. Currently, I am also working as an R&D intern at ASE Group (Advanced Semiconductor Engineering), where I’m part of a department focused on the development of power module packaging technologies, especially for electric vehicle (EV) applications. Our team explores various innovative packaging approaches, such as copper and silver sintering, as well as next-generation EMC (Epoxy Molding Compound) materials. My personal research focuses on the design, analysis, and application of Insulated Metal Substrate (IMS) in power modules, aiming to bridge the gap between academic insight and real-world implementation. By combining my university research and hands-on industrial experience, I strive to contribute practical and forward-looking solutions to the field of power electronics packaging.

Abstract:
The rapid proliferation of electric vehicles (EVs) necessitates advancements in power module technology, particularly in thermal management, reliability, and cost-effectiveness. Traditional ceramic substrates, including Direct Bonded Copper (DBC) and Active Metal Brazed (AMB), are widely utilized due to their excellent thermal conductivity and insulating properties. However, they present significant challenges primarily arising from mismatches in coefficients of thermal expansion (CTE) between ceramic and copper layers, causing stress-induced reliability issues such as delamination and chipping. Consequently, substrate design flexibility is limited to symmetrical copper layers, restricting further improvements.

Insulated Metal Substrates (IMS) offer a promising alternative, exhibiting superior CTE compatibility with copper layers, significantly reducing thermal and mechanical stress. This inherent advantage enables IMS substrates to employ more flexible structural designs, including asymmetric copper layer configurations, without compromising reliability. Furthermore, IMS substrates can be manufactured thinner by reducing dielectric layer thickness, significantly decreasing thermal resistance and enhancing heat dissipation performance.

Leveraging these advantages, this research evaluates three distinct IMS substrate designs: symmetrical copper layers, thicker upper copper with thinner lower copper layers, and thicker lower copper with thinner upper copper layers. Each IMS configuration maintains an identical total thickness as traditional DBC (ZTA) and AMB substrates. By strategically reducing the dielectric layer thickness, IMS substrates allow proportional thickening of copper layers, optimizing thermal performance.
Finite Element Analysis (FEA) simulations were conducted using ANSYS to assess thermal distribution and mechanical warpage behavior across various substrate configurations. Experimental validation included thermal resistance measurements using T3STER, warpage analyses via PS400 Shadow Moiré, and dielectric breakdown voltage tests to evaluate insulation strength across different dielectric materials. Integrating simulation with experimental results ensures a comprehensive and accurate evaluation of IMS substrates under realistic operational conditions.

The primary goal of this study is to identify the optimal IMS structural configuration, balancing superior thermal performance, enhanced mechanical reliability, and excellent insulation capability. The results will provide valuable guidance for effective power module substrate designs, validating the practical viability of IMS as a suitable replacement for conventional ceramic substrates in EV and advanced electronic applications. Ultimately, this research significantly contributes to developing highly efficient, reliable, and cost-effective power module solutions, thereby accelerating the adoption of advanced power electronics technologies.

Key Words: Power Module Substrate, Insulated Metal Substrate (IMS), Finite Element Analysis (FEA), Thermal Management, Warpage, Insulation Strength

 

Bio:
Ching-Kuan Lee is currently a Researcher with Industrial Technology Research Institute, Hsinchu, Taiwan.

Abstract:
Gallium nitride high electron mobility transistors are characterized by fast switching speeds and small chip sizes, making it challenging to achieve low parasitic inductance and high heat dissipation in packages for power electronics applications. In this paper, a packaging technique is developed for the fabrication of horizontal 650V, 30A GaN power transistors in discrete packages. The electrical contacts are silver sintered materials fabricated on direct plated ceramic (DPC) substrates using flip chip bonding technology and attached to a copper frame for heat dissipation and electrical connection. We performed process stress simulations and compared them with actual experimental samples. We fabricated discrete packages, characterized their static performance, and verified 1000-cycle temperature cycling tests (TCT). The data show the feasibility of this discrete package for power electronics applications.

 

Bio:
My name is Ming-Pei Lu, and I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University in Taiwan. My research focuses on the warpage behavior of high glass transition temperature (High Tg) epoxy molding compounds used in semiconductor packaging. I am particularly interested in understanding how material properties and process parameters influence thermal-mechanical deformation during packaging processes, with the goal of improving reliability and manufacturability in advanced electronic modules.

Abstract:
With the widespread deployment of wide bandgap (WBG) semiconductor technologies such as silicon carbide (SiC) in automotive and high-temperature power electronics, packaging structures are increasingly challenged by severe thermal-mechanical stress. Warpage deformation has become a critical issue that significantly affects the reliability and lifetime of power modules. To improve thermal stability and effectively mitigate warpage, this study investigates several high glass transition temperature (Tg) epoxy molding compounds (EMCs) as encapsulation materials, benchmarked against standard commercial EMCs. A representative single-side cooled power module structure is modeled for simulation and validation.

The study begins with experimental characterization of thermal-mechanical properties of EMCs, including measurements of coefficient of thermal expansion (CTE), modulus behavior, and glass transition temperature using TMA (Thermo-Mechanical Analysis), DMA (Dynamic Mechanical Analysis), DSC (Differential Scanning Calorimetry), and rheometry. These measured parameters are then integrated into a finite element model (FEM) that simulates the warpage behavior during the transfer molding process. The model also includes the sintered Ag die-attach layer, DBC substrate, and heatsink interface to reflect real package complexity.

Simulation results indicate that differences in elastic modulus and CTE among EMCs can result in significant warpage variations, reaching up to several hundred microns. Warpage deformation is found to be concentrated in the chip central region and strongly correlated with stress accumulation near material interfaces. Furthermore, the study explores how adjusting package thickness ratio, material stiffness, and cooling profiles can serve as effective strategies to reduce deformation.

To validate simulation accuracy, shadow moiré fringe analysis is employed to measure the warpage profile of post-molded samples. Additionally, scanning acoustic tomography (SAT) is used to identify delamination or void defects at key interfaces. The experimental observations show strong agreement with simulation results, confirming the effectiveness of the proposed modeling workflow and materials characterization approach.

This study demonstrates that proper material selection, along with fine-tuned process control, can significantly mitigate warpage in high-temperature power modules using high Tg EMCs. The research outcomes offer practical guidelines for packaging engineers in optimizing encapsulation strategies to enhance the reliability and mechanical stability of next-generation power electronic systems under high thermal stress conditions.

 

Bio:
My name is Kuan Chih Chen. I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. My research focuses on the application of copper sintering in high-power modules. I am currently interning at the R&D department of ASE Group.

Abstract:
With the increasing demand for high-reliability and high-efficiency power modules in electric vehicles and industrial applications, the selection of die-attach materials has become a critical factor affecting both thermal management and long-term reliability of the module. Sintered silver has long been widely adopted as the standard bonding material in high-end packaging due to its excellent thermal and electrical conductivity, along with superior thermal stability and mechanical strength. However, its high material cost and demanding processing requirements—such as elevated temperature and pressure—limit its adoption in cost-sensitive applications.
As a promising alternative, sintered copper has garnered significant attention in recent years owing to its excellent thermal conductivity, robust mechanical properties, and significantly lower material cost compared to silver. Nevertheless, one of the major challenges hindering its widespread adoption in practical module applications is its susceptibility to oxidation during the high-temperature sintering process. Oxidation at the bonding interface can degrade electrical conductivity and reduce joint strength.
In this study, two types of sinterable copper paste formulations were selected to evaluate their feasibility as substitutes for sintered silver. The experimental procedures included tensile and shear strength measurements to assess mechanical reliability, as well as thermal cycling tests (TCT) to simulate fatigue behavior under long-term thermal stress conditions. To further improve joint quality, process optimization targeting low void ratio was also implemented, as excessive porosity can adversely affect both thermal conduction and mechanical integrity. Cross-sectional inspection and microstructural analysis were conducted to investigate interfacial bonding behavior and failure mechanisms.
This work provides a comprehensive comparison between sintered copper and sintered silver, highlighting the performance potential of copper-based die-attach materials and analyzing the key challenges that must be overcome for commercialization in high-reliability power module applications. The findings reveal that while sintered silver still outperforms in terms of electrical and thermal performance, optimized sintered copper joints demonstrate comparable mechanical integrity and thermal fatigue resistance under certain conditions. Additionally, the influence of particle morphology, surface finish of the substrate, and sintering atmosphere were identified as critical factors influencing the joint quality of copper-based materials. Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDS) analyses provided insights into microstructural evolution and oxidation patterns, confirming that controlled sintering environments and protective surface treatments are essential to mitigate interface degradation. These results suggest that with appropriate material formulation and process control, sintered copper has the potential to become a cost-effective and reliable alternative for future high-performance power electronic packaging.

 

Bio:
Hung-Chi Chang is now a Ph.D. Student in the Institute of Electronics, National Yang Ming Chiao Tung University, Taiwan. His interesting research topic is electrostatic discharge (ESD) protection design for semiconductors and integrated circuits.

Abstract:
An effective solution to significantly improve electrostatic discharge (ESD) robustness of the silicon carbide vertical double-diffused metal-oxide-semiconductor field-effect transistor (SiC VDMOSFET) is proposed by co-packaging a transient voltage suppressor (TVS) inside the package with SiC device together. The weakness of ESD test on SiC VDMOSFET is the gate-to-source mode (GS mode), where positive or negative ESD zapping is applied to the gate of the device while its source is grounded and its drain is floating. With co-packaged TVS, the 1700-V SiC VDMOSFET can pass human-body-model (HBM) ESD level of ± 8 kV in the GS mode test, as well as no degradation on its switching performance verified by double pulse test.

 

Bio:
My name is WU BING-ZONG. I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing at National Sun Yat-sen University. My research focuses on the application of copper-to-copper bonding in high-power modules. I am currently interning at the R&D department of ASE Group.

Abstract:
A comprehensive and systematic comparison of the bonding structure between the substrate and the pin holder, focusing on two copper-to-copper joining technologies—ultrasonic welding and conventional solder paste bonding. Due to copper’s excellent electrical and thermal conductivity, it is widely used in various electronic packaging modules, especially in high-power and high-current applications such as automotive electronics, battery systems, and power modules. Therefore, ensuring the quality, strength, and long-term reliability of copper-to-copper interconnections is critical not only for the performance of individual modules but also for the stability and safety of the overall system.

In this research, key evaluation metrics—including contact resistance and shear strength—were selected to quantitatively assess and compare the performance of the two bonding techniques. Ultrasonic welding enables direct solid-state bonding by applying high-frequency mechanical vibrations under ambient or low-temperature conditions. This method does not require additional filler materials such as solder paste or flux, which greatly simplifies the bonding process. Furthermore, it avoids common problems such as thermal damage, material incompatibility, and interfacial delamination often seen in conventional soldering processes. The joints formed by ultrasonic welding are tightly bonded and exhibit low electrical resistance and high mechanical integrity, making them highly suitable for high-frequency, high-current applications in advanced electronic systems.

On the other hand, conventional solder paste bonding involves the melting and solidification of a filler metal, which relies heavily on thermal processing and precise control of heat profiles. This process is susceptible to the formation of voids, cracks, and brittle intermetallic compounds due to gas entrapment, flux decomposition, and insufficient wetting. These defects can degrade both mechanical strength and electrical conductivity over time, especially under conditions of thermal cycling or vibration. Moreover, the high temperatures required for soldering can impose additional stress or damage on sensitive components or multilayer packaging structures, making the process less suitable for compact, high-density designs.

The experimental results of this study clearly demonstrate that ultrasonic welding provides superior electrical and mechanical performance compared to solder paste bonding. In addition to reduced contact resistance and higher joint strength, ultrasonic welding offers advantages such as process simplification, minimal thermal impact, no flux or filler residue, and enhanced long-term reliability. These characteristics make ultrasonic welding a highly promising technique for next-generation electronic packaging, particularly in demanding fields where durability, stability, and miniaturization are essential.

As power electronic systems continue to evolve toward higher integration, greater efficiency, and increased reliability, ultrasonic welding presents itself as a future-forward solution to overcome the limitations of traditional soldering. It aligns well with the industry’s pursuit of environmentally friendly, low-temperature, and robust interconnection methods. In summary, ultrasonic welding not only enhances bonding performance but also provides a solid technological foundation for the continued advancement of high-performance power modules and electronic devices.

 

Bio:
I am a researcher at the Institute of Scientific and Industrial Research, Osaka University, working in the Flexible 3D Integration Collaborative Research Laboratory. My research focuses on the back-end processes of semiconductor manufacturing, particularly on the evaluation of encapsulation resins, reliability testing, and performance analysis.

Abstract:
With the rapid advancement of electrification technologies, power modules, which are essential components that manage electrical currents by rectifying, amplifying, or switching, have expanded into the field such as electric vehicles, renewable energy, aerospace, and robotics. These modules typically consist of a substrate, a semiconductor die, and bonding wires, which are mounted and interconnected before being encapsulated for protection. However, increasing the demand for smaller, more efficient modules capable of enduring demanding operating environments, one promising strategy for reducing module size involves replacing traditional gel encapsulation with epoxy encapsulation, which eliminates bulky outer casings and can reduce packaging volume significantly. Therefore, to ensure durability in challenging conditions such as elevated temperatures, humidity, thermal cycling, and electrical stress, it is essential to thoroughly assess the reliability of epoxy encapsulation. Generally, failures in power modules often occur at the interface between the epoxy and substrate, due to the formation of gaps and voids arising from thermal stresses mismatches in the thermal expansion coefficients of as well as the epoxy’s glass transition.
Recently, various epoxy materials with high-glass transition temperature (Tg) resins, whose thermal expansion properties closely match those of copper substrates, have been developed and have mitigated many common failure modes that were mentioned above. In this context, cycloaliphatic epoxy resins have garnered significant interest due to their inherently rigid molecular structure and offer superior thermal stability, reduced moisture absorption, and enhanced dimensional stability, compared to conventional bisphenol A-based epoxies. As a result, these attributes make them particularly suitable for power modules exposed to rapid temperature fluctuations and high humidity, conditions that often cause repeated resin swelling and interface degradation. Moreover, cycloaliphatic epoxies typically exhibit higher Tg and improved thermal properties, approaching those of advanced engineering plastics. This makes them promising candidates for applications involving SiC power devices and other high-temperature environments where conventional epoxies may fall short.
In this study, we compare a cycloaliphatic epoxy resin used for encapsulating copper substrates with a conventional bisphenol A-type epoxy resin. Samples are fabricated using a face-down compression molding method that simulates actual device packaging. In order to compare their reliability, pressure cooker tests and power cycling tests were evaluated for their mechanical properties, interfacial delamination, and crack formation before and after tests by scanning acoustic tomography (SAT), shear strength tests, and scanning electron microscopy (SEM). These experiments are currently underway, and we anticipate that the results will serve as one of the key guidelines for material selection and encapsulation design, ultimately contributing to the enhanced durability of power modules.

 

Bio:
I am currently an R&D Engineer at Tong Hsing Electronic Industries, Ltd., specializing in the development and application of conductive paste printing and sintering technologies. Before joining Tong Hsing, I spent over a decade in the PCB industry, where I worked as a Product Engineer and R&D Engineer. During that time, I gained extensive experience in product development and developed a solid understanding of PCB manufacturing processes. With a strong background in electronic materials and process engineering, I am committed to advancing high-performance conductive materials for next-generation electronic packaging applications.

Abstract:
ABSTRACT
With the rapid development of high-power applications such as electric vehicles, high-speed charging systems, and smart grids, the power density within modules has significantly increased. This escalation places stringent demands on thermal management structures and electrical reliability. Traditionally, metal spacers (e.g., AlSiC, CuMo) have been employed as vertical interconnects and heat-conducting elements between devices and substrates in power modules. While these materials offer excellent performance, they come with high material costs, complex mechanical processing requirements, and risks associated with supply chain instability. Under the current trend of global supply chain restructuring, these issues pose challenges to design flexibility and cost control in high-end power modules.
On the other hand, ceramic substrates—owing to their high thermal conductivity, excellent electrical insulation, and thermal stability—have increasingly become the mainstream base materials for high-power modules. If vertical electrical interconnection can be realized through precision via drilling combined with high-temperature sintered conductive pastes, traditional metal spacer structures can potentially be replaced, while retaining electrical and thermal functionalities and reducing overall material costs. Furthermore, compared to conventional electroplating via-filling techniques, printed via-filling methods offer simpler processes and support for larger via sizes and diverse geometries, thereby enhancing manufacturing flexibility.
This study focuses on integrating high-temperature sintered metal paste via-filling technology with the Direct Plated Copper (DPC) process to achieve vertical interconnection and high-density metallization on ceramic substrates. High-temperature sintered pastes exhibit excellent conductivity and stable microstructures post-sintering, forming high-adhesion interfaces with ceramic via walls. Under optimized sintering conditions, their electrical performance can sustain operational voltages from several hundred volts to kilovolt levels and current loads of tens of amperes.
Simultaneously, the DPC process enables the fabrication of precision copper circuitry on ceramic surfaces via direct plating. This process supports low-impedance, locally variable thickness designs to meet regional electrical and thermal dissipation requirements. By integrating these two technologies, the need for traditional spacer structures can be eliminated, allowing ceramic substrates to achieve more highly integrated structural designs. This advancement ultimately enhances power density, reliability, and manufacturing flexibility in power modules.
In summary, this study aims to validate the feasibility and effectiveness of the proposed integrated process in high-power module applications. It will focus on key aspects such as via filling quality, electrical conductivity, voltage endurance, and interface reliability between the paste and substrate, providing concrete solutions for the design and manufacturing of next-generation high-power modules.

 

Bio:
Hello everyone, my name is Ming-Ru Wu, and I am currently a second-year master's student at the Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-sen University. I focus on research in semiconductor packaging technology, particularly in the design and testing of high-performance electronic devices. During my studies, I have participated in several semiconductor-related research projects, gaining valuable academic experience. Apart from my academic work, I enjoy playing table tennis. It not only helps me relax and unwind but also improves my concentration and reflexes. I also enjoy discussing the latest developments in technology with friends and hope to contribute to the semiconductor industry in the future. I aim to combine my professional knowledge and interests in my future career, constantly challenging myself, learning, and growing.

Abstract:
The thermal dissipation performance of Epoxy Molding Compound (EMC) plays a critical role in the reliability and efficiency of electronic power modules. This study compares the thermal dissipation performance of high Glass Transition Temperature (Tg) EMC and high thermal conductivity EMC to evaluate their effectiveness in managing heat in power module applications. High Tg EMC materials are characterized by superior thermal stability and enhanced resistance to thermal cycling, making them suitable for high-temperature environments. In contrast, high thermal conductivity EMC materials are designed to improve heat conduction and reduce the temperature rise within the module, ensuring more efficient thermal management.

This study aims to systematically investigate the thermal dissipation behavior in modules through experimental and simulation methods, comparing the differences between high Tg and high thermal conductivity Epoxy Molding Compound. The thermal conductivity of the materials used ranges from 0.8 to 3 W/m·K, evaluating the actual model in molding comparisons. By comparing the thermal properties and behavior of both materials, the study assesses their suitability for different thermal management challenges in power modules.

In order to confirm the thermal transfer behavior of Epoxy Molding Compound in modules, this study uses ANSYS to perform numerical simulations of thermal conductivity. The thermal properties of the materials are analyzed, and the temperature transfer conditions are compared with actual measurement results. These simulations help to validate the real-world situation and refine the predictive models of heat flow within power modules, ensuring accurate simulations for optimizing material selection and module design.

In addition to simulations, Scanning Electron Microscopy (SEM) was also used to observe the material structure. These high-magnification observations allow for a comparison of internal material differences, providing insights into the microstructure of the EMC and its impact on thermal dissipation. By correlating the experimental data with the material properties, this study identifies key factors affecting thermal dissipation efficiency and compares the differences in heat dissipation across different materials. The microstructural observations further enhance the understanding of how the material's composition, structure, and surface characteristics influence its thermal performance.

The results from this research show that high Tg EMC materials, while providing exceptional thermal stability and resistance to degradation under high-temperature conditions, might not offer the most efficient heat conduction, which is crucial for high-power applications. On the other hand, high thermal conductivity EMC materials excel in minimizing temperature rise within the module, ensuring faster heat transfer and superior thermal management efficiency. These materials are better suited for applications where efficient heat dissipation is critical.

 

Bio:
Lo-Ching Wu received the B. Mgt. degree in Department of Logistics and Operations Management from National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan, R.O.C., in 2023. She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
As the international gold price rises, the cost of gold (Au) wire bonding package increases accordingly. In the packaging industry, various out-source assembly and testing houses (OSATs) have successively replaced Au bonding wires with other metal wires such as silver wire, copper wire or aluminum wire. Among them, copper wire and aluminum wire are mainly used in consumer electronics, industrial products, and low-cost electronic products, while the more expensive gold, silver wire and other precious metal wires are employed in high-end products such as in automotive, military, and aerospace applications.
Automotive electronic products have a long-span life and the relevant product specifications are more stringent. If the bond-wires used in the product are prone to oxidation, corrosion and other adverse conditions, it will cause product failure and have a high probability of affecting the user's life safety. Therefore, automotive electronic products must have higher reliability standards and environmental test tolerance of temperature and humidity, longer product life cycle, high failure standards that should be included in the consideration of bond-wire selection for electronic packaging.
This study will explore using silver alloy wire to replace gold wire as the bonding wire for stacked NAND flash memory packages that aims to meet automotive grade levels of electronic products. In the experiments there are two types of silver alloy wires, referred as silver Type A and Type B. The composition of the Type A is Ag 96%, Pd 3.5%, other < 0.5%, and that of the Type B is Ag ≧ 98%, other < 2%. Both silver types have wire diameter of 0.7 mil (~17.5 m). In this paper, we apply the factorial design of experiment (DOE) and analysis of variance (ANOVA) to find out the significant factors of wire bonding process for two candidates of silver alloy wires. Ball shear strength is major one of quality factors for evaluation. Response Surface Method (RSM) is used to achieve the optimal parameters of the significant process factors.

 

Bio:
2018 ~ 2024 School of Materials Science and Engineering, Gyeongkuk National Univ., B.S. 2025 ~ present Advanced Packaging Integration Center, Korea Institute of Industrial Technology, Researcher 2025 ~ present Gyeongkuk National Univ. Materials Science and Engineering, Currently enrolled in a master's degree

Abstract:
INTRODUCTION
To meet the demands of micro-pitch I/O density in advanced packaging for AI and high-performance semiconductors, both substrate pad miniaturization and high-reliability soldering are essential. Conventional mass reflow (MR) processes are widely used due to their productivity; however, prolonged exposure to high temperatures (~260 °C for several minutes) can induce significant warpage and thermal damage. This becomes increasingly problematic in fine-pitch applications where reduced solder volumes exacerbate defects such as opens or bridging due to warpage.
In contrast, laser selective reflow (LSR) offers a more localized and energy-efficient bonding approach by selectively irradiating only the solder joint areas, enabling rapid solder melting while minimizing thermal impact on the entire substrate. This study evaluates the advantages of LSR bonding by comparing the mechanical reliability and fracture characteristics of SAC305 solder joints formed on direct palladium immersion gold (DPIG) surfaces, a Ni-less alternative designed for improved RF performance and sustainable processing.

EXPERIMENTAL METHODS
The test vehicle used in this study was an FR-4-based PCB with solder mask-defined Cu pads (350 µm diameter). The surface finish applied was DPIG, comprising 0.15 µm of Pd followed by 0.15 µm of Au. SAC305 solder paste was stencil-printed onto the pads, and 450 µm diameter SAC305 solder balls were aligned and mounted uniformly.
LSR bonding was performed using a 1070 nm fiber laser with a 15 × 15 mm beam area. The laser was irradiated at 1.56 W/mm² for 2 seconds, reaching a peak joint temperature of ~250 °C. MR bonding was conducted in a nitrogen convection oven with a 6-minute reflow cycle, peaking at ~250 °C.
High-speed shear testing (1 m/s, 50 µm shear height) was conducted on 25 samples per condition to ensure statistical significance. Fracture surfaces were examined via scanning electron microscope (SEM) and classified as ductile (0–25% brittle), mixed (25–75%), or brittle (75–100%) based on the brittle fracture area ratio.
RESULTS AND DISCUSSION
X-ray analysis confirmed that void formation was minimal in both bonding methods, with the LSR process exhibiting negligible voids. Figure 1 presented the internal solder microstructures. The MR samples (Figure 1a and 1b) exhibited large columnar β-Sn grains with a coarse eutectic network, whereas the LSR samples (Figure 1c and 1d) showed fine equiaxed grains and a uniformly distributed eutectic structure, resulting from rapid localized heating and solidification.
In both bonding cases, Cu₆Sn₅ intermetallic compounds (IMCs) were formed at the solder–substrate interface. The Pd/Au layers of the DPIG surface finish were fully consumed during bonding, leading to direct Cu–Sn interfacial reactions. As shown in Figure 2, the IMC thickness in the LSR samples was significantly thinner than that in the MR joints.
Shear strength measurements indicated that the LSR samples exhibited higher mechanical strength than the MR samples, which was attributed to the formation of thinner IMCs and a more refined microstructure. Fracture mode analysis also confirmed that the LSR joints exhibited a lower ratio of brittle fracture compared to the MR joints.

CONCLUSION
The findings demonstrate that LSR bonding on DPIG surfaces provides superior joint reliability, higher shear strength, and reduced brittle fracture behavior compared to traditional MR bonding. Furthermore, by eliminating the Ni layer and minimizing thermal exposure, the LSR + DPIG combination supports both RF performance and green manufacturing objectives, such as energy efficiency and material sustainability.

 

Bio:
Ms. Chih Chieh Huang is currently an undergraduate student in the Department of Chemical Engineering and Materials Science at Yuan Ze University. Her research focuses on electromigration reliability of micro-joints in advanced packaging, with particular emphasis on surface finishes such as ENEPIG and ultra-thin Ni(P). Integrating finite element simulation with experimental characterization, he investigates failure mechanisms at the microscale. Her work also explores the impact of 5G high-frequency signal transmission on the electrical integrity and structural stability of packaging materials, aiming to develop reliable and low-resistance interconnects for next-generation high-speed communication systems.

Abstract:
The incessant trend toward ultrathin, multifunctional electronics necessitates a continuous shrinkage in the joint size, result in serious electromigration-induced failures in the join structures. In this study, electromigration reliability of eutectic Sn-Cu (Sn-0.7Cu) micro joints with three different surface coatings over the Cu pads was investigated by ANSYS simulation and metallographic analysis. This study reported that the ultrathin-Ni(P)-type ENEPIG surface finish not only promotes larger Sn grains in solder bumps in the as-reflow state (compared to OSP) but also markedly reduces the electrical resistance as well as Joule heating of micro joints (compared to traditional ENEPIG), both of which favor retarding Cu pad depletion and enhancing joint electromigration reliability. Based on the results of the present studies, we concluded that the ultrathin-Ni(P)-type ENEPIG surface finish significantly mitigates electromigration-induced damage to Cu traces while improving micro joint structural integrity and electrical reliability.

 

Bio:
Student from Department of Aerospace and Systems Engineering, Feng Chia University, Taichung 407, Taiwan, R.O.C

Abstract:
To alleviate the high computational cost, extensive modeling effort, and accuracy limitations associated with conventional simulation-driven machine learning, such as artificial neural network (ANN), random forest (RF), support vector machine (SVM), gaussian process regression (GPR), and convolutional neural network (CNN), this study aims to introduce a systematically optimized ensemble stacking learning (ESL) framework, the performance of which is driven by a structured optimization process that selects the best combination of base ML model candidates, an appropriate meta-learner, and finely tuned hyperparameters. This framework involves training multiple base ML models (e.g., ANN, RF, SVM, GPR, CNN) along with a meta ML model that learns to integrate their predictions. The proposed ESL framework is evaluated by applying it to accurately and effectively predict the process-induced warpage of an SiC power MOSFET module during manufacturing. To characterize the process-induced warpage, a finite element analysis (FEA)-based process modeling technique is developed. The effectiveness of the proposed ESL framework is demonstrated by comparing its predictions with those obtained from an ANN trained on a larger dataset. The results confirm that the proposed ESL framework delivers significantly higher prediction accuracy than any individual base ML model, thereby substantially reducing reliance on computationally intensive simulations.

 

Bio:
Zi-Chen Fang received the B.Sc. degree in Department of Biomechatronic Engineering from National Ilan University, Ilan, Taiwan, R.O.C., in 2023, He is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
The dielectric resonator antenna (DRA) possesses lower losses and higher efficiency compared to metal antennas at high microwave and millimeter-wave frequencies. DRAs are commonly used in compact portable wireless devices due to the ease of packaging and integration. A DRA is typically constructed of ceramic material for its high-Q potential that radiates electromagnetic energy transition from a higher dielectric constant to air. In this study, various DRA geometries are fabricated on organic substrates by using semiconductor molding organic materials and processes. A hexagonal-shaped DRA is proposed for investigation. For comparison, a rectangular DRA of similar dimensions and the same height is also considered. The configurations of both the hexagonal and rectangular DRAs with microstrip feedlines are illustrated in Figure 1. The designed dimensions of the hexagonal and rectangular DRAs are proposed to be simulated for comparison.
Both DRA shapes are fed by a microstrip line on the same substrate material, sharing the same dielectric constant. The simulation frequency range is set between 24 and 32 GHz, centered at 28 GHz. The purpose of the study is to explore the effect of geometric shape on resonant frequency and bandwidth characteristics. Preliminary simulated results of the reflection coefficients, S11, are presented in the Fig. 2, where the resonant frequencies of the hexagonal and rectangular DRAs are compared. These geometric differences cause DRAs to exhibit distinct resonant modes and radiation field patterns. Further optimization of the hexagonal DRA geometry will be explored as a promising strategy to improve antenna performance in the millimeter-wave frequency range. Electric field distributions, gain, and radiation patterns for the proposed DRAs will also be revealed. Additional performance metrics, including resonant frequency, −10 dB impedance bandwidth, radiation patterns, and gain, will be presented in subsequent article.

 

Bio:
Zhao Heng-Chen received the B.Sc. degree in mechanical engineering from National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan, R.O.C., in 2023, She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
ABSTRACT
Dielectric resonator antenna (DRA) offers advantages such as low metallic loss, high efficiency, broadband characteristics, and easy manufacturing, which is very suitable for modern wireless communication systems in millimeter wave applications. In this work, semiconductor molding material and processes are used to fabricate DRAs of various shapes on the organic substrates. A conical and truncated-conical DRAs are proposed for investigation. A truncated cone is a shape formed by cutting off the apex to be a plane parallel to the base (bottom plane) or, equivalently, perpendicular to the height. For comparison, a cylindrical DRA with the same base diameter and height as the conical and truncated-conical structures is also considered. Figures 1 (a) and (b) illustrate the conical and truncated-conical DRAs, respectively, which are fed with a microstrip feedline on the same substrate of the dielectric constant different with the proposed DRA’s material. On count of the configurations of the conical and truncated-conical DRAs are proposed to do simulation.
The simulation frequency range is set between 20 and 50 GHz, centered at 28 GHz. The purpose of the study is to explore the effect of geometric shape on resonant frequency and bandwidth characteristics. Preliminary simulated results of the reflection coefficients, S11, for both proposed DRAs compared with the cylindrical DRA of the same base diameter are presented in the Fig. 2. The conical and truncated-conical DRAs demonstrate higher resonant frequencies than the cylindrical counterpart. The different resonant modes exhibit based on the facts of the DRA's geometric transformation and radiate the different EM-field patterns depending on their shape. Further studies on optimizing the geometry of various shaped DRAs will be presented as an effective approach for enhancing antenna performance in the mm-wave frequency range. The electric field distribution inside the proposed DRAs and antenna gain, radiation patterns will be revealed. Further performance metrics, including −10 dB impedance bandwidth, radiation gain, and radiation patterns will be discussed in the subsequent full paper.

 

Bio:
Tzu-Ching Sun received the B. Sc. degree in electrical engineering from National Taiwan Ocean University, Keelung, Taiwan, R.O.C., in 2023. She is currently working toward the M. S. degree in Institute of Advanced Semiconductor Packaging and Testing, College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
In package substrate layout design, an area typically defined by a "keep-out" zone is enforced to be free of copper or any other board feature, such as traces, pours, vias, and even component pads within this zone. In the high-speed substrate layout, the copper keep-out is a designated area where other board copper features are prohibited to minimize electrical interference and improve signal integrity. High speed signals are susceptible to signal reflections, crosstalk, and impedance variations. This is crucial for signal integrity, minimizing unwanted coupling, such as crosstalk and parasitic inductive and capacitive effects, and ensuring proper impedance control to reduce signal reflections. By maintaining keep-out zone in substrate layout, these abovementioned impacts are minimized, leading to a stable and reliable signal transmission. This study explores signal integrity related to the presence or absence of a copper keep-out zone, specifically focusing on signal integrity of the differential-pair routing traces in the adjacent layers. Ansys HFSS software solver is used to simulate the transmission loss of the differential-pair signals and the degree of mutual interference with the adjacent differential-pair signals with and without the copper keep-out.

 

Bio:
Yu-Hur Shih received the B.Sc. degree in electronic engineering from National Ilan University, Ilan, Taiwan, R.O.C., in 2023, She is currently working toward the M.S. degree in Institute of Advanced Semiconductor Packaging and Testing College of Semiconductor and Advanced Technology Research at National Sun Yat-sen University, Kaohsiung.

Abstract:
Dielectric resonator antenna (DRA) possesses some attractive features such as low loss, small size, wide bandwidth, ease of excitation, and high degree of design freedom to meet the demands for applications in millimeter-wave (mm-wave) mobile communication. In the mm-wave frequency range, increased propagation losses and reduced effective aperture size necessitate antennas with higher efficiency and improved directionality to maintain overall system performance.
Dielectric Resonator Antennas (DRAs) have emerged as highly promising candidates for wireless and mobile mm-wave applications due to their advantages in efficiency, miniaturization, and frequency stability. DRAs utilize high-permittivity, low-loss dielectric materials as resonators and radiate electromagnetic energy through their intrinsic resonant modes. One of the most crucial factors affecting DRA radiation performance is its geometric configuration, which directly influences mode distribution, field patterns, impedance matching, bandwidth, and gain.

We present the configurations of the proposed trapezoidal and pyramidal (prism) DRAs. The trapezoidal DRA has a bottom side length of DL, side width of DLW, a top side length of DL, side width of DUW, a height of Dh, and a dielectric constant of erDRA (= 21), loss tangent of 0.008. It is placed at the center of a square substrate with a side length of SW, thickness of h, dielectric constant of 2.2, and loss tangent of 0.009. A pyramidal (prism) DRA with a same side length of DL, a height of Dh, and the same dielectric constant of erDRA as the trapezoidal type is also placed at the center of a square substrate that has a same size as trapezoidal DRA, for comparison. A rectangular DRA is also included and simulated for comparison. Among the various known geometries, the rectangular DRA is the most commonly used due to its simple structure and ease of fabrication. However, its uniform top and bottom surfaces often lead to modal limitations, resulting in narrower bandwidth and lower gain. To address these limitations, this study investigates tapered modifications to the top surface of the rectangular DRA, transforming it into trapezoidal and pyramidal (or prism) shapes. Specifically, by reducing the top width of the original rectangular DRA to 2 mm (trapezoidal) and 0 mm (prism), the radiation characteristics and gain are expected to improve significantly.

 

Bio:
Department of Chemical Engineering at Sungkyunkwan University. My research focuses on multifunctional flexible devices, including stretchable electronics, soft sensors, and bio-interfacing platforms. I am particularly interested in integrating electrical functionality with mechanical compliance for next-generation wearable and implantable systems. My recent work includes the development of liquid metal-based circuit architectures and textile-integrated electronic devices for soft robotics and biomedical applications.

Abstract:
Organic electrochemical transistors (OECTs) have garnered significant attention as emerging components for a wide range of bioelectronic applications, including real-time biological sensing, electrophysiological signal recording, and neuromorphic information processing. Due to their ability to operate efficiently in aqueous environments—where most biological reactions naturally occur—OECTs are particularly well-suited for seamless integration with living tissues and biofluids. One of the critical aspects in optimizing the performance of OECTs is a deeper understanding of how electrolyte materials interact with the organic semiconductor channel. In particular, ion transport within the electrolyte governs electrochemical doping and screening effects that directly modulate the channel conductivity and switching characteristics.

To enhance device sensitivity, stability, and signal transduction, materials with high ionic mobility such as ion gels and ionic liquids have been widely explored. However, despite numerous studies reporting performance improvements via the introduction of novel ion-conducting materials or surface modifications, the detailed mechanism of pre-diffusion-induced electrochemical effects remains poorly understood. In this study, we introduce a new class of solid-state, choline-based ionic electrolytes and systematically investigate the pre-diffusion effect of [Ch][Ace] ionic liquids on the electrical performance of OECTs. The choline-based ions serve not only as efficient charge transporters but also as functional dopants that can interact with charged species within the conducting polymer matrix. This dual functionality enables modulation of ionic screening and capacitance behavior, ultimately leading to an optimized channel environment.

Our results demonstrate that the presence of [Ch][Ace] promotes a shift in the gate voltage of maximum transconductance toward 0 V, which significantly reduces power supply noise and enhances the quality of recorded biological signals. Specifically, the system achieves high signal-to-noise ratios in electrocardiogram (ECG) monitoring without the need for external biasing or amplification circuitry. Furthermore, the choline-based solid electrolyte exhibits excellent biocompatibility, non-volatility, and mechanical stability, making it a compelling candidate for long-term use in wearable or implantable bioelectronics. The findings presented here not only highlight the functional potential of choline-derived ionic materials but also provide insight into the pre-diffusion mechanisms that govern ion–channel interactions in OECTs, paving the way for the development of next-generation organic biosensors with improved reliability, sensitivity, and user comfort.

 

Bio:

Cooper Li is a Signal Integrity Engineer at Advanced Micro Devices (AMD), specializing in high-speed digital design and signal integrity analysis for next-generation data center platforms. With over eight years of industry experience, he has led and contributed to numerous high-performance system designs, including data center servers and Ethernet switches. Cooper holds a Master’s degree in Electronics and Communications Engineering from.

Abstract:

With the rapid advancement of artificial intelligence (AI) and machine learning (ML) applications, PCI Express (PCIe) technology has emerged as critical infrastructure due to its superior bandwidth, low latency, and reliable high-performance communication channels capable of managing intensive parallel computing demands. As industry requirements continue to escalate, accelerating the adoption of next-generation PCIe specifications has become imperative; however, numerous signal integrity (SI) challenges must first be addressed to achieve these higher performance targets reliably. This paper investigates key SI issues associated with high-speed signal breakout designs from dense CPU or GPU pin fields, emphasizing the significant influence of breakout trace impedance, spacing constraints, and crosstalk noise in high-layer-count printed circuit board (PCB) stackups. Through comprehensive simulation-based performance analyses, we compare current-generation PCIe Copper Link channel solutions against anticipated next-generation demands, with particular emphasis on the implications of Pulse Amplitude Modulation with four levels (PAM4) signaling and the substantially increased operational frequencies introduced in PCIe 6.0 and 7.0 standards. Our findings demonstrate that meticulous optimization of breakout impedance, careful management of signal routing geometry, and strategic layer assignments can effectively mitigate noise coupling, reflections, resonance effects, and other signal degradation mechanisms. These optimizations lead to significant improvements in channel performance, including enhanced signal-to-noise ratio (SNR) and overall signal quality. The methodologies and design guidelines presented in this paper provide essential insights and practical recommendations for achieving robust, high-quality signal integrity in advanced PCIe interconnect implementations, facilitating the successful deployment of PCIe 7.0 at speeds up to 128 Gbps per lane in future data center and AI computing platforms.

 

Bio:

Katie Tsai is a senior Signal Integrity engineer with over ten years of experience in high-speed signal design, simulation, and validation across both system-level and 3DIC domains. She has assisted customers in establishing 3DIC analysis flows involving advanced packaging technologies such as CoWoS and InFO. She currently works at AMD as a Signal Integrity Application Engineer, responsible for simulation optimization of high-speed/DDR interface platforms and supporting customer-side R&D and debugging.

Abstract:

"As DDR interfaces advance toward higher data rates, CPU breakout (BO) design becomes increasingly critical. Among the available layout techniques, tabbed routing is widely used in breakout routing. However, whether tabbed routing is truly necessary for maintaining signal integrity remains an open question. Existing design flows often rely solely on simulation, lacking validation against real-world implementation.
This paper presents a structured validation methodology that evaluates the necessity of tabbed routing through both simulation and measurement. S-parameters are extracted from test boards with and without tabbed routing, and eye diagram analysis is conducted using the S2eye tool. We compare simulation-based and measurement-based S2eye results to assess the correlation and highlight the practical implications of layout choices.
The evaluation includes both simulation and validation results for key performance metrics such as Insertion Loss (IL), Return Loss (RL), Far-End Crosstalk (FEXT), and Time Domain Reflectometry (TDR), along with eye diagram analysis using the S2eye methodology. These metrics provide a comprehensive view of how tabbed routing influences signal quality across both frequency and time domains.
This analysis highlights how the presence or absence of tabbed routing affects key signal integrity metrics, providing valuable insights into its actual benefits and limitations in practical designs."

 

Bio:

Jun Wei is a Signal Integrity Engineer at SHPE AMD, specializing in signal integrity with a focus on high-speed input/output (HSIO) interfaces, particularly PCIe Gen5 and Gen6 standards. In this role, he is dedicated to ensuring the performance and reliability of advanced communication interfaces, optimizing designs to mitigate signal degradation and enhance overall system functionality.

Abstract:

"With the growing demand for higher data rates in digital communications, the shift from Non-Return to Zero (NRZ) signaling to Pulse Amplitude Modulation (PAM4) signaling is essential for maximizing bandwidth efficiency. PAM4 effectively doubles the data rate by using four signal levels, enabling greater data transmission within the same bandwidth compared to NRZ. However, PAM4 signal amplitude is reduced to one-third of NRZ, resulting in approximately 9.6 dB degradation. This amplitude reduction makes PAM4 signaling is more susceptible to noises such as power noise and crosstalk that can adversely affect signal integrity at the receiver [1].
This paper investigates crosstalk effects—specifically Far-End Crosstalk (FEXT) and Near-End Crosstalk (NEXT) - in high-density PAM4 Serializer/Deserializer (SerDes) implementations on printed circuit board (PCB) pin-field breakouts. Our analysis focuses on crosstalk interactions between NRZ aggressors and PAM4 victims while considering trace-to-via coupling (T-V coupling). This coupling occurs when long shallow-layer NRZ signals cross over SerDes PTH vias, presenting design challenges in densely packed PCB layouts (Fig. 1).
Through theoretical modeling, we quantified degradations in signal quality due to crosstalk in both NRZ and PAM4 systems. Our findings show that the signal-to-noise ratio (SNR) can be significantly compromised, resulting in an increase of bit-error rates (BER) in high-density configurations [2]. We investigated FEXT and NEXT mechanisms to understand how the characteristics of PAM4 may worsen these issues further.
The simulation setup involves extracting six pairs of channels using a 3D EM simulator (Ansys Electronics Desktop). One link operates in the shallow layer with NRZ modulation at 16 Gbps (PCIe Gen 4), while five PAM4 links in deeper layers operate at 64 Gbps (PCIe Gen 6). The end-to-end channel simulations were performed using Keysight ADS software, processing 1 million bits with optimized presets to ensure the best performance (Fig. 2). Our results indicate a 25% performance improvement when the NRZ channel is disabled, highlighting its detrimental impact on overall margin due the crosstalk impact (Fig. 3).
To address crosstalk challenges, we propose optimization strategies, including adjusting PCB routing to minimize T-V coupling. However, density requirements and fixed pin assignments limit this feasibility. Thus, changing the routing pattern from Model #2 to Model #1 achieves approximately 70% reduction in T-V coupling (Fig. 4A and B). Our comparative analysis reveals a maximum delta of 9 dB between routing models, underscoring the effectiveness of these optimization strategies (Fig. 5 and Fig. 6).
Additionally, we advocate for asymmetric pin field routing (Fig. 7) and propose CAD tools to automate the layout process, allowing adjustments to trace-to-via distances, enhancing layout efficiency while considering manufacturing capabilities.
In summary, this study provides valuable insights into the crosstalk challenges in high-density PAM4 SerDes PCB designs, emphasizing performance implications and offering critical mitigation strategies for optimizing high-speed data transmission in next-generation communication systems."

 

Bio:

Aik Hong is a highly skilled Signal Integrity Engineer with 6 years of experience in LSIO and DDR memory interfaces which focus on critical areas such as connector modeling, 3D modeling methodology, comprehensive channel analysis, and PCB channel optimization. He is passionate about solving complex SI challenges and contributing to DDR5 and DDR6 solutions.

Abstract:

"Achieving high data rates on DDR memory in modern electronics hinges on robust signal integrity, particularly in systems utilizing dual-inline memory module (DIMM) connectors. These connectors play a pivotal role in maintaining signal integrity, especially in DDR5 2 DIMM-per-Channel (2DPC) systems, which are designed to enhance memory capacity. The branch topology inherent in 2DPC systems introduces inter-symbol interference (ISI), with DIMM connectors contributing to parasitic effects such as inductance and capacitance. These effects can lead to signal reflections, material losses, and crosstalk, ultimately causing bit errors, data corruption, and potential system failures. Therefore, accurate connector modeling is essential for designers to simulate and optimize the signal integrity performance of 2DPC systems.
Incorporating a DIMM connector into a design necessitates a precise simulation model to achieve accurate end-to-end system performance. This is particularly critical for high-bandwidth applications like DDR5 MRDIMM 2DPC 1of2 11.2G enablement. Key considerations include configuring the return path, setting up excitation ports, and accurately representing the mating PCB stack-up. The challenge lies in the seamless integration of the connector and PCB models, as variations in fringe fields make it difficult to delineate where the connector ends and the board begins. To accurately model signal reflection, return loss (RL), insertion loss (IL), and crosstalk, a uniform transmission line is necessary. The board-level fan-out, pad stack, and return pin connections significantly influence the overall performance of the DIMM connector, often as much as the connector itself. Thus, having precise models to simulate the DIMM connector alongside the PCB DIMM pad/vias models is crucial.
The proposed methodology has the potential to enhance system-level signal integrity margins, through accurate modeling and reduce pessimism in the model. Potentially improving performance by more than one speed bin. This is a key enabler for achieving 11.2G in MRDIMM 2DPC 1of2 topologies and 8G in RDIMM 2DPC 1of2 configurations. This paper focuses on the connector modeling methodology, examining the impact of simulated eye margins on RDIMM and MRDIMM 2DPC systems with and without proper DIMM connector modeling. Additionally, it correlates 3D models against actual lab measurement data in the frequency domain.
In conclusion, the paper outlines future steps to achieve robust modeling in the DIMM region, including the integration of first and second DIMMs with DIMM-to-DIMM routing. Active lab correlation will also be a part of future endeavors, ensuring that the models align with real-world performance. This comprehensive approach aims to enhance the accuracy and reliability of DIMM connector modeling, ultimately supporting the development of high-performance electronic systems."

 

Bio:

Current Position:  Global Sr. Packaging Account TD Head

Organization:  Applied Materials

 

Job Experience:

Over 35 years of job experience in semiconductor industry, especially focusing on advanced packaging technologies.

Packaging Research Development Center, SPIL (in ASX)

Product Development, Quality, & Sales, bumping RD, Amkor Taiwan

Process & Quality, TI-Acer memory company

 

Award:

2018-2025, SEMICON Taiwan packaging industry contribution award

Invited as SEMICON Taiwan packaging committee co-chairman

Invited as IMPACT packaging committee executive co-chairman

Invited as TILA (Taiwan Intelligent Leader Association) chairman

Invited as invited / keynote speakers in over 50 packaging symposium in the world.

Abstract:

 

Bio:

Vincent has accumulated over 35 years of experience in Technology Development, Operations, Business, Sales, and Marketing, demonstrating success at renowned companies such as IBM, Amkor, ASE, TSMC, and GLOBALFOUNDRIES. He joined Applied Materials in 2016.
Currently leading Technology Pathfinding, Corporate, and Business Development within the Advanced Packaging and ICAPS division at Applied Materials, Vincent is responsible for establishing strategic alliances and partnerships essential to advancing technology for future product solutions. He oversees all aspects of critical technology transitions pertaining to Heterogeneous Integration, next-generation silicon integration, and volumetric scaling associated with advanced packaging technologies, including 3DIC Heterogeneous Integration.
In addition, Vincent serves on the Advisory Board of BESI, a company that specializes in advanced packaging equipment, and holds the position of Vice-Chairman at iNEMI, a consortium dedicated to the global electronics manufacturing supply chain.
Vincent holds a degree in Pure and Applied Sciences from Champlain Regional College and a Bachelor of Engineering degree from Concordia University. He is the author and co-author of over 40 patents in the field of advanced semiconductor packaging and heterogeneous integration.

Abstract:

 

Bio:

Deepak Kulkarni is a Senior Fellow at Advanced Micro Devices (AMD), where he leads the Instinct and Optics Technology Development team. In this role, he develops heterogeneous architectures for AMD’s AI accelerator products and oversees Photonics technology development.
With twenty years in technology development, Deepak has led the development of several innovative technologies such as panel-level fan-out, Embedded Multi-die Interconnect Bridge (EMIB), Elevated Fan-Out Bridge (EFB), and 3.5D packaging solutions. Recognized with top awards at both AMD and Intel, and a frequent voice on high-level industry panels, Deepak brings both technical depth and strategic vision to advancing heterogeneous integration.
Deepak Kulkarni's technical interests cover Co-packaged Optics, Panel-level packaging, and design- technology co-optimization. He holds forty patents and has published over twenty papers. He earned his PhD in Mechanical Engineering with a minor in Computational Science from the University of Illinois at Urbana-Champaign.

Abstract:

The ever-growing demand for AI computing power is propelling rapid advancements in packaging technology. AMD is at the forefront of these innovations, leading the way in 2.5D, 3D, and 3.5D packaging technologies. Beyond these advancements, we are pioneering the transformation of packages into complete systems by integrating components such as co-packaged optics.

This presentation will delve into the limitations of wafer-scale and explore the emerging trend of panel-scale packages that integrate entire systems. The discussion will emphasize the intersection of architecture, optics, and thermal design, illustrating how these elements converge to meet the increasing demands of high-performance, energy-efficient applications.

 

Bio:

Yu-Hua Chen received the Ph.D. degree in Chemistry from National Taiwan University in 2001. Since 2001, he has been with the Industrial Technology Research Institute (ITRI),Electronics and Optoelectronic Research Laboratories (EOL), as a member of the Packaging Technology Division in 2001~2012. Since 2012, he joined the Unimicron to develop the next generation substrate technology.

Abstract:

As the demand for energy-efficient, high-performance computing continues to accelerate, heterogeneous integration has emerged as a key enabler for next-generation electronic systems. Advanced substrates play a crital role in this evolution, serving as the foundational platform for integrating diverse chiplets—including logic, memory, RF, and photonics—into a single package. This presentation explores the latest innovations in substrate technologies. We will discuss the development of advanced substrate materials, and the adoption of advanced build-up layers and redistribution layers (RDLs). Emphasis will be placed on how these substrates facilitate chiplet-based architectures and enable system-level performance improvements in AI, HPC, and edge computing applications. By advancing substrate capabilities, we unlock new possibilities for heterogeneous integration, driving innovation across the semiconductor ecosystem.

 

Bio:

Naresh Kumar Asokan is Global product Manager in Panel Packaging and Solutions Group.
Naresh has more than 17 years of experience in semiconductor equipment industry and joined Applied Materials in 2020 following the acquisition of Tango Systems, where he led Engineering and product Marketing for PVD products. He has over 10 years of experience working on capital equipment development for substrate technologies.
He holds a master’s degree in Busies Management and B. Tech in Mechanical engineering from Anna University.

Abstract:

Introduction to Topaz PVD / Etch tools for panel level processing

 

Bio:

Co-invented digital lithography, acquired by Applied Materials in 2014. Invented Scattering Bars Optical Proximity Correction acquired by ASML in 1999, widely adopted for DUV & immersion lithography. He holds 100+ patents, dual MS from RIT, NY, USA.

Abstract:

International Data Corporation (IDC) projects the AI Supercycle will accelerate semiconductor revenue to $1 trillion before 2029—years earlier than expected. As monolithic transistor scaling approaches physical limits with rising costs, performance scaling now depends on heterogeneous integration to meet HPC demands. Emerging 2.5D–3.5D architectures impose unprecedented lithography challenges: imaging fields >6X reticle size (>100 mm × 100 mm) without stitching errors, 2 µm line/space RDL features with tight CD uniformity, and per-unit overlay correction for >10 µm placement shifts on warped substrates often exceeding 12 mm. Conventional steppers and LDI tools cannot meet these requirements simultaneously. Applied Materials’ Digital Lithography Technology (DLT) has already demonstrated 2 µm RDL patterning on production panels, achieving <10% CDU across 515 mm × 510 mm glass or CCL substrates. This talk previews the next-generation DLT platform, which expands design and process windows while improving overlay robustness. Key innovations include high-speed scanning alignment combined with Digital Dynamic Connection™ (DDC) to achieve design-intent overlay on shifted unit packages, improving yield. DDC enables per-unit wiring alignment across multiple masking layers for better design-rule compliance with minimal throughput impact.

 

Bio:

Bernhard Mueller has been active in the SEMI industry since 1995, beginning his career as a SEMI metrology application engineer. Since 2011, he has led application development at Applied Materials YTG team, focusing on the implementation of electron-beam based measurement and inspection technologies in the display industry and SEMI heterogeneous integration processes.

Abstract:

Test and inspection in advanced packaging face challenges due to shrinking feature sizes, complex 3D structures, and heterogeneous integration, which limit the effectiveness of traditional optical methods. Electron beam (e-beam) technology overcomes these limitations by offering nanometer-scale resolution and material-sensitive contrast. It enables precise defect detection, overlay measurement, and CD metrology even in high-aspect-ratio and buried structures. E-beam systems also support non-contact inline inspection with high throughput. This makes them essential for ensuring yield and reliability in cutting-edge semiconductor packaging.

 

Bio:

Shaw Fong currently serves as the Principal Engineer at one of the Kulim Campuses of Intel Malaysia. With ~24 years of extensive experience in the semiconductor industry, he has held various positions that encompass a wide range of technical domains including packaging processes, assembly, testing, and material technology development. Throughout his career, Shaw Fong has played a pivotal role in advancing multiple packaging and product development initiatives, with a particular focus on warpage development and mechanical testing. His technical acumen and leadership have significantly contributed to innovative solutions and improved efficiencies within these critical areas.

In 2023, Shaw Fong was honored with the prestigious IEEE/EPS William Chen Distinguished Award, recognizing his significant contributions to the IEEE in driving advancement in semiconductor assembly and testing field. He has been nominated to the IEEE/EPS Board of Governance and serves as Region-10 Program Director. He is also engaging in IEEE Malaysia Section as the Executive Committee (Industrial Relations). Additionally, he is an active Committee Member of both the Electronic Engineering Technical Division (eETD) and the Material Engineering Technical Division (MaTD) of the Institution of Engineers Malaysia (IEM). His recent designation as a Professional Engineer by the Malaysia Board of Engineers (BEM), along with his advisory roles with various local universities, underscores his unwavering commitment to engineering excellence and education. Shaw Fong holds a total of 12 combined patents and trade secrets, and he is a key driver of technical innovation at Intel Malaysia, having achieved over 90 technical publications. Outside of his professional endeavors, Shaw Fong is a devoted family man with two sons and a passionate sports enthusiast, particularly in football, where he proudly supports Liverpool FC.

Abstract:

The global semiconductor industry is undergoing a critical transformation, driven by the convergence of advanced packaging, heterogeneous integration, and AI-centric applications. At the forefront of this evolution is the Heterogeneous Integration Roadmap (HIR), developed by the IEEE Electronics Packaging Society (EPS), which outlines a 15-year vision for integrating diverse components—logic, memory, sensors, and photonics—into compact, high-performance systems. HIR serves as a pre-competitive guide for industry, academia, and governments, fostering collaborative innovation and standardization across the semiconductor value chain [1].

Malaysia is aligning its national ambitions with this global framework through the National Semiconductor Strategy (NSS), launched in May 2024. This ten-year, three-phase roadmap aims to elevate Malaysia from a traditional OSAT hub to a global leader in IC design, advanced packaging, and wafer fabrication, supported by RM25 billion in fiscal incentives and a target of RM500 billion in investments [2][3]. Regional ecosystems are critical to this transformation. Penang’s “Silicon Design @5km+” initiative, Selangor’s SIDEC and ASEM programs, and Sarawak’s SMD Semiconductor—home to Borneo’s first Chip Design Centre—are building robust design and packaging capabilities [4].
These efforts position Malaysia as a strategic partner for Taiwan, whose semiconductor leadership complements Malaysia’s strengths. Opportunities for collaboration include joint R&D in heterogeneous integration, talent exchange, and cross-border investment. By aligning Malaysia’s NSS with the IEEE HIR, both nations can co-create a resilient, innovation-driven semiconductor ecosystem that supports global supply chain diversification and regional technological sovereignty.

 

Bio:
Yeong Seok Ham is currently a Ph.D. student in the Department of Mechanical Engineering at KAIST, Republic of Korea. His research focuses on mechanical reliability of semiconductor interconnects, including interfacial fracture energy measurements and reliability assessment of ultra-low k dielectric materials. In addition to BEOL structures, he is also conducting research on interfacial adhesion and reliability evaluation of advanced packaging materials such as underfill-glass and underfill-Cu interfaces. His work aims to improve interfacial adhesion and structural robustness in advanced semiconductor devices.

Abstract:
Over the past several decades, the semiconductor industry has undergone remarkable advancements in the scaling of integrated circuits and the increase in transistor density, driving significant improvements in the performance of microelectronic devices. As device dimensions continue to shrink, the line width and spacing in back-end-of-line (BEOL) interconnects have also been reduced, leading to an increase in resistance-capacitance (RC) delay, which hampers the signal transmission speed of chips. To mitigate RC delay, ultra-low k (ULK) dielectrics have been employed in intermetal dielectric (IMD) layers, with carbon-doped silicon oxide (SiOC:H) being one of the most commonly used ULK dielectrics. However, the high porosity of ULK poses mechanical reliability challenges, including cracking and interfacial delamination at the interface with SiCN (etch stop layer). These mechanical failures occur under varying fracture modes, as the mode mixity of applied loads depends on factors such as the position within the interconnect structure, the stack configuration, and the material properties. Thus, the quantitative evaluation of fracture energy under different fracture modes is crucial for enhancing the mechanical reliability of SiCN-ULK interfaces.

In this study, the fracture energy of SiCN-ULK interfaces under three plasma treatment conditions (Pristine, H2, and NH3) was quantitatively measured using fracture mechanics-based experiments. Double cantilever beam (DCB) test and four-point bending (FPB) test were conducted to measure the fracture energy Gc under pure mode I and mixed-mode loading conditions, respectively. Fracture surface analysis were conducted using optical microscopy (OM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), and focused ion beam- scanning electron microscopy (FIB-SEM) to elucidate the fracture mechanism depending on fracture modes.

As a result of DCB test, there was no significant increase in Gc regardless of the plasma treatment conditions. In contrast, the results of the FPB test showed that the Gc was increased by approximately 43.1% by H2 plasma treatment, and by approximately 67.5% by NH3 plasma treatment, compared to the pristine condition. From the fracture surface analysis, the discrepancy in results between the DCB test and the FPB test has been attributed to the difference in crack paths under different fracture modes. This indicates that while plasma treatment is effective in improving mechanical reliability under mixed-mode loading, it has a limitation in enhancing the mechanical reliability against cohesive failure under pure mode I loading.

This study provides insights into the influence of plasma treatment on the mechanical reliability of SiCN-ULK interfaces under varying fracture modes, contributing to the design of mechanically robust BEOL interconnects capable of withstanding diverse fracture conditions.

Keywords: Mechanical reliability, Back-end-of-line, Ultra-low k dielectrics, Fracture energy, Fracture mode, Crack path difference

Acknowledgements: This work was supported by Samsung Electronics Co., Ltd (IO240522-10052-01)

 

Bio:
Ming-chun Hsieh is a researcher at Flexible 3D System Integration Laboratory and a PhD student at the university of Osaka, Japan. She has over 10 years of experience in packaging reliability analysis, specializing in electron microscopy techniques and the development of metal pastes. Her research focuses on advancing packaging technologies through materials characterization and reliability assessment.

Abstract:
With the increasing demand for higher packaging density in modern electronics, continuous innovations are being made in the manufacturing technologies, constituent materials, and structural designs of packaging substrates. Consequently, engineers and researchers face growing challenges in evaluating the interconnection reliability of newly developed substrates with diverse architectures. Failures in packaging substrates are widely recognized to be strongly influenced by mismatches in the coefficient of thermal expansion (CTE) among the layered structural materials. Although various reliability evaluation methods have been proposed to simulate damage occurring during manufacturing and in-field operation, a widely applicable and efficient testing approach has yet to be fully established. The thermal cycling test (TCT) is commonly employed to assess interconnection reliability in semiconductor packaging substrates. However, it is inherently time-consuming. To reduce the test duration, increasing the upper temperature limit is a frequently adopted strategy. Nevertheless, the selection of this upper temperature limit is often based on empirical practices rather than systematic criteria. In this study, we focused on the glass transition temperature (Tg) of the build-up film in the packaging substrate, as its physical properties—including CTE—undergo significant changes when the temperature exceeds this threshold. TCT was performed under two thermal conditions: one with the upper temperature below Tg, and another above Tg. In parallel, substrate warpage was experimentally measured at 150 ºC and 175 ºC using a 3D metrology system.
Two three-layer stacked packaging substrates were intentionally fabricated using identical materials and dimensions, with the build-up film having a Tg of 153 ºC, but differing in interconnection reliability. This difference was introduced by applying distinct electroless Cu plating methods at the micro-via bottom. Specifically, substrate A incorporates an electroless Cu plating layer with a higher density of voids—i.e., structural defects—than substrate B. Both substrates were subjected to TCT under the two conditions: Condition 1, cycling between -55 ºC and 150 ºC; and Condition 2, cycling between -55 ºC and 175 ºC, with each temperature held for 15 min per cycle. The upper temperature limits were selected with reference to the Tg of the build-up film.
Under Condition 1, substrate B exhibited a Life(10%)—defined as the cycle count at which 10% cumulative failure occurs—of approximately 300 cycles, while substrate A reached approximately 900 cycles, consistent with the expected difference in reliability. However, under Condition 2, where the upper temperature exceeded the Tg of the build-up film, the Life(10%) values of both substrates converged to approximately 100 cycles, making it difficult to distinguish their relative reliability. These TCT results will be analyzed in conjunction with the measured substrate warpage shown in Fig.1 during our presentation to evaluate whether the Tg of the build-up film can serve as a meaningful reference when selecting the upper temperature limit in TCT-based reliability testing.

 

Bio:
I am Shen-Yu Yang. I come from Tainan, Taiwan and graduate with a master's degree in Institute of Material Science & Engineering from National Central University. In graduate school, I was major in solid oxide fuel cell. After that, I have been in WNC Corporation, WNC provides comprehensive technical support in RF antenna design, software design, hardware design, mechanical design, system integration, user interface development, and product testing & certification. I am a technical supervisor in Advanced Mfg. Process Development Center and involved in advanced manufacturing processes about molding process and EMI shielding. In addition, I participate in radar and antenna package including material and process selection. Besides actual products manufacturing, I have also used simulation tool to simulate PCB/PCBA warpage. Based on PCB/PCBA simulation tool, I can know how to modify every PCB layer circuit. It is an honor to attend Impact 2025.

Abstract:
The performance demands for automotive electronic products are steadily increasing, leading to strict reliability requirements. The Network Access Device (NAD) module is a key hardware component that enables wireless communication and connectivity in vehicles, presents coplanarity issue due to its relatively large dimensions. As the NAD module must be mounted onto the main board to function properly, there is an increasing need to meet tighter warpage specifications. Additionally, to satisfy electromagnetic interference (EMI) shielding requirements, a metal structural component referred to as the shielding frame and cover, is mounted onto the printed circuit board (PCB). The combined effects of this shielding structure and modularized PCBA result in a more complex warpage behavior. In this study, a finite element analysis (FEA) approach is applied to simulate the structural behavior of the NAD module with an attached shielding frame at the module level. The mechanical model consists of the PCB, mounted components, traces, shielding frame, and ball grid array (BGA). To accurately predict PCB warpage, key simulation parameters, such as contact definitions, element birth and death techniques, and reference temperatures, are carefully defined because they significantly influence the warpage contour and magnitude. The simulation conditions are categorized into two groups: one investigates the reference temperature of the shielding frame, and the other examines the modeling for solder structure underneath the shielding frame. The simulation results based on the finalized settings are then compared with actual warpage measurements obtained using a 3D optical profiler. The study aims to evaluate the influence of the shielding frame on PCB warpage behavior and provide insights for future design optimization.

 

Bio:
N/A

Abstract:
In recent years, as mobile devices and high-frequency communication components continue to evolve towards thinner, smaller, and higher performance, electronic packaging technology has been facing more severe reliability challenges. Although the Flip-Chip structure has become an indispensable mainstream technology in high-performance applications, its mechanical lifespan under thermal cycling environments remains a concern. When the chip is connected to the substrate through solder balls, the difference in the coefficient of thermal expansion (CTE) between the chip and the package substrate leads to repeated deformation during thermal cycling, resulting in solder ball fatigue, crack propagation, and even complete package failure. Typical solutions rely on full filling underfill to provide overall stress redistribution and mechanical support. However, underfill technology still presents several limitations, such as long dispensing and curing times, difficulty in rework, and challenges in flux flow control, which can result in voids or packaging defects. To address these issues, strategies involving "localized reinforcement" and "material reduction" have begun to gain attention. This study focuses on the potential of the epoxy flux adhesion method in wafer-level chip scale packaging (WLCSP). Unlike full-coverage underfill, epoxy flux uses selective filling to reinforce only the areas around the solder balls where stress tends to concentrate. This approach strikes a balance between mechanical strength and process flexibility, while also reducing material usage and manufacturing costs. It is particularly suitable for mid-range products or cost-sensitive applications. In this study, a comprehensive three-dimensional model was constructed using the finite element method (FEM) to evaluate the effects of different epoxy flux fill heights on solder ball reliability. The simulation was based on a temperature cycling test (TCT) ranging from -40°C to +90°C, with lead-free SAC305 solder as the interconnect material. The model incorporated package geometry, material nonlinearity, and thermo-mechanical coupling to simulate stress evolution and equivalent plastic strain accumulation during thermal cycling. To improve simulation accuracy, material properties and geometric parameters of experimental samples were collected and used for result validation through cross-comparison.
Simulation results showed that when the epoxy flux fill height reached 100% of the solder ball height, it provided optimal mechanical support for the package and effectively limited the growth of equivalent plastic strain. Compared to the unfilled baseline model, the strain in high-stress areas was reduced by approximately 17.2%, as shown in Figure 3. Even at 60% fill height, a noticeable reduction in deformation was observed. These results demonstrate that the local reinforcement strategy can significantly enhance thermal cycling life without requiring full encapsulation. Compared to traditional underfill, epoxy flux offers greater process flexibility and material efficiency, aligning well with future trends in electronic module design focused on high efficiency and low material consumption. In conclusion, epoxy flux, as a new reinforcement solution that simplifies processing while improving reliability, shows great potential for applications in high-frequency and space-constrained conditions. Future research could further explore its material characteristics, fluidity, and thermosetting reaction mechanisms, as well as integrate and compare it with other selective reinforcement technologies such as local underfill or sidefill, to establish a more comprehensive packaging reliability solution.

 

Bio:
NA

Abstract:
With the rapid advancement of high-performance computing (HPC) and artificial intelligence (AI) technologies, large-area electronic packaging - often exceeding 100 × 100 mm²—has become increasingly prevalent. While these large-format packages support higher power delivery and integration density, they also introduce significant reliability challenges, particularly with regard to the durability of the solder joints. A major concern is the degradation of the solder joint during thermal cycling testing (TCT), which replicates the mechanical and thermomechanical stresses encountered in real-world operating and environmental conditions. In such packages, warpage and mismatches in the coefficients of thermal expansion (CTE) among constituent materials can result in severe localized stress concentrations, particularly at the outermost corner solder joints. This study systematically investigates the influence of the presence of edge bonds and its interaction with solder joints under TCT conditions. Three edge bond configurations were analyzed: (1) without edge bond, (2) with edge bond embedded in the substrate but not contacting solder joints, and (3) with edge bond directly contacting the first row of solder joints. Finite element analysis was employed to simulate stress distributions and identify high-risk failure zones for each configuration.
The simulation results indicate that the highest energy concentration occurs consistently at the top of the outermost corner solder joint. This location is especially prone to failure due to exposure to mechanical strain and warpage-induced deformation. In particular, both the absence of edge bonding and the direct contact between the edge bond and solder joints exacerbate energy accumulation in this region, increasing the likelihood of early failure. On the contrary, edge bonding that avoids direct contact with solder joints effectively redistributes stress and shifts the critical energy zone away from the outermost joints. These results confirm that edge bonds function as mechanical buffers, mitigating CTE-induced stress and delaying crack initiation in vulnerable solder joints. However, the efficacy of this buffering depends on avoiding direct mechanical coupling between the edge bond and the solder balls. Direct contact can inadvertently transmit stress rather than absorb it, counteracting the intended stress-relief function. Therefore, the implementation of strategic edge bonds - specifically designed to avoid direct solder joint - can significantly enhance solder joint and overall package robustness during thermal cycling. This insight is particularly valuable for the design of large-area packages in next-generation HPC and AI applications.

 

Bio:
Yuan-Hong Ding is currently a master's student in the Department of Mechanical and Electro-Mechanical Engineering at National Sun Yat-sen University, working under the supervision of Dr. Meng-Kai Shih in the Micro-Packaging Mechanics Design and Analysis Laboratory (MPMDA Lab). He holds a bachelor's degree in Mechanical Engineering from Tamkang University and is currently focusing on research in the field of electronic packaging reliability.

Abstract:
Fan-out packaging has gained widespread adoption in portable electronic products such as smartphones and laptops due to its high I/O density and compact form factor. However, its mechanical integrity under drop impact remains a critical reliability concern, particularly for solder joints. This study investigates solder joint behavior during drop impact events through a two-phase approach combining experimental material characterization and finite element analysis. Initially, uniaxial tensile tests were performed to examine the strain rate-dependent mechanical response of polyimide (PI). The results indicated that both the Young’s modulus and yield strength of PI increased with strain rate, confirming its viscoelastic sensitivity. These material properties were incorporated into a detailed finite element model of a board-level assembly to accurately simulate dynamic drop conditions. Simulations were conducted in accordance with JEDEC standards and validated against published experimental data, confirming the model’s accuracy in capturing solder joint stress behavior.
The validated model was subsequently employed to assess the effects of structural and material parameters on solder joint reliability using response surface methodology (RSM). The analysis revealed that the Young’s modulus of PI significantly influences stress accumulation within the solder joints. Increasing both the modulus and thickness of the PI layer, while concurrently reducing die thickness and the modulus of the epoxy molding compound (EMC), effectively reduced von Mises stress in the solder balls. Based on the RSM-derived optimization framework, the ideal parameter set was determined as follows: a die thickness of 370 μm, PI thickness of 6 μm, PI modulus of 5.4 GPa, underfill modulus of 7 GPa, and EMC modulus of 17.4 GPa. This optimized configuration achieved a 25% reduction in von Mises stress relative to the baseline design, indicating improved drop resilience. Further investigation demonstrated that increasing the underfill modulus to 15 GPa yielded additional benefits, lowering the von Mises stress in the solder region of copper pillar bumps (CPB-SnAg) from 36.2 MPa to 25.8 MPa, and the maximum principal stress in the copper portion (CPB-Cu) from 80.7 MPa to 65.5 MPa—without compromising solder joint integrity. These findings underscore the importance of PI mechanical properties, structural optimization, and judicious material selection in enhancing the drop reliability of fan-out packages. The methodologies and insights presented offer a practical approach to advancing the robustness of next-generation electronic devices under mechanical shock environments.

 

Bio:
Jui-Chang Chuang, also known as Oscar, is a Ph.D. candidate advised by Professor Chang-Chun Lee. His research specializes in mechanical simulation for neutral axis estimation in flexible electronics, warpage prediction in panel-level packaging, and stress distribution analysis in porous metamaterials. He also applies nanoindentation techniques to extract mechanical parameters and investigate energy dissipation behavior in thin films and porous metamaaterial material. He previously worked at TSMC APTS for two years, where he worked on mechanical simulation for advanced packaging and contributed to nanoindentation-based material characterization methodologies. During that time, he held over 2 patents related to TIM material and lid structure. He currently collaborates with ITRI, focusing on mechanical simulation for flexible electronics and panel-level packaging, particularly addressing die-first shifting and RDL mechanical deformation behaviors. He holds over 10 patents about flexible electronics and panel-level packaging.

Abstract:
To address increasing bandwidth demands and the limitations imposed by Moore’s law, advanced packaging strategies are employed, including Chiplet architectures, heterogeneous integration, and co-packaged optics, to enhance power efficiency and data transmission performance in high-performance computing, artificial intelligence (AI), and next-generation Ethernet systems. Glass substrates are selected for their favorable properties, including low dielectric loss, high thermal stability, and a coefficient of thermal expansion (CTE) closely matching the CTE of silicon material, minimizing thermomechanical mismatch at interfaces. Through-glass via (TGV) structures are utilized to enable vertical interconnections for DC and RF signal transmission, supporting high-density and low-loss routing essential for complex multi-chip modules. Moreover, panel-level glass packaging is adopted to satisfy enhancing demands for larger substrate sizes in advanced AI chip designs. On the other hand, TGV plays a critical role in ensuring reliable, high-aspect-ratio vertical interconnects across large form factors. However, during the manufacturing process, conventional measurement techniques are found to be inadequate for capturing changes in residual stress within the TGV regions due to the opacity and complexity of multilayer assemblies. This limitation underscores the need for advanced, integrated measurement and modeling approaches capable of resolving three-dimensional stress fields with sufficient accuracy. Therefore, physical estimation of TGV structures is investigated in this study. Surface optical full-field measurements, including the PhotoStress method and digital image correlation (DIC), are used to capture detailed surface stress and strain distributions on TGV substrates. The PhotoStress method is applied to visualize principal stress differences through birefringent coatings under polarized light. DIC is employed to obtain high-resolution, full-field displacement and strain maps by tracking deformation of a finely applied random speckle pattern during thermal loading. Finite element analysis (FEA) is conducted to simulate internal and depth-direction stress distributions, with realistic TGV geometries, anisotropic material properties, and thermal cycling profiles carefully defined. Experimental optical data and FEA simulations are calibrated and integrated through a hybrid modeling approach. FEA is validated with optical measurement in surface distribution based on lower than 10% difference, enabling the back-calculation of stresses along the blind via sidewalls and in the depth direction. Through this hybrid integration, complex three-dimensional stress fields within TGV structures under thermal cycling are accurately reconstructed. Critical insights into stress concentration zones, failure-prone interfaces, and thermal-mechanical reliability issues are thereby provided to inform advanced packaging design optimization and enhance the predictive accuracy of reliability assessments for high-performance electronic applications. A test vehicle is selected, consisting of a copper-filled TGV substrate measuring 50 mm in length by 50 mm in width, with vias of 30 micrometers in diameter. The aspect ratio is defined as 10 for the TGV sample to represent typical high-aspect-ratio via configurations encountered in advanced glass substrate applications. The TGV sample is prepared with appropriate surface treatments and metallization to ensure adhesion and electrical continuity. Finally, this hybrid modeling approach is considered effective for mitigating the timeline required for the design of large-scale TGV substrates, enabling more efficient evaluation of thermomechanical reliability and interconnect performance.

 

Bio:

2008: Researcher, Inst. Industrial Science, U.Tokyo
2011: Assistant Professor, Dept. Materials Engineering, U.Tokyo
2016: Lecturer, Dept. Materials Engineering, U.Tokyo
2023: Associate Professor, Research and Education Institute for Semiconductors and Informatics, Kumamoto University
2024: Professor
2025: Special Assistant to the President

Abstract:

This paper introduces SCFD (Supercritical Fluid Deposition), a film formation technology that utilizes chemical reactions in supercritical fluids. This technology can form uniform thin films even on deep structures with aspect ratios exceeding 100 and can achieve film formation rate of 10 nm/min, making it promising for application in Cu formation technology for TSVs.

 

Bio:
Professor Oliver Chyan directs the Interfacial Electrochemistry and Materials Research Laboratory at the University of North Texas. With over 30 years of R&D experience, he specializes in resolving critical interfacial materials problems related to high-volume microelectronic fabrication and IC packaging. His current research interests focus on developing novel copper interconnects to enhance performance and reliability.

Abstract:
The exponential growth in computational demands driven by AI, Machine Learning, and data-heavy applications has accelerated the transition toward 3D integration in microelectronics, now seen as a successor to Moore’s Law. As transistor scaling approaches physical limits, 3D integration enables vertical stacking for increased bandwidth, lower latency, and higher density. To meet these demands, high-performance communication between and within processors especially between GPUs and HBM requires robust, ultra-dense interconnects. Cu-solder micro-bumps and Cu-to-Cu direct bonding are key candidates, offering compact form factors, high-speed signaling, and thermal efficiency.
However, Cu’s high chemical reactivity presents a major challenge. Oxidation in ambient and elevated temperature environments forms CuO and Cu2O, which impede solder wetting and atomic diffusion, degrading interconnect performance. Conventional mitigation methods like no-clean flux, formic acid vapor clean, and metal coatings face critical drawbacks: no-clean flux still leaves corrosive residues, formic acid demands complex engineering due to its hazardous nature, and metal coatings add resistivity and processing complexity. These issues limit fine-pitch scalability, yield, and process efficiency, highlighting the pressing need for a cleaner, low-cost, scalable oxidation control method for next-generation 3D packaging.
To overcome this persistent challenge of Cu oxidation, we developed an ultra-thin (~2-5 nm) Cu-selective passivation coating, applied using industry-compatible deposition methods such as CVD or LPD. Notably, the coating maintained its integrity even after two months of ambient storage, proving its long-term stability. It effectively suppressed Cu oxide formation by up to 63% at ~240°C, ensuring a clean, bond-ready surface during high-temperature processes like TCB and solder reflow. In Cu-solder flip-chip assemblies bonded in ambient conditions, the passivation coating enabled robust Cu–Sn intermixing with well-formed Cu₆Sn₅ and Cu₃Sn IMCs, free from voids or delamination (Figure 1(a)). Mechanical reliability was exceptional, with joints achieving 5.16 MPa shear strength, exceeding MIL-STD-883G requirements (~1.5 MPa). Electrical performance was equally strong, with an initial contact resistance of 6.4 × 10⁻⁶ Ω·cm² and negligible drift after 1000 hours at 150°C and 1000 thermal cycles (–40°C to +125°C), along with only a slight increase in IMC growth demonstrating excellent environmental resilience and bond stability.
For Cu-to-Cu direct bonding, the same passivation coating enabled significant oxidation resistance, achieving approximately 56% oxide suppression after 20 minutes at 300°C in ambient air. When bonded under optimized TCB conditions, CMP-treated Cu substrates with the passivation layer yielded average shear strengths of 40.7 ± 4.2 kgf, surpassing the MIL-STD-883 Method 2019.9 requirement (~31.2 kgf for a 0.25 cm² die area). Cross-sectional SEM and EDX analyses confirmed clean Cu to Cu bonding interface with no residual oxides or interference from the passivation coating (Figure 1(b)).
This comprehensive strategy offers a cost-effective and practical solution for the microelectronics packaging industry, with the Cu-selective passivation coating enabling robust, fluxless Cu-solder and Cu-to-Cu interconnects. By effectively mitigating oxidation without sacrificing bond integrity or scalability, it presents a promising integration-ready approach for next-generation, high-density, AI-driven 3D integration platforms.

 

Bio:
Chen-Ning Li is a Ph.D. candidate in the Department of Materials Science and Engineering at National Yang Ming Chiao Tung University in Taiwan, working under the supervision of Professor Chih Chen. His research focuses on low-temperature nanocrystalline Cu bonding for 3D-IC applications.

Abstract:
Cu-to-Cu bonding has emerged as a promising approach for achieving fine-pitch hybrid bonding in heterogeneous integration applications. As bump diameters continue to scale down to the sub-micron level, the use of nanocrystalline Cu (NC-Cu) becomes essential to meet via-filling requirements. NC-Cu is not only the most suitable Cu microstructure for fine-pitch via filling, but it also exhibits exceptional properties that facilitate its application in low-temperature Cu bonding. Leveraging its high grain boundary density, grain boundary diffusion plays a critical role in surface atom rearrangement and interfacial void closure. Moreover, the internal energy stored within grain boundaries can be released during the thermo-compression bonding (TCB), providing a driving force for grain growth across the bonding interface. However, surface oxidation remains a critical challenge, as it hinders atomic diffusion and inhibits interfacial void closure. Therefore, various methods have been investigated to remove native Cu oxide prior to the bonding process, including formic acid vapor treatment, citric acid wet cleaning, and plasma surface cleaning. Although these pre-treatments can effectively remove the native oxide, the subsequent room temperature storage between the cleaning and bonding processes may lead to re-oxidation of the Cu surface. Thus, the processing window related to post-treatment storage time emerges as an important yet underexplored factor that can significantly influence the final bonding quality.
In this work, NC-Cu films were electroplated on a Ti/Cu substrate. The samples were then diced into 1 × 1 cm2 chips and subjected to a chemical mechanical planarization (CMP) process to reduce film thickness and improve surface planarity. Two types of surface pre-treatments, citric acid cleaning and plasma cleaning, were applied to evaluate the post-treatment durability of oxide removal. After surface pre-treatment, the samples were stored at room temperature for queue times of 1 h, 6 h, and 12 h to evaluate the effect of ambient exposure on surface oxidation. The bonding process was then performed at 280 °C under an external pressure of 22 MPa for 1 h. Cross-sectional focused ion beam (FIB) imaging was utilized to evaluate bonding quality by quantifying void size and distribution, while shear tests were conducted to assess the mechanical strength of the bonding interface. By correlating the FIB imaging results with the shear test data, we gained insights into the threshold queue time for different pre-treatment conditions. Additionally, the bonding fraction and void fraction, obtained from the cross-sectional images, showed a clear correlation with the measured shear strengths, suggesting a strong connection between the observed interfacial microstructure and mechanical performance. These findings highlight the importance of controlling post-treatment storage time to ensure reliable bonding performance in low-temperature NC-Cu bonding.

 

Bio:
I am a Chinese-Malaysian currently pursiung a Master's Degree at National Yang Ming Chiao Tung University, Hsinchu. It is my fifth year studying abroad in Taiwan, and had the wonderful opportunity to have Professor Chih Chen as my advisor. My main field of research is on improving the reliability of fine-pitch RDL structures, and aim to develop a thin and conformal passivation coating to inhibit electromigration induced failure. The material of choice here is tin for it's unique capability of forming stable intermetallic compounds (IMC) with copper, which can act as a blockade for atomic diffusion paths along the surface of copper lines.

Abstract:
As the pitch of Cu redistribution layers (RDLs) continues to shrink, challenges such as increased susceptibility to oxidation, corrosion, and electromigration become more pronounced due to the higher surface-area-to-volume ratio and elevated current densities. These stressors can significantly degrade the reliability of the interconnects in advanced packaging technologies. To mitigate these issues, the introduction of passivation or capping layers over Cu RDLs has become increasingly important. Such layers serve as physical and chemical barriers, protecting the copper from environmental and electrochemical degradation, thereby enhancing the overall thermal, chemical, and electrical stability of the RDL structures. Among potential passivation materials, tin (Sn) has emerged as a promising candidate due to its favorable interaction with copper. Upon annealing, Sn reacts with Cu to form stable Cu6Sn5 and Cu₃Sn intermetallic compounds (IMC), which not only prevents further oxidation but also helps restrict surface diffusion pathways of Cu atoms, effectively reducing the driving forces for electromigration. This makes Sn a particularly attractive option for next-generation Cu RDL passivation schemes. However, achieving uniform and conformal Sn coverage, especially on high-aspect-ratio structures, remains a considerable challenge. Conventional deposition methods such as electrodeposition and thermal evaporation often fail to provide adequate coverage on the vertical sidewalls and foot of the RDL lines. In our work, we deposited an 800 μm long, 5 μm thick, 10 μm wide nanotwinned copper (NT-Cu) line on to a RDL die consisting of Ti barrier layer and Cu seed layer with well-defined lithography patterning. Following electroplating, the surrounding Ti, Cu, and photoresist layers were removed using acetone and appropriate etchants to expose the NT-Cu line. To achieve a more conformal passivation layer, a thin Sn film was subsequently deposited onto the NT-Cu line using an electroless plating method. This approach allows for uniform deposition along the top surface, sidewalls, and bottom corners of the Cu line. The NT-Cu RDL was electroplated using a periodic reverse (PR) method, with forward and reverse current densities of 4 A/dm² and -1 A/dm² respectively, using a 40 ms forward and 4 ms reverse cycle. The Sn layer was deposited at various immersion times in a commercial plating solution, maintained at 68 °C and stirred with a magnetic stirrer on a hot plate to ensure uniformity. Cross-sectional microstructure analysis was carried out using focused ion beam (FIB) and scanning electron microscopy (SEM), while surface elemental composition was examined with energy-dispersive X-ray spectroscopy (EDS). Preliminary results show that longer immersion times yield thicker Sn coatings, while at extremely short durations may result in weaker coverage, particularly at the foot of the Cu RDL sidewalls. This suggests that coating conformality improves with immersion time and that total coverage of the structure is possible. Future work will focus on optimizing annealing conditions to promote the controlled formation of Cu₃Sn IMCs and to quantify their thickness across the RDL structure.

 

Bio:
Department of Materials Science and Engineering, National Chung Hsing University, Taichung 402, Taiwan

Abstract:
With the continuous trend toward thinner, lighter, and more compact electronic devices, the development of reliable, low-temperature metal bonding techniques has become increasingly important for advanced packaging. Ultrasonic bonding stands out due to its short processing time, room-temperature operation, and elimination of filler materials, making it a highly promising approach for direct metal-to-metal interconnections. This study focuses on the effects of vacuum ultraviolet (VUV) surface treatment under an oxalic acid atmosphere on Al to Al ultrasonic bonding. The results demonstrated a significant improvement in bond strength for specimens can be achieved when treated with VUV in oxalic acid for a proper duration. This enhancement is attributed to the formation of stable bidentate bonds between the carboxyl functional groups and aluminum surface atoms, which promote stronger interfacial adhesion during ultrasonic bonding. Additionally, the increased surface energy resulting from oxalic acid-VUV treatment contributes to improved wettability and atomic-level contact between the bonding interfaces. It can also be observed that excessive treatment time or high vapor concentration led to the presence of organic residues that were not fully decomposed under the given irradiation conditions. These residues adversely affected the bonding interface by creating contamination layers or voids, thereby reducing the mechanical strength of the joints. Oxalic acid assisted by VUV surface modification offers a promising route to enhance Al/Al ultrasonic bonding by engineering surface chemistry at the molecular level. These insights provide valuable guidance for developing low-temperature, high-reliability bonding processes in future electronic packaging applications.
Keywords: Aluminum direct bonding, Ultrasonic bonding, Oxalic acid, VUV surface treatment

 

Bio:
Dong Jun Kim is currently pursuing a Ph.D. in Mechanical Engineering at the Korea Advanced Institute of Science and Technology (KAIST), South Korea. He received his B.S. degree in Mechanical Engineering from Hanyang University and his M.S. degree in the same field from KAIST. He was recognized with the Student Grant Award for an outstanding presentation and paper at the IEEE Electronic Components and Technology Conference (ECTC). His research interests include the mechanical reliability of thin films used in semiconductor devices, particularly materials such as SiO₂ and SiN. His work focuses on tensile properties, interfacial adhesion, and thermal expansion behavior of these films. CV page : https://jkim111w.wixsite.com/mysite

Abstract:
As semiconductor devices continue to scale down, the mechanical reliability of back-end-of-line (BEOL) interconnect structures becomes increasingly critical for device performance and manufacturing yield. This study presents a comprehensive investigation of interfacial adhesion energies in BEOL structures using the integrated measurement method, double cantilever beam (DCB) fracture mechanics testing to identify the weakest interface and optimize material selection and process parameters. We performed mapping and comparing the adhesion energy results and strain results in the BEOL structure.
We systematically characterized three critical interfaces: Cu–Cap, Cu–IMD (inter-metal dielectric), and IMD–Cap using unified measurement methods. For Cu–Cap interfaces, two different capping materials (Cap1 and Cap2) were evaluated under various surface treatment conditions. NH₃ plasma treatment and consecutive H₂/NH₃ plasma treatments were applied, with treatment effects analyzed through chemical bonding characterization. Results showed that the enhanced surface treatment increased Cu–Si bonding ratios at the Cu–Cap1 interface through the removal of copper oxide layers, thereby improving interfacial adhesion energy. For the Cu–Cap2 interface, the SiH₄ gas treatment between H₂ plasma and NH₃ plasma treatments resulted in dramatic adhesion energy enhancement through selective Si atom incorporation, achieving approximately 260% improvement compared to the baseline treatment. For Cu–IMD interfaces, we compared two IMD materials with different dielectric constants (κ values). IMD1 with lower κ exhibited significantly lower adhesion energy (0.72 ± 0.03, normalized) compared to IMD2 with higher κ (1.47 ± 0.30), attributed to increased porosity and defect densities in low-κ materials that introduce nonuniform bonding characteristics and stress concentration points. The IMD–Cap interface demonstrated remarkable sensitivity to deposition sequence. When Cap2 was deposited first (Cap2–IMD1), adhesion energy was approximately six times higher than the reverse sequence (IMD1–Cap2), with crack propagation shifting from the target interface to the IMD–epoxy interface. Surface energy analysis revealed that the higher surface energy of Cap2 (49.01 mJ/m²) compared to IMD1 (32.54 mJ/m²) enhanced physical adsorption of CVD precursors, explaining the deposition sequence dependency.
Finite element method (FEM) simulation analyzed thermal stress distributions in BEOL structures, identifying geometrically discontinuous regions as vulnerable failure points. Combining experimental adhesion measurements with simulation results, we determined that the Cu–IMD (low-κ) interface represents the weakest link in BEOL structures, with particularly high delamination potential at Cu-filled via sidewalls.
These findings provide critical insights for enhancing BEOL reliability through optimized material selection, surface treatment protocols, and control of deposition sequence. The quantitative adhesion energy database and mechanical analysis will contribute to the development of more robust and reliable interconnect structures for advanced semiconductor packaging applications.
Keywords: BEOL, interfacial adhesion, semiconductor packaging, dielectric materials, surface treatment, adhesion mapping

 

Bio:
Ke-Wei Hsieh is a first-year M.S. student in the Department of Materials Science and Engineering at National Yang Ming Chiao Tung University. He is currently conducting research under the supervision of Prof. Chih Chen, focusing on nanocrystalline copper and low-temperature Cu–Cu bonding for advanced packaging applications.

Abstract:
Copper-to-copper (Cu–Cu) direct bonding has emerged as a highly promising alternative to conventional solder-based interconnects, which often suffer from limited high-temperature reliability, electromigration, and the formation of brittle intermetallic compounds. However, achieving strong Cu–Cu bonding at reduced temperatures remains a significant challenge due to the limited atomic mobility of conventional Cu surfaces.
To address this, we developed (111)-oriented dominant nanocrystalline Cu films that enable low-temperature Cu–Cu bonding. The (111) surface provides high surface diffusivity, low oxidation rate, and strong atomic packing, which together enhance bonding efficiency and promote interfacial elimination. Meanwhile, the nanocrystalline structure offers high grain boundary density and stored energy, which facilitate grain boundary diffusion, grain growth, and intimate contact. This combination enables effective bonding at reduced temperatures, making it well-suited for advanced electronic packaging.
Nanocrystalline Cu films with a strong (111) surface texture were fabricated using direct current electrodeposition with three specific additives—DP115, DP116, and DP117—provided by Chemleader, Inc. Chronopotentiometric (constant-current) electrochemical analysis showed that the incorporation of these additives significantly increased the overpotential, indicating their ability to promote fine-grained microstructures. According to electron backscattered diffraction (EBSD) analysis, the average grain size of the as-deposited Cu films was 132.8 nm, with a (111) orientation ratio of 57.4%, confirming the successful formation of a nanocrystalline, texture-dominant structure.
To evaluate bottom-up filling potential, a rotation speed-dependent electrochemical experiment was conducted to simulate via-filling conditions—where high rotation speed represents the via opening and low rotation speed the via bottom. The potential difference between the two conditions reached 21.5 mV, suggesting the feasibility of superfilling behavior enabled by the additive chemistry.
The microstructure and thermal stability of the as-deposited nanocrystalline Cu films were systematically evaluated. After annealing at 150 °C for 2 hours, the average grain size increased only slightly from 132.8 nm to 145.2 nm, demonstrating excellent thermal stability and resistance to spontaneous grain growth at room temperature. Morphology was further characterized using atomic force microscopy (AFM), while mechanical and electrical properties were assessed via hardness testing and sheet resistance measurements.
Cu–Cu bonding was performed at 200 °C under 22 MPa for 1 hour. Post-bonding annealing at 280 °C for 6 hours was carried out to evaluate interfacial grain growth. The bonding interfaces were analyzed by focused ion beam (FIB) microscopy to examine grain coalescence and migration behavior. Preliminary results revealed significant grain coalescence across the bonding interface after thermal treatment, indicating successful grain-boundary-mediated bonding and the potential for enhanced joint integrity.
To further validate the mechanical reliability of the bonded joints, shear strength testing is planned. Based on the observed microstructural evolution and the high-density grain boundaries in the nanocrystalline Cu, strong interfacial adhesion is anticipated. These findings support the feasibility of employing (111)-oriented nanocrystalline Cu films for low-temperature Cu–Cu bonding in advanced electronic packaging applications.
Overall, this study demonstrates a practical approach for fabricating thermally stable nanocrystalline Cu with a strong (111) surface orientation to meet industrial demands for low-temperature bonding. The results contribute to the development of more robust Cu interconnects suitable for next-generation electronic packaging technologies.

 

Bio:
Lee Kuan Fang origin from Malaysia, is a Principal Engineer of X-Fab Sarawak Sdn. Bhd. (an analog/mixed-signal semiconductor applications foundry). He is responsible for the quality and reliability assessment of wafer products. Bond pad quality and wire bonding process is the area he focused on, as well as electromigration test of the wafer devices. He is also experienced in the investigation of chip assembly failure and failure analysis of wafer level reliability failure analysis. He is involved actively in field quality feedback and investigation of various assembly packaging issues.

Abstract:
Abstract — Long term microelectronic device reliability is important for crucial applications. There is a high percentage of field reliability failure related to wire bond defects. This pointed out that device reliability and system reliability are significantly affected by wire bond reliability. In the scenario of gold wire bonding on aluminum metallization, Excessive intermetallic compound (IMC) growth is a major reliability concern. IMC growth is contributed by gold and aluminum diffusion processes. This is an ageing process that will eventually cause high resistance and open circuits of the product. In this study, aluminum bond pads with various characteristics were carefully evaluated to understand IMC growth behavior. Physical factors such as aluminum layer thickness and grains size are the focus of the study. Gold wire material was fixed during wire bonding for all samples, as well as wire bonding parameter settings. Subsequently after wire bonding, accelerated ageing conditioning was applied to the wire bonded samples. High Temperature Storage Life (HTSL) and Temperature Cycle (TC) are two common accelerated ageing methods for device reliability assessment. HTSL treatment exposed wire bonded samples with continuous high temperatures for a long duration. Meanwhile, TC treatment conditioned the sample between cold and hot environments. Both ageing methods will accelerate IMC growth of Au-Al bonding. Ball bond cross-sectioning was conducted at various phases of HTSL and TC. SEM images were obtained from cross-sectioned samples for close examination of IMC growth patterns. This is followed by a wire bond shear test to evaluate the integrity of Au-Al bonding. The level of IMC growth influenced by aluminum layer thickness and grain size are highly interested in this study. These two characteristics are determined by deposition rate and temperature used in wafer fabrication process. In view of this, data obtained from this study is valuable information for bond pad structure design and improvement activity in wafer fabrication process.
Keywords— Intermetallic growth, aluminium thickness, aluminium grain size, HTSL, TC.

I. INTRODUCTION

Good reliability of microelectronic devices is highly important to ensure long term functionality for crucial applications (such as automotive, healthcare, and telecommunication etc.). It has been reported that more than 30% to 40% of the field reliability failures are due to wire bond failure. Intermetallic compound (IMC) formed during wire bonding process plays a significant role in determine device reliability. [1]
IMC or purple plague is an alloy formed at the interface of gold wire and aluminium bond pad during thermosonic wire bonding. The type of intermetallic compound depends on the temperature of exposure and length of time exposure. Usually, Al5Au2 is the phase that is formed. Nevertheless, many different phases (such as AuAl2, Au5Al2, and Au4Al) are formed in the subsequent processes that involved heat treatment to the wire bonded sample.[2] IMC showing different characteristics in term of electrical resistance, thermal expansion co-efficient and hardness properties as compared to its original form of gold and aluminium. It is necessary for good interfacial adhesion of gold wire and aluminium bond pad. However, it also affects device reliability in two different ways, namely excessive IMC growth and brittle fracture of IMC. At the interface of ball bond, diffusion of gold and aluminium happen in opposite direction into each other to form a compound. However, when one of the atomic species diffuses faster than the other, it leaves vacancies behind. These vacancies may cluster together and form a void. Typically, the voids formed around bond periphery. This may cause high electrical resistance and lead to open circuit failure. The bonding interface will become mechanically weak with the presence of severe voids (such as Kirkendall voids) (Figure 1). Gold-aluminium intermetallic compounds are stronger than the pure metals. Nevertheless, they are also more brittle. When a micro defect exists in the intermetallic and subject to thermal cycling conditions, the crack will propagate at a high speed and causes brittle fracture of the IMC.[3], [5]-[8]

As a source of aluminium, this experiment was focus on bond pad characteristics that might be key factors of IMC growth. Aluminium layer thickness and grain size were included in the study. This information will also serve as important reference for bond pad structure design and aluminium deposition process finalization.

 

Bio:

Shun Mitarai received his B.E. and M.E. degrees from Tokyo Institute of Technology in 1994 and 1996, respectively.
He joined Sony Corporation in 1998, and engaged in the research and development of FeRAM, MEMS, IPD, mm-wave module, and various packaging substrate. He also has 13 years of experience in glass core substrate technology. Current his research interests include advanced packaging for image sensor and related devices.

Abstract:

The increasing size of package substrates presents various challenges, for which glass core substrates are considered a potential solution.

The conventional process (CP) for manufacturing glass core substrates, while maintaining large glass panels, is straightforward but requires significant investment for double-sided interconnect formation and extensive equipment modifications to handle the glass without breakage.
Recognizing CP as a promising method, we propose the Singulated Glass core Embedding Process (SGEP) as an alternative. SGEP addresses the challenges of CP by embedding singulated glass cores into glass-epoxy panels and processing them in this state. SGEP offers advantages such as glass edge protection and device embedding within the same process. However, it also has limitations, including lower theoretical yield and less stringent design rules compared to CP.
This study examines the advantages and disadvantages of CP and SGEP, and highlights the technical challenges and improvements of SGEP. The results indicate that SGEP could be a feasible alternative, potentially expanding the options for panel-level manufacturing methods of glass core substrates.

 

Bio:
Tobias is the business unit leader of the Advanced Electrolytic Plating department at MKS Instruments located in Berlin.

Abstract:
This paper introduces a novel electrolytic flash copper plating system specifically designed to address the unique challenges associated with copper deposition in the modified semi-additive process (mSAP) for printed circuit board (PCB) manufacturing. In the mSAP process, one of the most critical aspects is the effective and reliable plating of buried microvias (BMVs) that are often used in high-density interconnect (HDI) and advanced PCB designs. The primary challenge in electrolytic flash copper plating lies in achieving the right balance of copper deposition: sufficient coverage inside the BMVs to ensure long-term reliability, while avoiding excessive copper plating on exposed glass fibers, copper foil overhang, and uneven BMV hole walls. Additionally, the plating process must accommodate slight variations in the drilling quality of the BMV holes, which can result in uneven hole walls. Addressing these challenges while minimizing surface copper deposition is essential for maintaining the structural integrity of the PCB and maximizing layout density.

FIGURE 1: Low copper thickness on Top for good L/S capability and high copper thickness on bottom for good reliability.

The proposed plating system incorporates a range of innovative control mechanisms to precisely manage copper deposition within the BMVs, ensuring uniform copper coverage throughout the via structure. These advanced controls enable the system to plate copper selectively inside the BMVs, effectively filling and smoothing the via walls, while avoiding too much copper on the PCB surface. This ability to maintain minimal surface plating is crucial for optimizing the high-density layout of the PCB, which is a key requirement in modern electronic devices. Furthermore, the system offers enhanced flexibility in accommodating drilling defects, allowing it to mask minor irregularities in the BMV hole walls with a smooth copper deposition that ensures reliable electrical performance.

In the latest mSAP PCB flash copper plating process, the initial copper foil thickness typically ranges from 1,5-3,5 µm, with an additional 0.35-0.5 µm of electroless copper and 1-3 µm for flash copper thickness. This thin copper layer is crucial for achieving the fine lines and spaces required in high-end HDI boards. Achieving high plating uniformity with reduced copper thickness is technically challenging and requires aligning three key factors: 1) fluid delivery system, 2) electrolyte chemistry, and 3) electrical field control. To meet this goal, the anode box design was optimized for anode segmentation and spray pattern distribution. Another challenge in advanced HDI production with finer lines and spaces is particle control to minimize defects and yield loss. To address this, the entire system has been optimized for particle avoidance and filtration. Additionally, the transportability of particularly thin panels has been improved through sophisticated guiding components.

The new design also emphasizes reducing the consumption of water, chemicals, and electrical energy. Fluid delivery systems were optimized for efficiency by reducing pressure losses. Furthermore, the chamber size was reduced, and components were arranged more smartly, resulting in a reduction in material usage and overall bath volume.

The paper discusses the key design considerations and technical solutions behind the new plating equipment, including the integration of real-time monitoring and adaptive plating control. The results demonstrate improved via reliability, enhanced process control, and superior overall performance compared to traditional electrolytic flash plating methods. This innovation presents a promising solution for the next generation of high-density PCB designs, offering the potential to overcome the limitations currently faced in the electrolytic flash copper plating process.

 

Bio:
I graduated with a Bachelor's degree in Applied Chemistry from National Yang Ming Chiao Tung University. I am currently pursuing a Master's degree at the Industrial Academia Innovation School of the same university. My research focuses on the mechanical properties of electro-deposited copper foils and how microstructure characteristics influence material performance. This presentation highlights a study in which manganese was introduced into the electroplating process, alongside conventional additives, to achieve grain refinement. The goal is to enhance the mechanical strength and thermal stability of copper foils. Our findings demonstrate that this modification significantly improves the reliability and service life of the foils, making it highly relevant for the development of electro deposited copper foil.

Abstract:
Electrolytic copper foils, owing to their excellent ductility, thermal conductivity, and electrical conductivity, has been widely applied in critical fields such as lithium-ion batteries (LIBs), printed circuit boards (PCBs), and chip packaging substrates (CPSs). As LIBs evolve towards higher energy density designs and electronic components become increasingly integrated within circuits, copper foils are required to meet more stringent performance criteria. These include enhanced mechanical strength, thermal stability, and dimensional stability to ensure reliability and long-term durability under high load and miniaturized conditions. Concurrently, with various countries progressively implementing long-term net-zero carbon emission policies, the electric vehicle market is experiencing explosive growth, which in turn raises the performance demands on their core energy systems—lithium-ion batteries (LIBs). Within LIBs, copper foil is extensively used as the current collector for the anode. During prolonged charge-discharge cycles, it must withstand significant internal stresses induced by volumetric changes of the electrode materials. Insufficient mechanical strength often leads to cracking and degradation, ultimately causing battery failures. Therefore, effectively enhancing the mechanical properties of the copper foil has become a crucial research focus to improve the overall stability and reliability of batteries.
In this study, we successfully fabricated both high electrical conductivity and high strength copper foils by using Mn-containing inhibitor. The electrolyte consisted of 0.5 M copper sulfate (CuSO4·5H2O), 80 g sulfuric acid (H2SO4), 30 ppm chloride ions (Cl⁻), 0.5 M manganese sulfate (MnSO₄·H₂O), and an additive ECD108C supplied by Chemleader Corporation. The ultimate tensile strength (UTS) of the copper foil reached up to 679 MPa, representing a 52.6% increase compared to pure copper foils, with an electric conductivity of 77% IACS (International Annealed Copper Standard). After annealing at 400°C for two hours, the UTS remained as high as 302 MPa—68.7% greater than that of the pure copper foil—with IACS improving to 93.8%. Focused ion beam (FIB) analysis revealed that the microstructures under the influence of ECD108C consisted of columnar nanocrystalline twinned copper. The addition of manganese in electrolyte effectively refined the grain size, thereby achieving strengthening effects while also providing outstanding thermal stability.

 

Bio:
Gustavo Ramos is the Senior Director of Business Development & Global Sales and Service at GreenSource Engineering, specializing in wet-chemical process tools, automation, factory engineering, and zero liquid discharge (ZLD) systems for PCB and IC substrate manufacturing. A chemical engineer from the University of São Paulo, Brazil, he has over 20 years of experience in PCB fabrication and assembly. Previously, he held various roles at MKS-Atotech Headquarters in Germany, most recently as Global Product Director for Final Finishing. His expertise focuses on PCB and IC substrate manufacturing processes and equipment as well as sustainable manufacturing solutions. Gustavo has authored and co-authored several publications in the electronics industry over the past years.

Abstract:
The increasing prominence of high aspect ratio (HAR) through holes in printed circuit board (PCB) and integrated circuit (IC) substrate manufacturing is driven by the ongoing evolution of high-performance electronics, including the growing influence of artificial intelligence (AI) and machine learning. These technologies demand unprecedented levels of data throughput, signal integrity, and power efficiency. As devices shrink and component density rises, HAR through holes enable the vertical interconnection of increasingly complex circuit architectures. This is especially critical in high-density interconnect (HDI) structures, where space savings and electrical performance are key.
In AI-driven applications, from cloud data centers to edge computing devices, substrates must support high I/O counts, low-latency communication, and reliable signal transmission across multilayer interconnect stacks. HAR vias are defined by their narrow diameter and deep penetration through thick panels this help meet these requirements by minimizing signal path lengths and reducing parasitic inductance and capacitance. These performance enhancements are essential for AI processors, accelerators, and advanced memory interfaces operating at high frequencies.
In addition to electrical benefits, HAR through holes also contribute to mechanical integrity and thermal reliability. As substrates continue to become thinner and more layered, maintaining structural stability during thermal cycling, such as reflow soldering or operational heating, becomes increasingly important. HAR structures provide mechanical anchoring and consistent connectivity between layers, improving overall reliability in advanced electronic packages.
The increasing complexity of heterogeneous integration which includes the stacking or side-by-side placement of logic, memory, and AI-specific chiplets has further fueled the demand for vertical interconnect solutions. Technologies such as 2.5D and 3D IC packaging rely heavily on precise, high aspect ratio via structures for routing signals between multiple functional components within compact footprints.
To explore fabrication capabilities and process optimization for HAR through holes, this paper presents an evaluation using a novel modular vertical electroplating system developed by GreenSource Engineering (GSE). This electroplating cell is designed to merge the advantages of horizontal and vertical conveyorized plating lines while offering unmatched process flexibility and modular control. The study focuses on 16:1 aspect ratio through holes; specifically, 0.2 mm diameter vias in 3.2 mm thick PCB panels.
Three different current density settings will be applied in a controlled plating sequence to assess process uniformity, via quality, and repeatability. The objective is to determine optimal operating conditions for reliable metallization of HAR vias in a high-throughput, production-relevant environment. By leveraging this advanced vertical plating platform, the study aims to highlight scalable approaches for manufacturing next-generation substrates that meet the performance demands of AI and advanced electronics.
The plating tools uniquely designed compatibility with GSE’s patented closed loop water recycling system will also be touched upon.

 

Bio:
Tim Lin began his career at DuPont in 2022 as an R&D chemist, where he successfully led the development of the LVF-VI-M electroplating product for substrate-like PCBs (SLP) utilizing the mSAP process. In 2024, LVF-VI-M was adopted by the largest SLP mSAP fabricator, marking the introduction of the first DuPont electroplating product in the SLP mSAP field. Tim holds a Ph.D. and a B.S. in Materials Science and Engineering, both from the Georgia Institute of Technology.

Abstract:
In the rapidly evolving landscape of mobile device technology, the demand for high-performance substrates has driven innovations in printed circuit board (PCB) fabrication processes. This paper presents a comprehensive study on the advancements in substrate-like PCB (SLP) and modified Semi-Additive Process (mSAP), focusing on a novel copper electroplating solution known as Microfill™ LVF-7. Specifically designed for mobile device applications, LVF-7 stands out due to its unique structural engineering and formulation that collectively enhance trench via filling and plating uniformity.
The first aspect of Microfill™ LVF-7 is its leveler type, which employs an advanced structural engineering approach to achieve robust bottom-to-top trench filling. This feature is critical in ensuring that the copper plating effectively fills vias completely, thus enhancing the overall integrity and reliability of the PCB. Additionally, the selection of an appropriate carrier type creates a synergetic effect with the leveler, leading to improved uniformity in plating thickness across varying trench dimensions. The intrinsic formulation of LVF-7 guarantees the absence of voids, which is a common challenge in traditional plating processes that compromises the reliability of electronic connections.
Moreover, the one-bath solution designed for LVF-7 significantly reduces process complexity while maintaining excellent trench filling capabilities. This is particularly advantageous in the mSAP process, where precision in plating thickness is paramount. Through a series of rigorous tests and evaluations, the proposed copper electroplating solution has demonstrated superior performance metrics, rendering it a viable option for next-generation substrate designs.
In conclusion, the integration of Microfill™ LVF-7 into the mSAP process not only elevates the quality of substrate-like PCBs but also paves the way for further technological advancements in mobile device fabrication. This paper elucidates the potential implications of these findings on future PCB manufacturing practices and the overall performance of mobile electronic devices.

 

Bio:
Christopher Ryder Christopher has been working in electronics for over 20 years, beginning his career at AT&S Austria, a world leading PCB and IC Substrate manufacturer. Early work in Quality Management led to initial work on industry papers on subjects of process and product reliability for developing technologies (such as embedded components) as well as a role as Instructor for HDI Manufacturing at IPC APEX. As Key Account Manager for a major American Semiconductor manufacturer while at AT&S, Christopher was also part of the company’s transformation from PCB to IC substrate manufacturer and played a role developing new products and markets. Christopher joined ESI in 2013 to lead development of the Geode Via Drilling platform as Director of Product Marketing. Since the MKS acquisition of ESI, he has worked closely with the broad spectrum of resources represented by the corporation to bring the innovative Geode Drilling platform to the market for ever-increasing area of applications. More recently Christopher changed roles to Sr Director of Business Development and relocated to MKS Japan, where his primary focus is growth in the IC substrate and adjacent semiconductor markets.

Abstract:
ABSTRACT
Laser trenching, sometimes referenced as linear laser via (LLV), is an emerging market trend for both the rigid and flexible circuit board application space. Increasingly, it has become a key solution for PCB designers and manufacturers as they look to push the difficult engineering boundaries required for products in the AI server, Low Earth Orbit (LEO), and smartphone application space. Given the steady drive for miniaturization, real estate on printed circuit boards and IC substrates in these spaces are at a premium. Maintaining the end device’s functional performance and total thermal load distribution, while adhering to strict material utilization metrics, reliability-driven quality specifications, and ever-increasing productivity requirements are the core elements of the challenge.

The root of the technology involves canal-like linear pattern ablation of one or more materials through the top of the panelized circuit to the next adjacent Cu layer, or trenches. Trench dimensionality can vary in width and depth, but design characteristics are commonly limited only by manufacturing tool limitations. Trenching is advantageous to PCB designers, as it often utilizes the otherwise unused areas of dielectric between adjacent copper layers and may enable a higher functional density without significant added costs to the manufacturer’s overall process.

While these trenches may have varying functionality in the final product, the technology demands precision in execution to fulfill strict quality specifications. Akin to standard microvias, clean sidewall taper and minimal bottom copper damage are the key quality metrics to consider when developing advanced trenching applications and investing in related processing technology. Specific to LLV drilling, it is crucial to ensure geometric uniformity throughout the trench length including junction points. Given the potential for a significant increase in total laser energy required to create LLVs, an effective thermal management strategy is also required to minimize material damage and heat-affected zone (HAZ). Moreover, as typically more material is ablated versus a standard microvia, productivity is essential to avoid laser-based manufacturing bottlenecks.

In this paper, we will explore ways in which an AOD-based (Acousto-Optical Device) CO2 laser via drilling system equipped with advanced beam-steering and laser power control technology may offer some unique technological approaches to meeting existing and emerging trench geometry specifications. This method allows for unique laser energy displacement and deflection to maintain the high rate of material ablation such applications require, while simultaneously deploying hardware and software-based thermal management strategies for HAZ reduction. Furthermore, through theory-based process simulation and replicated contrast-processes (non-AOD-based), we can gain insight into the building blocks this technology may offer to current high volume manufacturing (HVM) and future product roadmap development.

 

Bio:
Since August 2021: Senior R&D Manager, Desmear and Metallisation (PTH) at MKS Atotech September 2011-July 2021: R&D Manager, Desmear and Metallisation (PTH) at MKS Atotech September 2009-August 2011: R&D Scientist, Desmear and Metallisation (PTH) at MKS Atotech Postdoctoral researcher in computational chemistry at the Humboldt University of Berlin (Germany) PhD in inorganic chemistry at the Universities of Karlsruhe and Regensburg (Germany) MChem in chemistry and polymer science at the University of Lancaster (UK)

Abstract:
Recently, we reported on a smart, nickel-free electroless copper bath specifically designed for ultra-thin (≤ 150 nm) deposits for SAP applications. Although this bath, henceforth referred to as Bath A, is not capable of achieving thicker deposits during conventional plating times as a result of its self-limiting behavior, it does offer other significant benefits such as excellent electrical reliability, throwing power, deposit purity and crystallinity as well as good deposit adhesion to smooth substrates. Furthermore, deposits from Bath A demonstrate a low specific resistance, which is close to that of bulk copper. In view of these benefits and of the fact that the industry is still challenged in efficiently handling electroless copper deposits in the sub-200 nm regime on a mass-production scale, we decided to design a bath system that allows for easy and flexible switching between desired deposit target thicknesses using one and the same fundamental bath formulation. Consequently, by adding a certain moderating component composition to Bath A, the still nickel-free Bath B is obtained, in which the self-limiting feature of Bath A is lifted, and the deposition speed is accelerated. Bath B is therefore capable of blister-free deposition on established build-up films at thicknesses of up to 250 nm using typical plating time durations. To obtain blister-free deposits with thicknesses greater than 250 nm, one can use Bath C, which is prepared by simply adding nickel to Bath B. Since all three baths are based on the same fundamental composition defined by Bath A, enhanced throwing power, deposit purity and crystallinity as well as conductivity are ensured for all three baths. We expect Bath C to meet current and near-future industry requirements regarding electroless copper deposit properties including thickness. Thinner deposits with increasingly better conductivity can be readily accomplished by just “switching off” the nickel and the moderating component composition supply in succession, which will allow the easy transition to Bath B and finally to Bath A. Baths A-C thus constitute a modular electroless copper bath system, which is suitable for immediate deployment and is also future-ready. We expect this bath system will offer the industry unparalleled flexibility, agility and adaptability as it transitions to a state in which it is able to handle thinner and thinner electroless copper deposits on a mass-production scale.

 

Bio:
Carmichael Gugliotti has 12 years of experience in the PCB industry working at MacDermid Alpha Electronic Solutions based in Waterbury, CT. Carmichael currently is a Global Product Manager for Primary Metallization, prior to this he was the Applications Manager, Applications Specialist and R&D Chemist in the Metallization division. He holds a Bachelor of Science in Chemistry from the University of Connecticut and an MBA from Quinnipiac. He has worked on new metallization technologies for both primary and secondary metallization’s such as electroless copper, direct metallization, and acid copper plating.

Abstract:
The fabrication of a functional printed circuit board (PCB) is a complex, multi-layered process that plays a critical role in the modern electronics industry, an industry valued at $2.5 billion in 2024 (Prismark data). A key step in PCB manufacturing is metallization, specifically the process of making drilled holes conductive. Traditionally, this has been achieved using electroless copper deposition. However, direct metallization technologies based on carbon or graphite have existed as niche alternatives for over two decades, often limited by concerns regarding reliability and broader market acceptance.
In recent years, advancements in colloidal chemistry and process engineering have significantly improved the stability, performance, and sustainability of carbon- and graphite-based direct metallization systems. These innovations include more consistent colloidal dispersions, enhanced wet etch techniques, and superior coating uniformity, all contributing to a substantial reduction in void formation. These improvements enable direct metallization to meet the stringent quality and environmental standards demanded by today’s high-density interconnect (HDI) and advanced packaging applications.
This paper explores the evolution of colloid science in PCB manufacturing, detailing how next-generation carbon and graphite processes offer a more reliable and environmentally friendly alternative to traditional electroless copper. The result is a more viable metallization method better suited to meet the increasing performance demands of today's and tomorrow’s electronic applications.

Key words: Direct Metallization, Carbon, Graphite, Reliability, SEM, FIB, Ion mill, Coating, Colloid.